Design of MOS-translinear Multiplier / Dividers in Analog VLSI

A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-1am CMOS process, are provided in order to verify the correctness of the proposed approach.


INTRODUCTION
The area of analog multipliers constitutes a field of active research due to their wide applicability in analog signal processing.Frequency transla- tion, phase detection, correlation, convolution, adaptive filtering, etc., are usually achieved using these circuits; moreover, novel applications are steadily increasing this already extensive list, e.g., Square-Root Domain companding systems [1].
Nevertheless, most of existing proposals are designed for voltage-mode applications, and the availability of general-purpose current multipliers in CMOS technology is still modest [2].
In this paper, a novel approach for designing current-mode analog multiplier/divider circuits is presented, based on the cascade connection of a geometric-mean circuit and a squarer/divider circuit.The resulting topology is very well suited for being fully implemented in standard CMOS using MOS-translinear (MTL) loops, as will be evidenced subsequently.It can be successfully applied to a wide range of different analog systems, featuring simplicity, favorable precision, an area-efficient implementation due to the fact that only MOS transistors are employed, and wide dynamic range originated from the current-mode approach followed.In addition, insensitivity to temperature and process variations is inherited from its MOS-translinear nature.

BASIC PRINCIPLE
A simple procedure for obtaining a current multi- plier/divider is to generate a current which is the geometric-mean of two currents Ix and Iy, i.e., lgm k lklxl (1) being k a nonzero arbitrary constant; if this current is injected into a squarer/divider circuit having the following input-output characteristic: lout-li2n (2) kZlw then the squarer/divider output will be given by the expression k21w (3) that can be equivalently written as lout Ixly (4) Iw Hence, according to (4), a current-mode multi- plier/divider could be obtained by this simple method.This idea is shown in Figure 1.
Since Eqs. ( 1) and ( 2) are inverse one each other, it can be expected that both could be implemented in practice using the same basic topology, by just interchanging input by output and properly adapting the input and output impedances.A general approach to the design of the required blocks using MOS-translinear techniques will be provided in the next section.

MULTIPLIER/DIVIDER DESIGN
Both squarer/divider and geometric-mean cells can be obtained by using either the stacked or folded second-order MTL loops shown in Figures 2a  and 2b, respectively.In both cases, applying the KVL to the loop and assuming MOS transistors operating in saturation and having equal trans- conductance factors and threshold voltages, the g-mean  following expression is obtained: being Ii and Wi/Li the drain current and aspect ratio, respectively, of transistor Mi (i= 1, 2, 3, 4).
The folded topology has some important advantages, not the least of them being the possibility of decreasing the supply voltage re- quirements (if a proper biasing is applied), and alleviating the VTn mismatch due to the bulk effect that adversely affects the stacked topology if tech- nology precludes the connection of MOST source terminals to their bulk terminals (i.e., NMOS loops in n-well technology).
If the following aspect ratios are chosen L3 L4 L L2 being k a positive constant, and the strategy for injecting currents into the MTL loop is such that k 2 (I1 + 12) + 2kI5 13 14 4 (7) for a certain current 15, the following relationship among 11, 12 and 15 is revealed after squaring both sides in (5) and rearranging, 15 kv/2 (8) Therefore, a geometric-mean circuit is obtained if 11 and I2 are the input currents and the output current is a copy of 15.Alternatively, a squarer/ divider is obtained if the output is a copy of either 11 or I2 and the inputs are the remaining two currents, being, respectively, I1 k2/2 or 12 k2ii (9) Table I illustrates four possible designs which result from combining the two proposed kinds of MOS translinear loops, and two values for the k parameter previously introduced.A number of different practical circuits result by using different values for k, and by implementing alternative schemes for current injection into the four-transistor MOS-translinear loops.Also, PMOS and/or NMOS loops can be used depend- ing on the available technology.Note that the choice of the current injection strategy is far from trivial, since it has an strong influence in the area occupied, power consumption and potential for low-voltage operation.Some of the multiplier/ dividers achievable, according to the schemes in Table I, will be presented subsequently.Using the blocks shown in the first row of Table I in the diagram of Figure 1, a version of the multiplier/divider is constructed; the detailed schematic of the circuit thus obtained is shown in Figure 3.The MOS-translinear loops of the geometric-mean and squarer/divider circuits are formed by (PMOS) transistors M1A-M4A and M1B-M4B, respectively; the bulk terminals of these transistors are connected to their sources, thus avoiding the bulk effect.Note that the relative aspect ratio of these transistors is determined by the choice for k employed, according to (6).
M7A_ B and M20A_ B are diode-connected tran- sistors included for alleviating the channel-length modulation effect in M1A-B and M2A-B, respec- tively.Transistors M5A-B--M6A-B form simple current mirrors, and MSA_B--M19A_ B constitute high-swing cascode current copiers employed for injecting the required combinations of currents into the MOS-translinear loops.The middle current mirror formed by transistors M-M4 is employed for inverting the output current of the geometric-mean block in order to be properly introduced into the squarer/divider.Note the simi- larity of the geometric-mean and squarer/divider blocks employed, which is beneficial in terms of matching between both blocks, thus improving the multiplier/divider performance.
3.2.Folded MTL Loop; k 1 As mentioned elsewhere, the stacked topology of Figure 2a suffers from the bulk effect if technology does not allow an independent connection of the bulk terminals; this can seriously affect the loop behavior.This shortcoming is greatly alleviated using the folded MOS-translinear loops shown in the second row of   injecting the loop currents is shown in the circuit of Figure 4.The folded MOS-translinear loops are formed by transistors MA-M4A and MB-M4B; since k in (6), the loop transistors are equally sized.The remaining transistors constitute current copiers that inject the appropriate loop currents.
A similar voltage supply than the stacked topol- ogy is required, due to the stacking of diode- connected transistors employed, thus not fully exploiting its low-voltage capability.An alterna- tive way of injecting the loop currents is shown in the multiplier/divider of Figure 5, allowing to operate at a supply voltage as low as one Vs plus two VDs of a saturated MOST.This is achieved by avoiding diode-connected transistors at the sources of the loop transistors (shaded areas).V keeps the biasing transistors at the bottom in saturation for any input currents.

SIMULATION AND MEASUREMENT RESULTS
The multiplier/dividers of Figures 3 and 4 were fabricated on a monolithic IC using a n-well 2.4-gm CMOS process.The circuit of Figure 3 was firstly tested.The aspect ratios chosen are shown in Table II.Supply voltage was VDo 5 V, and VcN=2.3V. Figure 6 shows the measured multiplier/divider DC characteristics obtained for Iw 10 gA, Iy values ranging from 0 laA (lower line) to 10gA (upper line) in 2.51aA steps and Ix swept from 0 to 100gA.The good linearity obtained is readily noticeable.
The measured output THD at 10 kHz, for an input sinusoid with DC component Ioc 50 laA, was well below 2% for input peak amplitudes as large as 45 gA.Iy and Iw where set to 10 gA for this measurement.
Subsequently, the circuit of Figure 4 was tested.The aspect ratios chosen are offered in Table III.When compared to the circuit of Figure 3, a certain loss in dynamic range is observed since a 3.3 V supply was employed; VcN was set to 1.5 V.
Figure 7 shows a microphotograph of the circuit; the area occupied is 0.19mm2.In Figure 8, the measured DC characteristics are shown; Iw was kept to a constant value of 15 laA, whereas Ix was stepped from 15 gA to 40 t.tA in 5 t.tA steps and Iy was swept from 0 to 25 gA.  10 kHz is less than 2% for input sinusoids having peak amplitudes .aslarge as 101aA, and a 11 DC component.
A four-quadrant multiplier can be readily obtained from the above multiplier/divider circuits by using a couple of them in a balanced structure.This configuration was only simulated due to the lack of two separate multiplier/dividers on the same chip; the multiplier/divider shown in Figure 5 was employed for these simulations.A 1.5V operation could be obtained using models from a 0.7-gm CMOS process; the basic aspect ratios employed were (30/4) and (60/4) for the NMOS and PMOS transistors, respectively.Figure 9 shows how such balanced version can be employed as an amplitude modulator.Ix was 10(1+ 0.5 sin(27rft))laA, with f= 10 kHz, whereas Iy was the modulating waveform, corresponding to a triangular periodic wave; Iw was set to 10 laA.
based on the cascade connection of a geometricmean block and a squarer/divider obtained using essentially the same cell (a simple second-order MOS-translinear loop).Measurement results of two versions of the circuit have been offered, confirming in practice the feasibility of this ap- proach.The precision and simplicity of the result- ing topologies make them suitable for being applied in a varied repertory of analog VLSI circuitry, in areas such as analog neural computation and analog fuzzy hardware.The performance of the multiplier/dividers proposed here is quite similar in terms of linearity and dynamic range to other proposals based on the MOS-translinear principle, e.g.[6].Nevertheless, the circuits proposed here employ just a couple of MOS-translinear loops, whereas in [6] three loops are required, thus un- necessarily complicating the design and leading to an increase in power and area consumption.

CONCLUSIONS
A novel approach to the design of analog multi- plier/divider circuits has been presented, which is FIGUREPrinciple of the multiplier/divider circuit.

FIGURE 6
FIGURE 6 Measured DC transfer characteristics of the multiplier/divider of Figure3for different bias currents.

TABLE
Some possible building blocks for the multiplier/divider Geometric Mean, lou k// Squarer/Divider, lou I/k211,2 Table II as the required blocks of the multiplier/divider.A possible way of

TABLE II
Transistor aspect ratios in the circuit of Figure3*

TABLE III Transistor
aspect ratios in the circuit of Figure4*