Configurable 2-D Linear Feedback Shift Registers VLSI Built-in Self-test Designs

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.


INTRODUCTION
Ever-increasing VLSI circuit density has made today's chip testing more complicated and costly.
Built-in self-test (BIST) has been proven to be an effective approach to achieve sufficiently high, if not complete, fault coverage without any external automatic test equipment on site.It has revolu- tionized the way the integrated circuit chips can be tested by (1) reducing the cost of manufactur- ing testing by shortening the test application time, (2) minimizing the amount of test data stored, and (3) lowing the cost of test equipment.The Corresponding author.implementation of BIST can result in a reduc- tion of the product development cycle and cost, and the cost of system maintenance can be signifi- cantly reduced by testing chips, boards, and the entire system virtually using BIST.Typical BIST architecture consists of a test pat- tern generator and a test response analyzer.The efficiency of BIST implementation can be char- acterized by test length and hardware overhead for a given fault coverage requirement which is defined as the ratio of the number of faults that can be detected to the total number of faults in the assumed fault domain.It is expected that BIST insertion to integrated circuit chips will result in high fault coverage, small volume of test data, at-system test speed, and compatibility with the design for testability techniques.High fault cover- age can be achieved only if all faults of interest are detected and their effects are retained in the test response analyzer.
There have been various BIST techniques based on pseudo-random testing [1,9], pseudo-exhaus- tive testing [2, 10, 11], weighted random testing [3,12,13], and reseeding of LFSR [5][6][7].These approaches offer different trade-off among test data volume, test application time, hardware overhead and fault coverage.One of the most popular approaches is the pseudo-random BIST, which employs an LFSR to generate a large num- ber of test patterns with small hardware over- head.The major limitations with this method are the long test time and low fault coverage.Several approaches have been proposed to overcome these disadvantages, most of which embed a set of precomputed test vectors, called deterministic pat- terns, to reach high fault coverage within a shorter time.Such deterministic patterns can be obtained by an automatic test pattern generation (ATPG) and implemented with a ROM to store the patt- erns, or the traditional LFSRs with pre-designed seeds to generate the patterns.
Recently, another method was presented to realize both pseudo-random pattern generation and deterministic pattern embedding using a 2-D LFSR [8].With the two-dimensional feedback algorithm, it can achieve higher fault coverage than the conventional LFSR due to improved randomness.However, the hardware overhead is much higher than conventional LFSR for some practical circuits.In this paper, our focus is to reduce the hardware overhead by proposing a configurable 2-D LSFR based BIST scheme.very small area overhead that is composed of exclusive-or gates (XORs) and flip-flops (FFs).
The general structure is shown in Figure 1, which can be expressed with the polynomial in Eq. (1).

P(V)
q--C1V -+-C2V 2 --+ CM-1 g M-1 q-g M (1) The coefficients Ci(i= M-1) are zero or one.An LFSR goes through a cyclic sequence of states and the outputs produced are also periodic.The maximum length of this period is 2 t-1, where M is the number of stages.So the patterns generated by an LFSR are pseudo-random and the random properties depend on its initial state and its generating function P(V ).Once the generating function and the initial state are fixed, the patterns produced are also determined and in one period there is no recurrent patterns.It cannot produce a sequence of deterministic ordered patterns.The fault coverage is usually low because the random- pattern-resistant faults exist in some logic struc- tures that can be detected only by deterministic ordered patterns.A number of the LFSR based techniques [5][6][7] have been developed to generate deterministic ordered test patterns to detect the random-pattern-resistant faults, but the encoding and decoding procedures and the implementation of control logic are relatively complex.A 2-D LFSR structure was presented in [8], which can first generate a deterministic sequence used to detect random-pattern-resistant faults, followed by random patterns used to detect a large percent- age of easily testable faults.Figure 2 shows the gen- eral representation of a 2-D LFSR based on N primitive polynomials:

2-D LINEAR FEEDBACK SHIFTER REGISTERS
A conventional LFSR can be used to generate a large number of pseudo-random test patterns with This circuit consists of N shift registers, each of which has M stages.Vi(i N ) represents an N- bit vector, and ViDk(k--M) represents the kth delay of a vector Vi.Vi is generated by the feedback network given by Eq. ( 2).signal V#D k is connected to the XOR gate to generate Vi.Otherwise, there is no connection.If Ci 0, the output of the XOR gate is connected to the shift register directly.If Ci--1, then an inverter is added to the input of the shift register for gen- erating a complementary feedback signal.Given L vectors with a length of N-bit, V1 bll, b12 b13,..., b V2 621, b22, b23,..., b2L VN bN1, bN2, bN3,..., bNL.
To store these vectors in a 2-D LFSR with minimum stage M, we construct Eq. ( 3) and ob- tain the solutions including determining the mini- mum value of M by using the branch and bound method.

7=1
where Vi(n)hi,n, Vj(n k)-Vj(n)D i-1 N and n-1 L. When solving the first vector Vi(1), Vj.(1 k) represents the initial states of the 2-D LFSR.A procedure to solve Eq. ( 3) is described below: M-1; /w M is the index count of time frame expansions w Set initial states of 2-D LFSR; While (aijk's for any signal Vi are not found) { if (a,j's for each signal Vi are found) return; for (each unsolved Vi signal) { Build_Equations;/, Formulate Eq. ( 3) and set Ci--0 Besides embedding the deterministic sequence, the 2-D LFSR can generate better pseudo-random patterns than a conventional LFSR according to the experimental results in [8].The longer the deterministic sequence is, the more stages of a 2-D LFSR are required, which means more hardware required.For some practical circuits, a large over- head is unacceptable.In the next section, a fea- sible configuration scheme based on a 2-D LFSR to reduce the overhead is proposed.generator is proposed to generate an embedded deterministic sequence of test patterns followed by pseudo-random patterns.The generator mainly consists of four types of function blocks-the flip- flop array (FFA), the configuration network (CN), the multiplexers (MUXs), and the control unit (CU) as shown in Figure 3.The FFA is an N x M flip-flop array, where N is the number of inputs of a circuit under test (CUT) and M is the number of stages of the 2-D LFSR.In order to reduce the hardware, M is usually a small number.If Eq. ( 3) cannot be solved with a small value of M, the embedded test sequence is then partitioned into subsequences for obtaining solutions for a config- urable scheme.Each CN consists of XOR gates and an inverter if necessary.The MUX block selects one of the p configuration networks and feeds the feedback signal to the N-input FFA, where p is the number of configurations.The MUX block is controlled by [logzp] signals as shown in Figure 3.A relatively simple CU gen- erates these signals for the MUX and a reset sig- nal for the FFA.When resetting the generator, the initial states of FFA are set to (1010...} in each column of the FFA.
The synthesis procedure for a configurable 2-D LFSR is shown in Figure 4 with two main tasks: (1) find a set of deterministic ordered patterns and (2) embed these patterns in the configurable 2-D LFSR.The HITEC [4] is used as an ATPG tool to generate a set of test patterns for detecting random-pattern-resistant faults.For some circuits, however, it is hard to find test patterns to detect random-pattern-resistant faults only.Therefore, all faults including random-pattern-detectable and random-pattern-resistant faults are considered in ATPG.With the test patterns generated by the ATPG, the coefficients aijk'S in Eq. ( 3) is solved so as to generate the sequence of test patterns.The number of stages, M, in the 2-D LFSR reflects the hardware complexity.Given a small number of M, Eq. ( 3) is sometimes not solvable; therefore, a modified algorithm is needed.For example, par- titioning the original sequence of test patterns into consecutive subsequences of test patterns and then solving Eq. (3) for each subsequence becomes a feasible solution.As the length of each sub- sequence decreases, Eq. ( 3) can be solved with an acceptable small number of stages.While the num- ber of LFSR stages decreases by the partition- ing sequence, the complexity of the configuration network increases.Hence, it is necessary to opti- mize the configuration network for a less cost.The following is an example to show the number will be 5 without the configuration effectiveness of the configurable 2-15) LFSR based structure as shown in Figure 6.The initial patterns generator.Given a deterministic ordered sequence of both generators are shown in Figures 5 and 6. with 18 6-bit patterns with the initial seed The first test pattern (101001) in this example is (101010), generated with the initial pattern (101010) feeding tl t2 t3 t4 t5 t6 t7 t8 t9 tl0 tll t12 t13 t14 t15 t16 t17 t18 1: 0 0 0 0 0 0 0 0 0 2: 0 0 0 0 0 0 0 0 0 0 3: 0 0 0 0 0 0 0 0 0 0 4: 0 0 0 0 0 0 0 0 0 0 5: 0 0 0 0 0 0 0 0 6: 0 0 0 0 0 0 both a configurable generator and a non-config- through the configuration network CN1, and then urable generator are designed.Figure 5 shows the is shifted into the 2-D LFSR.Other patterns schematics of the generator with 1-stage registers are generated in sequence by following the same and two configuration networks, whereas the stage procedures until the ninth pattern (110100) is 1 RandomTest Patt'ern's' Genratlon generated.In this configurable generator, the CN1 generates the first 9 patterns, 101001 ), (011100), ( 111111), (001111), (010111}, (000001), (010010}, (111010) and (110100).The CN2 generates the other 9 patterns, (100011), (001001), (001111), ( 110111), (000011}, (100000), ( 101001), ( 100110) and (010001).The tenth pattern is generated with the ninth pattern (110100} feeding through the CN2.The CU with a modulo-9 counter controls this switch.With the optimization on the feedback network of Figure 5, an optimized configurable 2-D LFSR is shown in Figure

EXPERIMENTAL RESULTS
Five synthesized circuits are used as benchmark circuits to evaluate the configuration structure in the 2-D LFSR scheme.The characteristics of the five circuits are summarized in Table I.Am2910 is a 12-bit microprogram sequencer, which has a stack of depth 5, a stack pointer, a microprogram counter, and a register counter (down counter).A  address from either the input data bus, the stack, the register counter, or the microprogram counter.Multl6 is a 16-bit 2's complement multiplier, which uses a shift-and-add algorithm.The control unit has been implemented using 3-bit and 4-bit counters.There is one start instruction.Divl6 is a 16-bit divider that uses repeated subtraction to perform division.A zero-detect unit checks for the divide-overflow condition and flags the termina- tion of the repeated subtraction loop.There is one control instruction: Start.Pcont2 is an 8-bit parallel controller used in DSP applications.This circuit is composed of 8 adders, 2 fixed-point multipliers, and 3 MUXs-all combinational logic.Three registers serve as delay elements.A global reset line resets all the registers, and new data is input at every clock cycle.There is no control unit.Piir8 is an 8-point infinite impulse response filter for DSP applications.It has a very regular structure with 7 adders, 8 fixed-point multipliers, 7 8-bit registers, and 7 2-to-1 MUXs.
The data input and output buses are 8 bits wide.
There is no control unit.A global reset line is the only control signal.In Table II, the configuration and the original non-configuration results of the five benchmark circuits are compared.The first column is the number of embedded deterministic patterns detecting the random-resistant faults for each circuit.The second and third columns give the stage number of shift registers and the total number of flip-flops for the non-configurable test generator.The number of configurations, the stage number of shift registers and the total number of flip-flops for the configurable 2-D LFSR based generator are given in the fourth, fifth and sixth columns.For the am2910 and mull 6 the flip-flops are reduced significantly to 15% and 14% re- spectively.Because the number of embedded pat- terns for divl6, pcont2 and piir8 is small, the synthesis procedure results in no reconfiguration.
Compared with the other four circuits, divl6 has the largest FFA due to its large number of inputs.
The minimum stage number of M can be obtained by increasing the loop times in the branch and bound algorithm while solving Eq. ( 3) at a cost of CPU time.Table III shows the comparison of the fault.The test patterns generated by HITEC can be either stored in a ROM or scanned in.The results of the conventional LFSR generator are listed in the third column.Column four gives the results from a combination of the conventional LFSR and the additional deterministic ordered patterns.The data in the fifth and last columns are obtained by the 2-D LFSR and the configurable 2-D LFSR based generators respectively.The average number of equivalent faults of five cir- cuits is 9,441 where 3,955 faults are detected by "HITEC" and 6,054 faults are detected by "Random Patterns".Comparing "LFSR", "LFSR / Add", and "2-D LFSR", the experimen- tal results show that the average detected faults by "2-D LFSR" is 5.08% higher than that of "LFSR+Add" and 8.65% higher than that of "LFSR".Note that the average number of faults detected by "2-D LFSR" is 5,952, which is only 1.76% less than that of "Random Patterns".The average number of faults detected by "Configur- able 2-D LFSR" is 5,986, which covers about the  LFSR and a procedure to design a test pattern generator have been presented.Without storage of test patterns and seeds, the 2-D LFSR test pattern generator can generate a sequence of deterministic test patterns as well as pseudo-random patterns.
The hardware overhead of this BIST scheme decreased considerably through configuration.
The experiment result shows that compared with the non-configurable 2-D LFSR, the number of flip-flops is reduced by 79% for five synthesized circuits.The average number of faults detected by the configurable 2-D LFSR is 9.27% higher than that of the conventional LFSR and 0.57% higher than that of the non-configurable 2-D LFSR.
In order to improve the fault coverage of the configurable 2-D test pattern generator, a set of embedded deterministic patterns with high fault coverage is needed.Logic optimization tools are also necessary to further reduce the hardware overhead of the feedback networks.

FIGURE 2
FIGURE 2 Two dimensional LFSR structure.

TABLE III
detected faults as the 2-D LFSR generator, but the overall overhead of the FFA has been reduced by79%.