Simultaneous Switching Noise Minimization Technique Using Dual Layer Power Line Mutual Inductors *

A novel technique for minimization of simultaneous switching noise is presented. Dual Layer Power Line (DLPL) structure is newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is halfdivided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly minimize the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.

INTRODUCTION In today's CMOS VLSI, more and more high- density and high-speed I/O buffers are required, to switch large number of drivers at the same time.
As a result, simultaneous switching noise (SSN) or 'supply bouncing', which comes from a parasitic inductance of power lines, is also becoming significant [1][2][3][4][5][6][7].The output pad buffers are the main contributors of the SSN because of large switching currents that change very fast flow through the parasitic inductance at the bonding wire and packages [1 2].
A typical output stage of a pad driver is shown in Figure 1.There are the parasitic inductor, resistor and capacitor along the power line, pad, bonding wire and pin package path.Generally, the parasitic resistor is neglected because it's compar- ably small [1].In the worst scenario, if the peak magnitude of SSN exceeds the threshold voltage of the transistors, then it causes malfunction of the circuit.Therefore, more accurately and, more importantly, to mini- mize SSN in the output drivers [1,2].
There have been a number of formulae proposed for modeling and minimizing the SSN [1][2][3][4].Yang [1] and Jou [3] presented optimized output buffer circuit in constraint of SSN magni- tude or transition time.Song [2] presented a new modeling for the SSN.Spurlin [4] proposed a serpentine transistor layout technique to reduce current variation with respect to time at cost of silicon area for extra switching circuits.
In this paper, we propose a new solution for the SSN, Dual Layer Power Line (DLPL) technique that can be implemented by adopting a simple power line strategy without causing any extra cost either in layer number or in silicon area.In Section 2, a brief description of the SSN is given and an analytical expression of the DLPL dynamics is derived.In Section 3, DLPL mutual inductor implementation technique on silicon is illustrated.Finally, conclusions along with future works are given in Section 4.

SSN MINIMIZATION THEORY
Figure 2 depicts two power line parasitic inductors of the typical CMOS output drivers.Suppose inputs Vin switch simultaneously, then a sudden current change will be induced in the power line generating the SSN.
The switching noise (Vn) at node A is defined as [1] Vn nLvss d- (1) where n is the number of simultaneously switching drivers and I is the current flowing through one buffer.Here we only consider the Vss power line case and the SSN of the VDD can be explained in the same way.
Figure 3 shows the SPICE simulation of the SSN in Eq. ( 1).As can be seen the SSN peaks at t ns with the highest of 2 volts with n-100 case.Note here the SSN level is considerably high enough to disrupt the chip function.
Basically, the proposed technique Dual Layer Power Line (DLPL) adopts well-known mutual inductor dynamics into power lines on silicon.
Figure 4 shows the schematic of the DLPL with mutual inductors, here functionally same as transformers.L vss and Uvss represent primary and secondary inductors, respectively.
Figure 5 shows this mutual inductor model in the ground line.Power line (VDD) can also be modeled in the same way and not dealt in this work.Here I represents a time-varying current in Eq. ( 1), which is same as is.Two inductors, L vss and Lvss, are electro- magnetically coupled being separated by a very thin insulator such as silicon-nitride or silicon- dioxide.In this scheme, we know that dis Vn Lvss-+ M d-- v'. vs -+ M d-; Vn Lvss' VSS is -Self current flow direction it Induced current flow direction The coupling coefficient, k, indicates the degree of coupling between two inductors, which is defined as, M v/Lvss Uvss where M is mutual inductance [6].If ideally, L vss and Lvss are perfectly coupled and same size, k equals 1.That means that Eq. ( 4) becomes M -Lvss Lvss. (5)  In Figure 5, if node A and node C connects with D and B, respectively, then we have Vn--V n.
Combining Eqs. ( 2) and (3) now yields, Vn + Vn Lvss-+ M--( di, dis ) + Lvs s--+M---0 (6)   Putting Eq. (5) into Eq. ( 6) we have + --O. (7)  Therefore, ii is to be -is, resulting, Eqs. ( 2) and (3) be as follows, v. v 0 (8) So, when k= 1, the SSN can theoretically be eliminated as an ideal case.In reality, however, k cannot be 'one', but we know this will minimize the SSN, Vn and V n" In order to prove DLPL technique, SPICE simulations are used with a 150pF CLOAO, 2nil inductance, and with Ins rise time input.Figure 6 shows the SPICE simulation result, which is compared with [2] (noted as 'SONG') and 'SPICE' with a conventional power line scheme.As seen, about 63% SSN reduction was obtained.
Figure 7 shows the cases of the values of k with 0.8, 0.9 and 0.999 for 36 drivers.'SSN' in the figure presents the switching noise of conventional power scheme.These mutual inductors, or transformers, in power lines are very easily realized by dual layer power line (DLPL) technique, that will be explained in the following Section 3.   It consists of two stacked power lines.Insulator such as silicon-dioxide, silicon-nitride or others (larger dielectric material is preferable for a larger k) fills the space between DLPL.It was reported in [7] that with a reasonably feasible thin insulator thickness in current CMOS technology, the coupling coefficient, k can be increased more than 0.88.For DLPL structure, there is no need to use special fabrication process.This DLPL is realized by a standard CMOS double metal process.Using a double metal process it should not be too difficult to make dual layer mutual inductors.
In order to realize this mutual inductor com- posed by DLPL, we need to apply a new power line strategy as shown in Figure 9. Drivers are divided, thus without any size overload, in two same half-sized buffers.Such as, dotted box in the Figure 9 corresponds to one buffer with channel width W= 600 tm that is composed of two same- sized W--300 lxm buffers.Here, one power line is connected at "IST Line" and the other is connected at "2ND Line" of the DLPL.Now, the buffer composed of two half-sized small buffers handles two opposite-direction in- stant currents of same amount at the same time.
Here we assume probability density functions of switchings, at individual buffers of the dual power lines, are same, which is reasonably acceptable with a large number of I/O drivers in current high- speed digital logic.This is because SSN only occurs when many output buffers are simulta- neously switching.Therefore, with our assump- tion, we can apply that two currents in DLPL are almost same with only opposite direction, satisfy- ing Eq. ( 7).
One driver layout using the proposed DLPL is shown in Figure 10.Notice here that this structure occupies the same size as the typical conventional driver.
In Figure 10, sources of transistor M1 and M2 (or M3 and M4) are connected to metal and metal 2, respectively.All gates and drains of M1, M2, M3 and M4 are connected.
One simple example for pad frame configuration is shown in Figure 11.Power pads are located at the corner of die.Each corner has one VDD and VSS pads that are separated using different metal lines.

CONCLUSIONS
A novel technique for minimization of simulta- neous switching noise is presented.Dual Layer Power Line (DLPL) technique is newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions.Although we still need to take into account of the stray effect of the pad, bonding wire and the pin in the package, this technique gives us a new perspective of minimizing the SSN from an IC designer's point of view.This mutual induct- ance between two power layers enables us to significantly minimize the switching noise without overload of silicon estate.SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces more than 63% compared to the previously reported solutions.Notice that this technique can also be adopted for the PCB power line art-works.Layout for the DLPL technique and test from silicon are under way.Research works are currently on going and more works will be included in the final paper.

FIGURE 2 FIGURE 3
FIGURE 2 CMOS representation of the output drivers.

FIGURE 4
FIGURE 4 The proposed SSN minimization drivers with mutual inductors.

FIGURE 5
FIGURE 5 Mutual inductor model in the ground(Vss) line.

3 .
Figure 8(a) shows geometrical power line structure for the DLPL mutual inductor, and Figure 8(b) depicts lateral view of the DLPL.It consists of two stacked power lines.Insulator such as silicon-dioxide, silicon-nitride or others (larger dielectric material is preferable for a larger k) fills the space between DLPL.It was reported in[7] that with a reasonably feasible thin insulator thickness in current CMOS technology, the coupling coefficient, k can be increased more than 0.88.

FIGURE 8
FIGURE 8 (a) Dual layer power line(DLPL) mutual inductor for Vss and VDD and (b) lateral view of the DLPL.

FIGURE 9
FIGURE 9The proposed output driver structure with DLPL for mutual inductors.
it is necessary to estimate SSN 45O Y. LEE et al. inputs Vss FIGURE Typical output drivers and parastics.