An Efficient Test Pattern Generation Scheme for an On Chip BIST

Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.

INTRODUCTION Performance, area, power and testing are some of the most important attributes of complex VLSI systems.With the current reduction in device sizes, it is becoming possible to fit increasingly larger devices onto a single chip or wafer.As chip density increases, the probability of defects occurring in a chip increases as well.The quality, reliability and cost of the product are directly proportional to the degree of testing of the product.Over the time, the focus on testing of Integrated Circuits (ICs) has shifted from the final fabricated ICs to the design stage.In this context, many Design For Testability (DFT) techniques have been developed to ease testing of circuits [1].The testability of a circuit can be increased with DFT.Testing of the circuit involves the generation of test patterns for the circuit, application of these test patterns to the circuit and analysis of the output response of the circuit.To get the maximum fault coverage of the circuit, one of the simplest approaches is to apply the exhaustive test patterns to the circuit.Many test pattern generation methods like, Ran- dom Pattern Testing, Pseudorandom Testing and Pseudo-Exhaustive Testing have been developed [2, 3] aiming to reduce the pattern length without compromising the fault coverage.Built In Self Test (BIST) is a suitable test methodology for highly complex VLSI devices like systems on a chip.Minimization of circuit area and delay has been the main objective in VLSI design for many years.However, low power consumption has recently emerged as another important design objective.Often circuit designers try to reduce the power consumption of a circuit at the cost of increasing the area and delay of the circuit.Power dissipation in CMOS circuits is dominated by the dynamic component [4] which is incurred when- ever signals in the circuit undergo a logic transition.One of the several important factors affect-ing power consumption is the choice of circuit technique for logic drivers, latches and flip- flops.A good understanding of how the power consumption occurs in the circuits is essential to design more efficient circuits which consume less power.One method reported [5] suggests to switch off the power to the test area to reduce the power during normal operation of the circuit.However this does not look into the power consumption of the test area during testing.In this paper, a method is proposed by which the power consumption during testing is minimized.
The paper is organized as follows.Section 2 describes the power consumption in CMOS circuits.Section 3 describes problems faced in testing and methods to reduce them.Section 4 gives a description of the methods used to generate test patterns.Section 5 gives the simulation results on three circuits to study the behavior of the fault coverage, transitions in the logic of the internal nodes and capacitance switching in the circuit for various LFSR sequences.Based on the simulation results, a method to compute the characteristic polynomial which gives maximum fault coverage with minimum transitions and capacitance switch- ing is explained in Section 6. Section 7 summarizes the salient features suggested in this paper to reduce the power consumption in the BIST imple- mentation while testing.

POWER CONSUMPTION IN CMOS CIRCUITS
The power consumption of digital CMOS circuits is normally divided into three parts, short circuit power Psc, static power Ps and dynamic power Pd [4].

Short-circuit Power Consumption
When a static CMOS gate is switched by an input signal with a non-zero rise or fall time, both n-channel and p-channel transistors conduct simultaneously for a short time.During this time, there will be a "short-circuit current", flowing directly between Vdd and ground.

Static Power Consumption
Static power consumption in CMOS circuits is caused by leakage currents of transistors and pn- junctions.

Dynamic Power Consumption
Dynamic power consumption is related to a node capacitor which is charged and discharged.The average dynamic power dissipation in the circuit is given by, g=l where folk is the clock frequency, Vdd is the supply voltage, Cload(g is the load capacitance of gate g, and T(g) is the average number of transitions at gate g per clock cycle.
The total power consumption P of the circuit is given by, P Psc + Ps + Pd (2) Dynamic power consumption normally dominates static power consumption and short circuit power consumption.It may range from 80% to 85% of the total circuit power consumption.Once the operating frequency of the circuit fclk is fixed, the parameter which can be optimized to reduce the average dynamic power consumption is Cload(g)'T(g).In this paper a method to reduce this switching factor for reduction of the dynamic power dissipation in the circuit during testing is proposed.

TESTING
Testing falls into a number of categories depending upon the intended goal.The diagnostic test is used during the debugging of a chip or board and tries to identify and locate the fault in a failing chip or board.The functional test (also called go/no go test) determines whether or not a manufactured compo- nent is functional.This problem is simpler than the diagnostics test since the analysis and debugging is not involved in this test.Since this test is to be executed on every manufactured die and has a direct impact on the cost (viz., test equipment cost, testing time), it should be as simple and swift as possible.The parametric test checks on a number of nondiscrete parameters, such as noise margin, propagation delays and maximum clock frequencies, under a variety of working conditions, such as temperature and supply voltage.patterns to its inputs.For an N-input circuit, this requires the application of 2 N patterns.In a sequential circuit, the output of the circuit depends not only on the inputs applied, but also on the value of the state of the internal registers of the circuit.An exhaustive test of this finite state machine requires the application of 2 N+M test patterns, where M and N are the number of registers/flip-flops and inputs of the circuit respectively.As N and M increase, the test length expands exponentially.To reduce the test pattern length an alternate approach is required.
By eliminating redundancy and providing a reduced fault coverage, it is possible to test most combinational logic blocks with a limited set of input vectors.To test a given fault in a sequential circuit, the circuit must first be brought to the desired state/initial state before applying the input excitation.One approach adopted in scan test, is to convert the sequential circuit into a combinational one by breaking the feedback loop during the test.Testability of the circuit, depends on the con- trollability and observability of the internal nodes of the circuit [6].Combinational circuits fall under the class of easily observable and controllable circuits, since any node can be controlled and ob- served in a single cycle.Design For Testability (DFT) [1] is the design effort through which a design can be made an easily testable design by en- hancing the controllability and observability.DFT is used to reduce test generation costs, enhance the quality of the tests and hence reduce defect levels.
The DFT strategy contains two components: (1) Provide the necessary circuitry so that the test procedure can be swift and comprehensive.
(2) Provide the necessary test patterns (excitation vectors) to be employed during the test procedure.For reasons of cost, it is desirable that the test sequence be as short as possible while covering the majority of possible faults.

Some of the Intricacies of the Test Problem
The functionality of a combinational circuit can be verified by exhaustively applying all possible input 3.2.Built-in-self-test(BIST) An attractive approach to testability is having the circuit itself generate the test patterns instead of using external patterns to test.Even more appeal- ing is a technique where the circuit itself decides if the obtained results are correct.Depending upon the nature of a circuit, this might require the addition of extra circuitry for the generation and analysis of the patterns.
BIST [7] schemes provide advantages such as at-speed testing, easy reuse of the built-in test structure for diagnosis and repair.One salient feature of BIST that makes it stand out in design and test of VLSI is using a divide-and-conquer approach in which every block has its own embedded BIST structure and is controlled by a chip-wide BIST controller.An ideal BIST scheme achieves not only very high fault coverage with minimum area overhead, low or zero performance degradation and minimum test time but also has low power consumption while testing.

TEST PATTERN GENERATION (TPG) SCHEMES
There are many ways to generate and apply stimuli for the Circuit Under Test.Most widely used stimuli are the exhaustive, pseudo-exhaustive and random [2,3] approaches.In the exhaustive ap- proach, the test length is 2N, where N is the number of inputs to the circuit.The exhaustive nature of the test means that all detectable faults will be detected, given the space of the available input signals.An N-bit counter is a good example of an exhaustive pattern generator.However as N increases the testing time increases exponentially.
Normally in a system with N input variables, every function may depend only on a subset of M inputs.
Then the test pattern set which contains 2 M vectors gives the same degree of confidence in a system as if it is tested with all 2 TM vectors since each func- tion in the circuit is tested exhaustively [3].As mentioned earlier, the testing time can be reduced by shrinking the test pattern sequence.Many test generation algorithms and methods like PODEM, FAN and TOPS have been developed [1].An alternate approach is to use random patterns to get maximum fault coverage with minimum test time.
Various types of test generation procedures for synchronous sequential circuits described at the gate level have been developed.Some of these are deterministic branch and bound techniques [1] and are successful in achieving high fault coverage with high computational complexity and others are based on genetic optimization procedures [8].A test generation scheme MIX reported in [9] com- bines several test generation approaches to derive test sequences exhibiting very high fault coverage at relatively low CPU times.Using any of the above methods, an effective set of 'k' test vectors (patterns) can be identified.These 'k' patterns can be applied to the CUT in the following ways.
The 'k' patterns can be stored in a lookup table (ROM) and addressed by a counter.By designing a logic circuit for the 'k' patterns using counter design techniques.
By designing a suitable Cellular Automata.By choosing a suitable LFSR which can cycle through the minimum patterns in which all 'k' patterns are included.
The efficiency of the method is evaluated in terms of fault coverage, test application time, power consumption, area overhead, performance penalty/degradation and computational time to arrive at a particular solution.

SIMULATION STUDIES OF AN LFSR AS A TPG
Autonomous circuits such as Linear Feedback Shift Registers (LFSR) [1] are used as low-cost-test pattern generators for circuits testable by pseudorandom patterns.An LFSR with different feed- back coefficients (characteristic polynomials) started with different initial seeds may yield significantly different pattern lengths.When these patterns are used as test sequence, it yields dif- ferent fault coverage.To study the relationship among the features such as the fault coverage, transitions and capacitance switching in a circuit using all possible sequences of an LFSR, fault simulation and circuit simulation have been carried out on three different circuits (viz., ripple adder, Booth multiplier and comparator).The circuits were synthesized using ASIC Synthesizer of Compass tools.The gate level net list has been simulated using QSIM of Compass tools to cal- culate the number of transitions of each net.Fault simulation has been done using Verifault- XL Cadence tool for the same gate level net list.We considered all the possible characteristic polynomials of an 8-stage LFSR and all possible initial seeds for each characteristic polynomial in the simulation studies.The summary of simulation results is shown in Tables I, II and III.The results shown in these Tables are chosen on the basis of the following criteria: Maximum fault coverage achieved in a circuit with minimum number of patterns.
The results corresponding to the number of patterns where the percentage difference be- tween fault coverage is maximum.
The results corresponding to the number of patterns where the percentage difference be- tween number of transitions is maximum.

Simulation Results of a Ripple Adder
An 8-input ripple adder circuit was simulated and a summary of the simulation results is shown in Table I.The simulation results indicate that a fault coverage of 97.3% can be achieved by using patterns of length 5 to 255.It may be observed that, as the pattern length reduces, the number of transitions also reduces.Moreover, for the same   pattern length, depending on the pattern sequence produced by the LFSR, the fault coverage and the number of transitions vary.For example, with a pattern length of 5, depending on the pattern seq- uence, the number of transitions varies between 61 to 132 while the fault coverage varies between 67% to 97.3%.It is observed that a pattern length of 255 also yields the same fault coverage.However, the number of transitions varies between 3623 to 3660 for the pattern length of 255.This behavior of fault coverage and number of transitions with respect to the pattern length is reflected in Figure 1.

Simulation Results of a Booth Multiplier
Simulation were carried out on an 8-input Booth multiplier circuit.The results shown in Table II indicate that a fault coverage of 99.59% we can achieve using patterns of various lengths between 15 and 255.It may be observed that, the number of transitions also reduces with reduction of the pattern length.The fault coverage and the num- ber of transitions vary depending on the pattern sequence produced by the LFSR.For instance, consider a pattern length of 15.Depending on the pattern sequence, the number of transitions varies between 354 to 658 while the fault coverage varies between 86.69% to 99.59%.It may further be noted that a pattern length of 255 also yields the same fault coverage with the number of transi- tions varying between 7875 to 8051. Figure 2 illustrates, this behavior of fault coverage and number of transitions with respect to the pattern length.
patterns fault coverage transitions FIGURE 2 Fault coverage and number of transitions for a multiplier.

Simulation Results of a Comparator
Table III presents the simulation results obtained on an 8-input comparator circuit.The simulation results indicate that a fault coverage of 100% can be obtained by using patterns of length 14 to 255.In this example also, the number of transitions reduces with the pattern length.Moreover, for the same pattern length, depending on the pattern sequence produced by the LFSR, the fault coverage and the number of transitions vary.For example, with a pattern length of 14, depending on the sequence, the number of transitions varies between 56 to 234 and the fault coverage varies between 60.6% to 100%.Note that a pattern length of 255 also yields the same fault coverage, but the number of transitions varies between 2739 to 2777.This behavior of fault coverage and number of transitions with respect to the pattern length is reflected in Figure 3.

Summary of Simulation Studies
A summary of these three simulation studies is presented in Table IV.These studies indicate that a method must be adopted to select the test pattern sequence such that the application of this test pattern sequence to the CUT gives the maximum fault coverage, while minimizing the number of patterns and number of transitions.Minimum number of transitions has the obvious advantage of reduced power consumption during testing of the circuit.For example, the number of transitions in the adder circuit for a fault coverage of 97.3% can be reduced from 3623 to 132, with a reduced test length from 255 to 5, by suitably selecting the characteristic polynomial of an LFSR.Configuration of an LFSR for use as an efficient TPG in an On Chip BIST is a difficult problem.
We must obtain a solution, such that the LFSR cycles through a minimum number of states in which all the required test patterns are included, ensuring high fault coverage consuming minimum power during testing.A method based on learning and genetic optimization process has been ex- plained in [10].In this approach, the authors have considered test length and fault coverage as the parameters of interest but have not aimed at power minimisation during testing.Considering minimi- zation of power consumption during testing as the primary objective we propose a methodology shown in Figure 4.
Testing of an n-input combinational circuit requires an n-stage LFSR, which is used as a TPG.Normally, the LFSR behavior can be represented in a directed graph.The vertices of the graph are the different output patterns gen- erated by the LFSR.An edge connects two prob- able sequences of the output patterns.Consider a 3-stage LFSR whose behavior is shown in the following graph (See Fig. 5).
For a characteristic polynomial / x / x 2 / x 3 and an initial seed of "010", the 3-stage LFSR cycles through the paths {all,al2}.Similarly depending on its characteristic polynomial and its initial seeds, the LFSR can cycle through the SklCl q-Skit2 -t--I-SknCn Sll Now the problem reduces to solving these equations to find out the values of c l, c2,..., Cn.
Although the above set of equations appear to be a set of linear equations, the addition is a modulo 2 operation.Hence, the conventional techniques which are used to evaluate linear system of equations can not be used directly.We can solve these equations by modulo 2 addition of pairs of equations in the set.However, using this approach need not always lead to a solution of the system of equations.Hence, we propose a method of substitution to evaluate these coeffi- cients.In this method we assign "0" as the value for one of the coefficients.The equations are rewritten with the given values and should be checked for consistency as defined below.DEFINITION A system of equations is said to be consistent if there exist a vector C-(cl c2... %) to i,j=l under modulo 2 addition.
If the resulting set of equations are consistent then we take the coefficient to the assigned value as "0", otherwise make the value of the coefficient as "1".Proceed further in the similar manner for the next coefficient evaluation.In this way all the coefficients can be evaluated.To explain the above process, we take an example of an 8-stage LFSR whose pattern sequences and steps to achieve the solution for coefficients of a characteristic polynomial is explained below.From Eq. ( 4), these sequences result in the following system of equations.This system of equations can be solved for the coefficients ca, C2,..., Cn, by assigning values either "0" or "1" to the unknown coefficients and checking the resultant system for consistency.While choosing the values, "0" is given priority since the feedback connection can be avoided while realizing the LFSR.Simplification of the above equations is done by modulo 2 operations.
For the above example, the unknown coefficient vector (c c2 c3 c4 c5 c6 c7 c8).By fixing C "0", we have the following system of equations after simplification of the above set of equations.
The resultant set of equations satisfies c =0 since the above equations are consistent.By successive assignment of the values "0" or "1", to the rest of the coefficients we can get the solution.It may be noted that assigning c4=0 after fixing cl =c.=c3=0, we get the following set of inconsistent equations.
characteristic polynomial (cl c2 C3 C4 C5 C6 C7 C8) (0 0 0 0 0 0 1) is obtained.The corresponding LFSR is shown in Figure 6.This way one can find LFSR coefficients and realize the circuit for required Test Pattern Generator.It may also be noted that some of the sequences generated by an LFSR can be obtained by more than one characteristic polynomial.Hence, our method of substitutions leads to one of these characteristic polynomials.For example, a 3-stage LFSR cycles through the same sequence 110, 011, 101 for two different character- istic polynomials, namely, -[-ClX--{-C2x2, +C3X 3.
Though the theory is not mathematically proven here, we have carried out several experiments using the proposed methodology.We have achieved the result with few iterations.-0 (7.9) (7.10) =0 (7.11) -0 (7.12) Equation (7.1) and Eq.(7.6) are contradict- ing each other.Hence, we assign c 4 1.By ap- plying the above method, the coefficients of the FIGURE 6 LFSR with characteristic polynomial nt-C4X4q C8 X8.
This paper has discussed a suitable method to reduce the power consumption in the BIST im- plementation during testing.Since LFSRs are being used as TPG in the BIST implementation scheme as a cost effective TPG, we have con- ducted simulation study of LFSRs with different configurations and initial values for different test sequences.Simulation study on three different circuits has revealed that maximum fault coverage can be achieved with an LFSR sequence of mini- mum test length while keeping the power con- sumption of the circuit at a low value.We have shown how to choose a test sequence produced by LFSR to reduce the power consumption using graph theory techniques.Also we have shown how to find the characteristic polynomial for a given test sequence.Even though the approach shown here is convenient for small combinational circuits, large combinational circuits can be partitioned into smaller sub blocks and can be tested in a similar way.In case of sequential circuits, similar approach can be adopted by introducing scan methods.We are currently extending our ap- proach for testing sequential circuits.

FIGURE 3
FIGURE 3 Fault coverage and number of transitions for a comparator.

6. 3 .
Example to Compute the Coefficients of the Characteristic Polynomial Consider an LFSR of 8 stages that has to cycle through the following twelve sequences. c3