A Fine Grain Configurable Logic Block for Self-checking FPGAs

This paper proposes a logic cell that can be used as a building block for Self-checking 
FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 
multiplexers and a D flip-flop. The cell has been designed using Differential Cascode 
Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off 
faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The 
multiplexers and the D flip-flop provide either correct (complementary) output in the 
absence of above-mentioned faults; otherwise the outputs are identical.


INTRODUCTION
FPGAs are frequently used for rapid prototyping of digital systems [1].The complexity of FPGAs has increased to an extent that they are used to implement circuits of many thousands of gates.Although FPGAs can be fully tested before a function is programmed into it, faults such as shorts and opens can only be detected after a device has been programmed [2].Also, the currently available testing techniques can detect only permanent faults, not transient faults that may occur during normal operation [3][4][5][6][7][8].The characteristics of transient faults require a test strategy that is based on continuous monitoring of circuits during normal operation, the presence of a fault being indicated by an invalid output pattern.Such a test strategy is known as concurrent checking or on-line testing.A circuit with con- current checking capability is known as a self- checking circuit [9].A typical self-checking circuit shown in Figure consists of a functional part whose outputs are encoded using an error detect- ing code, and a corresponding checker circuit that monitors the outputs of the functional circuit.A checker must have two outputs and hence, four *Corresponding author.Tel.: (501) 575-5159, Fax: (501)575-5339, e-mail: lala@engr.uark.eduTel.: (336)344-7761X229, Fax: (336)344-7716, e-mail: alvernon@ncat.edu

Output code words
Outputs FIGURE Model of a totally self-checking circuit.output combinations.Two of these combinations are considered to be valid e.g.(01 or 10).A non- valid checker output, 00 or 11 indicates either non- code word at the inputs of the checker or a fault in the checker itself [10,11].Thus, by observing the output of the checker circuit it is possible to deter- mine whether there is any fault in the function or in the checker circuit.
The following two definitions describe the manner in which self-checking circuits deal with faults [12]: DEFINITION 1 A circuit is fault-secure for a given set of faults, if for any fault in the set the circuit either produces the correct code word or a non- code word but never an incorrect code word at the output for the input code space.DEFINITION 2 A circuit is self-testing if for every fault from a given set of faults the circuit produces a non-code word at the output for at least one input code word.
A circuit is totally self-checking if it is both fault secure and self-testing.Totally self-checking cir- cuits are very desirable for highly reliable system design since during normal operation all faults from a set would cause a detectable erroneous output.Such circuits have significant advantages, such as: (1) Transient faults as well as permanent faults are detected.
(2) Faults are immediately detected upon occur- rence; this prevents propagation of corrupt data within the system.

SELF-CHECKING CELL
Figure 2 shows the proposed self-checking cell that can be used as a building .blockfor FPGAs.It  and the D flip-flop have been implemented using differential cascode voltage switch logic (DCVSL) [13, 14].Each cell can implement a given function of upto five variables.Functionally this cell is divided into two main blocks: Block I and Block II.Block I is used to implement the logic function.
Block II acts as a control module for the cell.
This module works in four modes: As indicated earlier the proposed cell is imple- mented using DCVSL.A logic function and its inverse are automatically implemented in this logic style.The pull-down networks implemented by the nMOS logic tree generated complementary out- puts (Fig. 3).The advantage of DCVSL is in its logic density that is achieved by elimination of --m, {T VDD Latch FIGURE 3 General structure of a DCVSL gate.large PFETS from each logic function.All functions are implemented using NFETS only, and PFETS serve only as the pull-up devices.A DCVSL circuit can be divided into two basic parts: a differential latching circuit and a cascoded complementary logic array.The latch in these logic circuits is realized with two cross-coupled pMOS transistors as shown in Figure 3, i.e., transistors Tp0 and Tp 1.The cascode complemen- tary logic array is realized with a nMOS logic tree.The function is realized by the part of the nMOS logic tree connected to node Z.The complement of that function is realized by the section of the logic tree connected to node Z in Figure 3. Due to the two outputs (or lines) associated with dual-rail logic, four distinct signal states are possible.To illustrate the behavior of DCVSL circuits in the normal and single stuck-at faults case we consider the 2-to-1 multiplexer.Figure 4 shows a 2-to-1 multiplexer with inputs A and B and their complements A and B respectively; S and S are the control signals.Table I shows the normal operation of the multiplexer.Control signal S is high (S-1) and S is low (S 0) for vectors to 4. For vector 1, input A--1, A=0, B--1 and B--0, the output response are Z= and Z-0.produce either 01 or 10 outputs.Vectors 5 to 8 are similar to vectors to 4 except for control signal S 0 and S 1. Now let us examine the behavior of the circuit shown in Figure 4 for a stuck-at 0 fault on input A with A=0, B=0, B--1, S= and S 0. Both T7 and T8 are off for this input.Therefore both pulldown networks are off in this case.In this state the output of the DCVSL gate is only determined by the differential latching circuit, i.e., transistors T1 and T2 in Figure 4.The output of the circuit corresponds to the two states of the latch, i.e. (Z)= 01 and 10, the output state of the circuit, i.e., the state of the latch, is set during the last fault-free event in the circuit.The output of the DCVSL gate should be 11 or 00 in this case for online fault detection.Table II shows the behavior of the 2-to-1 multiplexer in the presence of a s-a-0 fault at its inputs for a previous circuit output of 01, i.e., Z 0 and Z--1.Vectors and 2 in Table II indicates the behavior of this multiplexer when input A is s-a-0.The desired response of the DCVSL circuit is also shown in Table II.Both pulldown networks are not conducting for all the vectors and s-a-0 faults in Table II.In this mode the output of the gate is determined by the differential latch.The output of this circuit doesn't indicate the presence of a fault because the two states of the differential latch 01 or 10 correspond to valid output codes, i.e., 01 or 10.
To indicate the presence of a fault it should be either 11 or 00.If we modify the 2-to-1 Multiplexer by adding two weak p channel devices, i.e.,  transistors T9 and T10, as shown in Figure 5.The output of the modified 2-to-1 Multiplexer will equal 11 for all the vectors and s-a-0 faults in Table II.This will also be its Figure 5 here output for any single fault that causes both pulldown networks to be nonconductive.The DCVSL rise time characteristics is determined by the geometry of the weak p-channel pullup transistors, i.e., T9 and T10 in Figure 5.The propagation and power dissipation of the Multiplexer is also affected by this configuration.Stuck-at faults can also cause both sides of the logic tree to conduct simultaneously.
A list of vectors and stuck-at faults that causes the circuit to operate in this mode is given in Table III.Table III shows the expected outputs for all single stuck-at-1 faults at the inputs of 2-to-1 multiplexer.The input vectors are the same as vectors and 2 of Table I and Table II but both Z and Z should become 0 in the presence of an input s-a-1 fault.To determine the output of this dual- rail circuit when both pulldown networks conduct consider the DCVSL inverter shown in Figure 6 for an input of VDD on both gate inputs.If we assume that the threshold voltage of the transistors in this circuit are equal and that/l/f14-fl2//3 then  the voltage on nodes V A and V B is, Therefore the ratio of the MOS transistor gain factor/3, for transistors T1, T2, T3 and T4, that is required to insure that the output of the gate falls within the output low noise margin NML is defined by the following relationship,  Table III shows the outputs for all single stuck-at- faults at the inputs of the modified 2-to-1 multiplexer.The input vectors are the same as vectors and 2 of Table I and Table II but both Z and Z become 0 in the presence of an input s-a-1 fault.Transistor stuck-on or stuck-off faults have similar effect on the outputs as s-a-1 and s-a-0 faults respectively.Some of which are shown in Table IV.The 4-to-1 multiplexer behaves in the same manner as the proposed 2-to-1 multiplexer in the presence of all-single stuck-at faults and transistor stuck-on/off fault i.e., the transient response for normal and s-a-l/0 will show the similar pattern for all defined fault-free and faulty conditions.Its transistor level diagram is shown in Figure 7. Figure 8 shows the Self-checking master- slave D-flip-flop that has inputs Clk (clock), D (data-in) and their complements Clk and D respectively; the outputs are Q and Q.The fault- free operation of this D-flip-flop is shown as vector in Table V. Vectors 2 to 6 show the behavior of D-flip-flop in the presence of assumed stuck-at- faults.For any transistor-fault or faulty input conditions i.e., 00 or 11, Q and Q either provides correct output or non-code word.Z ABC + DE This can be illustrated by using proposed cell as shown in Figure 9.Let us assume A is stuck-at-1 then for input pattern A-0, B-0, C-0 and E-1, outputs are Z-0 and Z 0. If A is stuck- at-0 then for input pattern A 1, B 0, C-0 and E-1 outputs are Zand Z--1.Similarly, for other single stuck-at fault in this cell Z and Z gives either the expected output or the wrong output.Output waveforms (generated by Berkeley SPICE- 3.5) for the fault-free cell, A stuck-at-0, and A stuck-at-1 condition are shown in Figures 10, 11   and 12 respectively.In Figures 10, 11 and 12, nodes u (9) and u (8) represent output Z and Z of the circuit shown in Figure 9. Figure 13 shows the layout of proposed cell that has been implemented using Magic layout in 2-# CMOS technology.We illustrate the implementation of the seven MCNC benchmark circuits using the proposed cell.They are tested in the presence of faults and have produced the similar results as derived in fault tables.These are listed in Table VI.It is also found    5exp 3 that most of the complex functions required only one cell except for vg2 and 5expl, which are eight and ten variable functions respectively.

CONCLUSION
We have developed a programmable cell with built-in self-checking feature.This cell can be used as a configurable logic block in an FPGA.The major features of such an FPGA are: (1) Each configurable cell uses fewer transistors than that required in FCMOS implementation.(2) A single transistor stuck-on or stuck-off fault in a multiplexer or in the D flip-flop will result in an output of 00 or 11 from the cell.Also, any single stuck-at fault at the inputs of a multiplexer or the D flip-flop can be detected on-line.
(3) A number of such cells can be interconnected to implement any complex logic function.If such cells are interconnected in n-stages, the presence of a single fault in one of the inter- mediate cells will propagate to the output of the final stage.The final outputs of such a function can be verified internally by incorpor- ating two-rail checkers.

FIGURE 2
FIGURE 2 Proposed self-checking cell.

Figure 4
Figure 4 for a stuck-at 0 Vectors S FIGURE 6 DCVSL inverter.

TABLE
Fault free operation of 2-to-1 multiplexer in

TABLE II
Behavior of 2-to-1 multiplexer in the presence of single stuck-at-0 faults

TABLE IV
Output response for stuck-at-1 conditions