Impact of Scaling on CMOS Chip Failure Rate , and Design Rules for Hot Carrier Reliability

Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy distribution, as it causes an increased probability of smaller devices having lower activation thresholds and therefore faster activation times. Further, we quantify the voltage shift necessary to overcome the decreased yield due to the increased number of early device failures, and show, for 0.1 tm MOSFET scaling, that this shift can be a considerable fraction of the conventionally designed supply voltage.


INTRODUCTION
There are at least two degradation mechanisms in MOSFETs that are caused by the hot carrier- induced activation of hydrogen from the silicon- silicon dioxide interface: the creation of interface traps, and the creation of bulk oxide traps [1].The creation of interface traps is significant for MOSFET channel hot electron degradation [2,3].
Interface traps are responsible for a reduction in the saturation drain current (IDsAT) of the MOSFET which causes an increase in the propa- gation delay [4] which is then responsible for failure of the chip.The activation energies of the hydrogen bonds are therefore an important param- eter for the degradation process.Note, that this may also be true for the creation of bulk oxide traps, not discussed here, which likewise seem to be related to hot carriers and hydrogen release [1].
Past models [2] have assumed that the hydrogen activation energy was constant at around 17(mean) a,l 3.7 eV.This is inconsistent with charge-pumping measurements, which show broadened energy distributions of the hot car- rier induced defect states with half-widths r larger than 0.1 eV [5].Disorder-induced variations   among the Si--H activation energies, EA,IT, must be at least of this order, and are believed to be a source of the sub-linear time dependence of nMOSFET aging [5].If we assume that the bond energies of individual bonds independently follow such a distribution, then each device will have a different set of activation energies, and we can expect variations in the hot carrier aging rate of individual nMOSFETs.These variations will result in a distribution in transistor and chip lifetimes.As the geometry of devices diminishes, there is an increased probability of having a device, or a critical path of devices, that has a sufficient number of hydrogen bonds with low activation energies to fail at much smaller times than the mean time to failure.In other words, the distribution of device lifetimes increases its width as we shrink the MOSFETs affecting device reliability.Quantifying this effect on the lifetime of the MOSFET is the subject of this paper.resulting from the activation of the Si--H bonds at the interface.Similar disorder-induced varia- tions in the Si--H bond energies can be expected (physical explanation analogous to theory in [6]): /,(mean) EA IT)/fliT) The integral of this distribution is the probability that the fraction of activated Si--H bonds under hot-carrier stress have activation energy less than or equal to EA,T: + exp (\P-'X,IT EA,IT)/fliT) where Dito and ADit are the original interface defect density and the hot carrier activated defect density, respectively.Then (ZIDSAT/IDSATO) is a function of fHCI.Defining a lifetime constant 'IT using: qVDD Measurements for/DSAT degradation (our perfor- mance measure) under the worst-case stress show a corresponding lifetime following an Arrhenius- type relation or models such as Ref. [2]: Then we get by inserting Eqs. ( 1) and (4) into Eq.(3): qVDD where is the time needed to activate Si--H bonds with activation energy less than EA,IT (enough for specific device failure).Charge-pumping meas- urements show a broadened fermi-derivative distribution in the energies of the defect states with: qVDD OHCI (6) aiTm ln (10) The technology-dependent constant M can be extracted from the plot of lOg/measured versus (1/VDD) for a measured device (e.g., we use data 1This form of the activation energy distribution has been used in the study of the reliability of grating-based optical dense- wavelength division multiplexed (DWDM) chip interconnects where bus signals are carried by separate lightwaves in the same link.
from [8]): /i//]t;,(measured) log /measured --"A,IT -1--C (7) qVoo where tmeasured is the time needed to activate SinH bonds with activation energy less than IT(measured) 'A,IT (enough for measured device failure).Assuming a starting number of N/4 neutral defects (hydrogen) for this device, then the actual number of defects Nf needed for device failure (i.e., 5% IDSAT de- gradation) can be obtained from charge-pumping or simulation data and can be used to solve for (measured) {EA ITI'HcI(EA,IT) Nf/NH} by "-'A,IT using Eq. ( 3).In this work, 2 p/_/is assumed to be 1012 cm 2 in the whole channel, and we calculate the average number of silicon-hydrogen bonds which are in danger of activation by assuming a box of width W (width of the device) and length Lit at the drain end of the device.We define Lit as the region where the electric field drops to one fourth of its maximum value.The number of silicon- hydrogen bonds in that region is then N/_/= pHLitW.Then we can calculate the number of bonds required to cause the device to fail, Nf, by performing DESSISIsE TCAD simulation and find the density of interface traps Pi required to cause failure where failure is defined as a 5% degradation in IDSAT.Throughout, we use the Interna- tional Roadmap for Semiconductors and the well tempered MOSFET part of the DesCArtES project [10] to obtain values of various device parameters.Equation (6) gives a very important relationship between the sub-linear power-law factor OZHC and VDD/M once OIT the half-width of the defect activation energy distribution, is known.The above analytical form for the power- law factor (i.e., Eq. ( 6)) can serve as a great tool for chip reliability engineers as discussed in [5] for the design and understanding of hot-carrier immune devices.One can replicate the measured sub-linear time-dependence of hot carrier aging with an appropriate choice of the half-width O'IT.
We show in [11], using a 180 nm device that aT E(mean) 0.2 eV.In addition, we have A,IT 3.1 iV.
We would like to add that we have described a model of the time-dependence of hot-carrier degradation owing to a unimodal distribution of hydrogen activation energies that gives the single power-law of Eq. ( 5).However, recent theoretical calculations on the Si-SiO2 interface structure [11] suggest that defect activation can occur with probability p around a principal mean energy EA meanl) 3.5 eV as well as a lower secondary mean ,IT (mean2) energy A,T 2.9 eV with probability -p suggesting that the activation energy distribution is actually bimodal.As shown in [5], this would give a slightly more accurate time-dependence then Eq. ( 5) which is a double-power law: Hf(t) (p/(1 + (t/Tq)-)) + ((1 --p)/(1 + (t/7-2)-2)) ( 8)

FAILURE STATISTICS AND RELIABILITY ASSURANCE
The failure probability of a device before time (or equivalently by the activation of a sflieient number of hydrogen with activation energy less than or equal to EA,IT, where and EA,T are related by the Arrhenius equation) is given by the finite binomial probability (after some mathema- tical manipulations): where NH--W fee pl-l(X)dx and Nf-w f eg pit(x)dx are the starting number of SigH bonds at the interface and the number needed for 5% IDSAT degradation respectively, Pi-i(x) and Pit(X) are the Work is under way to alternatively calculate pit(x) by using our newly developed interface state generation model with input of a nMOSFET hot carrier energy distribution given by the Monte Carlo code (MoCa) [9].
density of SigH bonds and interface traps till failure, respectively, as a function of position x in the channel.We can extract the defect activation energy distribution from the model of Eq. ( 5) or Eq. ( 8) by fitting to short-time accelerated tests data [5].
Once we have determined the parameters of the activation energy distribution, we can assure reliability for all times by imposing the following constraints (with MTF >_ (1/aFIT)): where PPM is the failed parts per million devices goal, FIT is the failure in billion hour time units goal, a is the relative failure rate per device normalized to the 180nm technology and /3

FIGURE
MOSFET FIT (inverse of MTF) and PPM (failed parts per million) versus maximum supply voltage (VDD .... 1.1 VDD....dmap) reductions.Device is safe when it meets both PPM and FIT criteria.The different CMOS generations are characterized by their effective channel length and the corresponding poly gate lengths: (a) LG=.25 pm (b)  LG 18 gm (c) LG 13 gm (d) LG .09gm. of critical dimension) normalized to the 180nm technology.In this way, during device lifetime, tf<< MTF, the probability of even weakest device failing is miniscule.We are imposing a constraint on the device reliability function and its slope, both of which are important for the long-term reliability qualification of not only the hot- carrier failure mechanism but also other failure mechanisms.With the design aims of Eqs. ( 10) and (11), we can calculate maximum supply voltage reductions for safety.With the shrinking geometry of MOSFETs, there is an increased probability, FHCI, of devices having enough low activation energy defects which necessitates more than the conventional 10% VDD,max reduction for safety.If we require failure rates below 10 FIT as well as reliability below 50 PPM as design aim for all generations (Fig. 1), then much larger /gDD,max are required for smaller devices (Fig. 2).

CONCLUSION
We have quantified CMOS chip failure rates from a first principles study of hot carrier aging of nMOSFETs and by considering variations in such an aging rate due to a distribution in the width of the bond energies of passivating hydrogen at the interface.We emphasize that there are only three essential requirements for the effect discussed above to be significant in small geometry devices: (i) There must be a distribution of activation energies, although the specific form of the dis- tribution is not critical, (ii) the number of charged defects necessary for degradation must decrease roughly as fast or faster than the channel width, and (iii) the fast degradation of a sizeable fraction of circuits is unacceptable.Each of these assump- tions appears reasonable.Because of the effect of the bond energy distribution on the failure rate, we argue that the reliable operation of deepsubmicron CMOS technology can only be achieved for VDD,max-/ VDD,max where VDD,max can be determined from conventional methods of device reliability [8], and A Vr)r,max can be determined from our results (Fig. 2).Another alternative would be the use of a better quality interface (such as deuterium passivated interfaces [3]) where lifetime variations are more tolerable.

FIGURE 2
FIGURE 2 Reductions in maximum supply voltage, VDD..... for safety for the different technologies.