A Q-Enhanced 3 . 6 GHz , Tunable , Sixth-Order Bandpass Filter Using 0 . 18 μ

An experimental filter was designed to operate at 3.6 GHz using mainstream 0.18 μm CMOS. In the design, the Q-enhancement technique was used to overcome the low-Q characteristics of the CMOS on-chip inductors. A sixth-order bandpass filter with a wide passband and a high image rejection was built by cascading three stages of second-order Q-enhanced filters. A combination of three biquads with offset in center frequency provides wider tuning frequency and bandwidth. This high-performance filter provides a 340 MHz tunable center frequency around 3.6 GHz, an image rejection of 50 dB and a tunable Q from 25 to 50 for a bandwidth adjustment from 95 MHz to 35 MHz. The filter achieves an 18 dB voltage gain while consuming 130 mW of power at 1.8 V DC supply. The chip occupies an area of 900×900 μm2 including all the required bonding pads. The design provides a simple architecture to simplify tuning scheme for both frequency and bandwidth for practical use. The tunable ability of the design could be exploited in further study to be used as a channel-select filter in the gigahertz range.


INTRODUCTION
The rapid growth in wireless telecommunication systems necessitated research and development of monolithic bandpass filters for gigahertz radio frequencies.There has been great interest in building LC bandpass filters using monolithic inductors on silicon [1][2][3][4][5][6][7].The drawback in the integration of these filters in a single chip is mainly due to the lack of high-Q on-chip inductors.Recent progress in IC technology highly improves performances of the CMOS RF components.The integration of filters in GHz range faces many hurdles such as the design of high-Q on-chip inductors and capacitors and in particular, the accurate high-frequency CAD models for onchip passive components.In addition, the design of a wide tuning range and high-quality varactors in CMOS technology is also a great challenge [8].
This paper presents an approach and design of a tunable 3.6 GHz CMOS bandpass filter to achieve the following characteristics: low-noise figure, wide-tuning range, high-voltage gain, and high-linearity.The filter is designed as a secondorder and then cascade to form a sixth-order filter with a tuning capability in both center frequency and quality factor.These tunings offer frequency selection and bandwidth adjustment.Power gain, noise figure, and particular linearity of the filter are also taken into considerations of the design.

TUNABLE BANDPASS FILTER DESIGN
The basic second-order bandpass filter includes an input transconsductor to interface with other devices, a tunable LC resonator to provide fundamental frequency and a Qenhancement circuit to increase filter qualify factor.Two separate voltages are used to tune the filter frequency and Q. Figure 1 shows a block diagram and a simplified schematic diagram for the second-order BPF.

The input transconductor and the LNA
The input transconductor is used as an input stage for the filter.In this design, the input transconductor directly connected to a 50 Ω system.Such direct connection requires an impedance matching for power transfer from the external device to the gate of the input transistor.A source degeneration input transconductor shown in Figure 1(b) is used.This transconductor also acts as a low-noise amplifier (LNA) to reject part of the undesired bandwidth.This structure provides a good input impedance matching, a good power handing capability, a high linearity characteristic, and a lownoise figure.The impedance of this input transconductor can be controlled by careful design and layout of the inductor L1 and the gate-to-source capacitances of the input transistors.
It has been known that the first stage requires a circuit with a noise figure as low as possible, therefore care has been taken in the design of this LNA.Note that the design employs the differential mode.This mode offers a stable reference point for the LNA (i.e., the other half circuit instead of the unreliable ground point due to parasitics of the single-ended mode).Another benefit of this mode is the linearity improvement by canceling some of the harmonics.

The LC resonator
The parallel LC circuit shown in Figure 1(b) is used as a second-order resonator.This tank circuit includes a pair of inductors and a pair of diode junction capacitors (varactors).
In this design, a center-tapped symmetrical spiral inductor shown in Figure 2 is used.
This geometry provides symmetrical inductors in a single coil.The benefit of this configuration is that the inductors can be used in differential mode which is the topology of this design.Metal 6 (the top metal layer in the 0.18 μm CMOS technology) is used as wire because this thick layer of metal locates far from the lossy substrate.Metal 5 is used for interconnections between the turns.To further reduce substrate loss, a patterned ground shield (PGS) in metal 1 layer is formed underneath the inductor.This PGS also helps to further isolate the noise from the substrate [9].This 5-turn inductor has a wire width of 8 μm, a turn spacing of 1μm, an inner radius of 16 μm, and an outer radius of 60 μm based on [10].Figure 2 also shows the inductor model and its parameters are listed in Table 1.Structure of the p + to n-well junction varactor is an array of small junctions instead of a large junction.This arrangement occupies a smaller chip area and the sidewall capacitances increase the variable capacitance per unit area.This increment provides a better C max /C min ratio for the tuning range of the resonator.The designed varactor consists of 8 junction array columns and 7 junction array rows with a width and length of 5.8 μm. Figure 3 shows a layout of the array varactor used in this design and its model.The model includes an n-well to p-substrate junction and side-wall capacitors.The inherent losses are represented by the series resistor and the parallel resistor.The series resistor represents the losses associated with the junction and the parallel resistor represents the lossy signal path through the p-substrate.
The junction capacitance, C j , is a function of various parameters as follows: in which C j0 is the junction capacitance per unit area at zero voltage, A j is the junction area, Φ is the built-in junction potential, and m j is a fitting process constant.This constant depends on the doping profiles for p + and n − implantations.As indicated, this junction capacitance is a function of the reverse voltage (V r ) across the varactor.Changing this   The model above is used to simulate using advanced design system (ADS) simulator.The Q values of the varactor were found between 25 and 29 depends on its tuning voltage as shown in Figure 4. Simulation results also indicate a C max /C min ratio of 1.11 (C max =2.825 pF, C min =2.550 pF).As the low Q of the on-chip inductor and varactor inherent from CMOS, a Q-enhancement technique is employed in the design to increase the overall quality factor of the filter.

The Q-enhancement circuit
The basic function of the Q-enhancement technique is to add a negative conductance to the LC circuit to compensate the losses in the resonator.Serial parasitic resistor of the on-chip inductor, low Q diode junction capacitance, and lossy substrate are the main sources of loss in the LC tank.The inductor resistance usually dominates the loss.Detailed explanations on the losses and techniques to generate a negative impedance, −G m , to reduce the loss can be found in literature such as [5,11].

Design of the sixth-order bandpass filter
A wideband filter with good selectivity can be implemented with higher order filters; one way is to cascade several stages of the second-order filter [12].Three stages of the secondorder are coupled with capacitors to form a sixth-order filter as shown in Figure 5.The stages are tuned to three different center frequencies.In this design, with a single tuning voltage, the first stage is tuned around 3.56 GHz, the second stage around 3.64 GHz, and the third stage around 3.60 GHz.As a result, the overall center frequency of the filter is at 3.6 GHz with a wider bandwidth.A simplified schematic diagram of this sixth-order filter is shown in Figure 6.

Frequency tuning
Frequency tuning of the second-order filter is implemented by varying the reverse voltage of the junction diode varactor.In the sixth-order filter, there are three stages that contain three different resonators.Each stage must be tuned to a different center frequency to provide an overall wider bandwidth.This can be only realized by tuning each stage separately.To simplify the frequency tuning scheme, an innovative method was used so that only one tuning terminal is used to tune all three center frequencies.In order to set the center frequencies apart to have a wide bandwidth, extra capacitances are inserted into the first stage and the third stage.The frequency of each stage is derived as where C xn is the extra capacitance added to the nth stage, the other parameters are as the same as in (1).The optimum numbers found for these capacitors are: C x1 = 35 fF, C x2 = 0, and C x3 = 25 fF. Figure 7 shows the center frequency of each stage with the inserted capacitances.With these values of capacitors, the center frequencies are spacing In order to make the combined passband ripple as small as possible, Q of the third stage is intentionally designed smaller than Q's of the first two stages by setting the tail currents, Ib, of the three stages to the following ratio: Ib1 : Ib2 : Ib3 = 1 : 1 : 0.8.

Filter components
As shown in Figure 6, the filter is implemented by cascading 3 stages of the second-order filter.The stages are coupled with coupling capacitors (C1 to C4).The LNA is the same in all stages.In order to optimize the gain distribution, the width to length ratios of the current source transistors to the stages are scaled to 1 : 1.1 : 1. Table 2 lists the component values of the designed filter.

Linearity consideration
Linearity of the Q-enhancement circuit is critical because the nonlinearity of this circuit greatly affects the overall filter linearity.There are several techniques to improve linearity.One is to add a source degeneration resistor, Rd, across the crosscoupled transistors of the Q-enhancement circuit [4].G m of the modified circuit now becomes This source resistor reduces G m , thus, improves circuit linearity.The drawback of this technique is that the resistor consumes a substantial amount of power and degrades noise performance.The other technique is to use transistors biased in their triode regions as shown in Figure 8 in which M3 and M4 are the source-degenerated resistance [13].As the input signal increases, the small-signal resistance of one of the two triode-transistors in parallel is reduced.The reduction in resistance attempts to increase transconductance.The action results in a partial canceling of the decreasing G m value.The transconductance G m of this modified circuit is derived and expressed as follows: in which k i is a constant depending on technology and size of the transistors, k i = K(W i /L i ).
The designed filter utilizes both linearization techniques as shown in Figure 6 with resistors R1, R2, and R3 and the source-degenerated transistors operating in the triode region: M9-M10, M19-M20, and M29-M30.This design improves filter linearity with the trade-off in power consumption and degradation in noise performance.

Simulation results
All the simulations used the post layout extraction to have realistic parasitic values.Microcircuits of inductor and diode junction capacitor models were used.As shown in Figure 1, the DC voltage at the cathode terminal of the diode is near to the 1.8 V DC supply.The voltage swing in the LC tank is controlled to be under 400 mV.In order to keep the junction away from its forward biasing zone, the tuning voltage is restricted to a maximum of 1.4 V.In the simulation, the frequency tuning voltage is varied from −0.6 V to 1.4 V and the center frequency changed from 3.672 GHz to 3.519 GHz. Figure 9(a) shows simulation results of the center frequency versus tuning voltage.The Q tuning range depends on stability and pass band ripple of the filter.In the simulation, when Q was tuned over 50, the pass band ripple of the filter exceeded 0.5 dB.For a Q over 100, the filter became unstable due to its high gain.The maximum Q tuning range was chosen to be under 50 shown in Figure 9(b).There is a relationship between the tuning of frequency and the Q of the filter.To change frequency, capacitance of the resonator must be adjusted; the changing in capacitance varies quality factor according to the following relationship: Therefore, in order to maintain a desired bandwidth, for every shift in frequency, the quality factor needs to be readjusted (i.e., changing R in ( 5)). Figure 10 illustrates the tuning ability of the filter using a combination of both tunings.For a reasonable high gain, the tuning range is about 140 MHz.When the gain is adjusted too high, the filter exhibits a narrow bandwidth but with an unacceptable ripple.
Figure 11 shows the bandwidth and gain tuning ability of the filter by changing the bias voltage.A bandwidth adjustment between 48 MHz to 125 MHz can be achieved.Figure 12 shows the noise performance of the 3 stages.The LNA affects overall noise figure of the filter.Obviously, as more stages are cascaded, more noise is added into the filter.The minimum noise figure can be achieved is around 14 dB at the target frequency.
Linearity of the filter is simulated using a two-tone test.By applying two sinusoidal signals of equal power P in and different frequencies f 1 and f 2 to the filter, the output power spectra P out at frequencies f 1, ( f 2), and P IM3 at (2 f 2 − f 1) and (2 f 1− f 2) were measured.By plotting P out and P IM3 versus input power P in , the input referenced output 1dB compression point IP 1dB and the input referenced third-order intercept point IIP 3 were obtained.A summary of the simulation results at different Q of the sixth-order filter is listed in Table 3.

Circuit layout and fabrication
The filter was laid out using Cadence layout tools for Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm CMOS technology.This filter was designed for the 1.8 V DC supply.The total chip size is 0.9 × 0.9 mm 2 including 20 bonding pads.These are power supply, two control voltages for the Q tuning and for the center frequency tuning, analog inputs, and analog outputs.Three RF outputs from 3 stages are provided for testing purposes.Using three outputs, the filter can be used as second, fourth, or sixth order as desired and can be tuned to a narrower bandwidth.Figure 13 shows the layout and micrograph of the fabricated filter; the symmetry layout and the surrounding power rings are clearly shown.

Testing results
The IC was tested using the HP 8722 ES/ET microwave network analyzer and a spectrum analyzer.The filter was mounted on a PCB with appropriate supply and tuning voltages.The device under test was considered as a two-port network to measure its parameters.To determine frequency tuning range of the filter, the frequency tuning voltage was varied between −0.6 V to 1.2 V and the results were plotted and shown in Figure 14.The tuning of Q was required in this test in order to maintain the same bandwidth for every frequency setting.The frequency tuning is 300 MHz (3.54 GHz-3.88GHz) which is much larger than the simulated result of 140 MHz.The difference may come from the inaccuracy of the varactor model and over-estimation of the fixed parasitic capacitances.To determine the bandwidth tuning ability of the filter, frequency responses under different Q tuning voltages were measured and shown in Figure 15.The bandwidth of this filter can be tuned between 35 MHz to 95 MHz to be usable at its maximum center frequency of 3.8 GHz.This comes short from the simulated values of 48 MHz-125 MHz.By measuring the reflection coefficient, the input matching was determined and found to have a perfect match around 3.8 GHz.
The other measurement results are reported in Table 4.
A comparison of this design to previously reported works on on-chip bandpass filters is given in Table 5.The filter in this work uses the most advanced CMOS technology.As indicated, this filter operates at the highest frequency using the lowest supply voltage.In addition, both frequency and bandwidth are tunable while majority of the filters have both values fixed or self-tuned.The designed features of this filter provide an easy interfacing of the tuning signals for frequency and bandwidth adjustments.The designed inductor has the best Q among some of the previous designs.However, this filter consumes more power than the other filters listed in Table 5.For example, it uses 22 mW/pole compared to 15 mW/pole in [14].Majority of the power is consumed by the 3 linearization resistors R1, R2, and R3 in Figure 6.This is a trade-off between power consumption and linearity.Another trade-off for a better linearity is the increase in NF of this design (15 dB) while the filter in [14] obtains an NF of 7 dB as the resistors in this filter are the sources of noise.In overall, the designed filter uses a simple tuning scheme for a wide bandwidth and achieves higher image rejection, larger tuning range, and much higher linearity compared to other filters.

CONCLUSIONS
A tunable bandpass filter was designed using the main stream 0.18 μm CMOS technology at the 3.6 GHz range.Three second-order filters were cascaded to form a sixth-order filter to have higher image rejection and wider bandwidth.The bandwidth and center frequency of the filter are tunable using a simple tuning scheme for practical applications.An innovative method was employed to set apart the center frequencies of the stages in order to obtain a wider bandwidth and a single voltage was used to tune all 3 stages.In addition, the bandwidth tuning requires only a single tuning voltage.The tuning scheme greatly simplifies the filter and makes it more applicable to commercial applications.The design employed inductive degeneration technique to minimize the noise at the input stage.Careful layout and design techniques were employed to develop better quality inductors in the CMOS technology.The causes of poor circuit linearity were identified and corrected to improve the filter performance.Test results show the frequency deviation and the inaccuracy of the tuning range in the fabricated filter compared to the simulation results.These errors may come from the inadequate accuracy in modeling of the inductors and varactors.This design shows new achievements in this research field: 3.6 GHz BPF using standard CMOS, high quality inductor, tunable center frequency and bandwidth, and high image rejection for a high gain filter.However, this filter suffers high-power consumption compared with other filters designed in the past because of the use of resistors to improve linearity; this problem must be fixed for portable applications.The tunable ability of the design seems useful to be investigated further for the feasibility of using this feature as a channel-select filter.

Figure 1 :Figure 2 :
Figure 1: Block diagram and simplified schematic diagram of the second-order BPF.

Figure 3 :
Figure 3: The designed varactor and its model.

Figure 4 :Figure 5 :
Figure 4: Q of the varactor as a function of its reverse bias voltage.

Figure 6 :Figure 7 :
Figure 6: A simplified schematic diagram of the sixth-order BPF (bias circuits are not shown).

Figure 12 :
Figure 12: Noise performance at different stages of the filter.

Table 2 :
Component values of the sixth-order bandpass filter.

Table 3 :
Simulation results of the sixth-order filter.

Table 4 :
Measured and simulated results of the sixth-order filter.

Table 5 :
A comparison of this design to other publications.