Low Phase Noise and High Conversion Gain Oscillator Mixer Constructed with a 0.18-μm CMOS Technology

This paper presents a compact down-conversion oscillator mixer fabricated with a 0.18-μm CMOS technology. The oscillator mixer consists of a conventional nMOS differential coupled oscillator, a switch stage, and a pMOS cross-coupled pair which is used to release the design constraint between the conversion gain and the start-up condition. Since the switch stage and the pMOS crosscoupled pair are stacked on the nMOS differential oscillator, the bias currents of the switch stage and the pMOS cross-coupled pair can be entirely reused, so as to reduce the power dissipation. The experimental results show a conversion gain of 6.5 dB at 2.1 GHz associated with a single-sideband (SSB) noise figure of below 13 dB. The oscillator mixer also exhibits a tuning range of 184 MHz and a phase noise of −116 dBc/Hz at 1-MHz offset from the LO frequency of 6.8 GHz, and it consumes 11 mA from 1.8 V bias voltage.


Introduction
Low power and highly integrated circuits (ICs) are key issues for developing components or modules of wireless communications systems.Hence, work undertaken during the past few years has focused on achieving higher levels of integration and low current consumption.Many efforts have been made to combine the oscillator and mixer into a single unit for such purposes [1][2][3][4][5].
In the work [2], a 2-GHz 1.6-mW phase-locked loop (PLL) fabricated by using a 0.6-μm BiCMOS technology was proposed.The oscillation and mixing function is achieved by stacking two differential pairs on ring oscillator for low power consumption.However, the oscillator mixer employs inductive peaking, level shift, and extra speed-up current sources to improve start-up condition and fasten speed of VCO core; these additional circuits make the design more complicated and increase parasitic capacitances which will reduce VCO's tuning range.
Another double-balanced oscillator mixer constructed with a 0.18-μm CMOS technology has been reported to exhibit good performance and a compact configuration [3].
In such a CMOS oscillator mixer, the LO output signal is generated by the nMOS-only differential VCO which is directly fed into the source of the switching pair.Although, the configuration can be operated under low voltage supply, an extra bias voltage is needed for appropriate circuit operation.And the characteristics, for example, linearity and conversion gain, may be limited due to the demand for the low power dissipation.
To further reduce power consumption for global positioning system (GPS) applications, a RF front-end receiver topology merging LNA, mixer, and VCO into a single stage called the LMV cell is presented [4].The LMV cell utilizes the intrinsic mixing functionality of a LC-tank oscillator to provide a compact and low-power solution.The virtual short-circuit is used to sense the output IF current for that to reduce conversion gain is sensitive to parasitic capacitors present at the IF nodes.However, to avoid a design tradeoff between LNA and VCO, a low-frequency degeneration circuit must be introduced, attenuating the 1/f noise injected by the LNA core into the VCO.
In [5], a similar work has made to integrate a thirdharmonic self-oscillating mixer with an antenna to form high-performance receiver on a low-loss printed circuit board (PCB).However, the communication system may still be implemented using an MMIC technology as operation frequency significantly increases.
In this paper, a new circuit architecture that consists of a mixer and a VCO is proposed.Among this study procedure, we know that the proposed oscillator mixer cannot be synthesized by directly connecting an nMOS-only VCO and a mixer stage, however, the match problem and the amount of the bias current between the two circuits must be carefully considered.By using an additional pMOS cross-coupled pair to separate their bias currents and to compensate the loss of the LC-tank, it still preserves the characteristics of the low phase noise and the high conversion gain.

Oscillator Mixer Topology.
Since active mixer has a larger gain than a passive mixer and relax noise performance of following circuit blocks, most down-converter ICs employ active mixer configurations.One of the commonly used active mixers is the double-balanced Gilbert mixer which mainly comprises an input transconductance stage, an LO switch stage, and output loads shown in Figure 1.The transconductance stage is applied to translate voltage-form RF signals into current-form RF signals.The switch stage is used to mix the RF currents with LO signals to generate IF signals.However, the parasitic capacitances (C par ) between the switch's sources and ground not only provide leakage paths that degenerate Gilbert mixer's conversion gain, but also corrupt input third-order intercept point (IIP3) due to the nonlinear characteristics of the parasitic elements.The above drawbacks will become more and more serious as circuit's operation frequency increases.Moreover, the parasitic capacitances also form an indirect mechanism that causes noise pulse to appear at output of Gilbert mixer and Circuit schematic of a mixer with static current injection.
have been quantitatively derived as follows [5]: where T is the period of the LO signal, g ms is the transconductance of the LO switches, and V n is the equivalent flicker noise of the switching pair.Based on (1), one can know that it rapidly goes up as the capacitances and the LO frequency increase.To alleviate the effect of the parasitic capacitances, a direct-conversion mixer to use current bleeding circuit and two resonating inductors has been proposed [6,7], as shown in Figure 2. It had demonstrated that conversion gain and flicker noise performance of a Gilbert mixer are improved simultaneously by making the inductors (L 1,2 ) to resonate with the capacitors (C par ), and the transistor M p conduct the most parts of the bias current for improving flicker noise of the switch stage (V n ).Nevertheless, the main goal in this paper is to preserve the above superior mechanism and to merge VCO and mixer into a single block for low power application.
A new configuration of oscillator mixer is obtained by translating the transistors (M 5 and M 6 ) of Figure 2 into a cross-coupled pair.Based on this structure, the transistors (M 5 -M 6 ) and the inductors (L 1 -L 2 ) construct the nMOSonly VCO that provides oscillation signal to drive the sources of the switch pairs, of which gates are controlled by the RF signals.However, to guarantee that the oscillator mixer can work properly, a fundamental design criterion is to make the VCO's start-up condition hold.Such a condition may be satisfied if the negative resistance provided by the nMOS cross-coupled pair is enough to compensate the loss caused by the lossy LC tank.Moreover, we also have to reduce the parasitic capacitors (C par ) so as to improve the phase noise of the VCO core due to its bad quality factors.Thus, it is straightforward that the transistor sizes (M 1 -M 4 ) must be reduced and high-Q inductors must be adopted.But Q factors of integrated inductors on CMOS substrate are quite low, and the use of small-sized switching transistors will degenerate the conversion gain of the mixer.To resolve the problem, one useful design strategy is to increase the bias current of nMOS cross-coupled pair through a current source realized by pMOS (M p ).However, based on experimental results, the architecture still needs an excess bias current to maintain good performance for higher frequency applications.Therefore, a new structure of oscillator mixer that employs a pMOS cross-coupled pair to alleviate the confined design between the conversion gain and the startup condition, and uses the inductors (L 1 -L 2 ) for the free of voltage headroom and flicker noise is proposed, as shown in Figure 3.The oscillator mixer plotted in the figure ignores the gate bias (V RF ) of the switching pair.

Voltage Gain Analysis.
We assume that the differential LO signal of the VCO core is big enough to turn on or off the switch transistors.Thus, the circuit of Figure 3 is substituted with the half circuit of Figure 4.The frequencies of RF signals are assumed to be higher than those of the LO signals and to be considered as small signals.So, the switch time-variant conductance g(t) can be derived as where V LO is the LO magnitude and V S is the source voltage of the transistors (M 1 -M 2 ), V RF is the dc bias for RF.Although the poor-quality parasitic capacitors, varactor and inductor losses are compensated by the cross-coupled pairs and are resonated at the frequency ω LO , the resonant condition is not suitable for the RF signals.In other words, to calculate the voltage gain of the half-circuit should include the source impedance (Z s,OM (ω)).By following an analogous deviation of differential amplifier, the IF voltage gain is written as where g 1,2 (t) is the conductance of the differential pair (M n1,n2 ), p(t) is polarity of the differential IF voltage, and L 1,2 is the output load.According to (3), we know that the channel resistance of the nMOS cross-coupled pair (M n1 ,M n2 ) and the LC-tank has critical effects for the voltage gain of the oscillator mixer.So, for improving the voltage gain of the oscillator mixer, it is preferred to adjust the widths of the nMOS cross-coupled pair as the LC-tank value must be chosen to be resonated at the required LO oscillation frequency in the proposed circuit.However, altering the sizes of the nMOS transistors affords a tradeoff between low phase noise and high conversion gain.Hence, a largely inductive load may be a better choice for the oscillator mixer.where r p is the parasitic resistance of the inductor, g n,p is the conductance of the cross-coupled pairs, Q ind and I B are the Q factor of the inductor (L) and the bias current of the VCO, respectively.Δω is the offset frequency from the carrier, and Γ rms is the rms value of the effective impulse sensitivity function (ISF) which represents the time-varying sensitivity of the distributions of phase noise.The parameter γ has a value of unity at zero V DS and 2/3 in saturation region with long channel devices.Equation ( 4) demonstrates that L(Δω) = f (Q ind , I B , C var ) can be improved by increasing Q ind , or designing I B near the maximum position in currentlimited regime.By taking derivation of ( 4) with respect to the varactor C var , we can know that VCO's phase noise is associated with tuning range.In this work, a narrow-tuned varactor is chosen to reduce the variation of the phase noise in the range of the control voltage (V ctrl ).

Oscillator Mixer Design Analysis.
Based on ( 3) and ( 4), we realize that the performance of the conversion gain and phase noise is related to the conductances of the switching and the pMOS cross-coupled pairs.To gain deeply insight into the problem, Figure 5 reports the simulations of the conversion gain and the phase noise versus the ratio of I p /I sw .Here, I sw and I p stand for the bias currents of the switching transistors and the pMOS cross-coupled pair, respectively.Notice that we must ensure the sum of I sw and I p to be as consistent as possible through all simulated cases in despite of resulting a little difference for the wanted oscillation frequency (the variation approximate ±75 MHz at the center frequency of 6.8 GHz).Since the summed current is entirely reused by the nMOS cross-coupled pair, the percentage of the current reuse is 100%.Based on simulated results, the oscillator mixer can provide good performance while maintaining suitable bias points; that is, V DD and V RF should be set to 1.8 V and 1.35 V, respectively.The detail design parameters of the proposed oscillator mixer are listed in Table 1.The simulated results of Figure 5 shows that the conversion gain drops rapidly as the bias currents in the switch stage reduces, and the phase noise has not obvious variation while the ratio is larger than 7.The quick attenuation of the conversion gain is that it mainly depends on the switch's transconductance under the assumption of the fixed source impedance (Z s,OM ( ω)).The slow variation of the phase noise is that the VCO core has been operated at the current-limited regime while I p /I sw is set to 7. For optimizing phase noise, besides to alter VCO's bias current, channel noise in active transistors and output parasitic capacitors (C par ) must also be considered [10].This paper mentioned that the ISFs (Γ rms ) of the VCO's crosscoupled pairs strongly depend on the parasitic capacitances between LC-tank outputs and ground if high impedance levels at the sources of nMOS and pMOS cross-coupled pairs is absent.

Experimental Results
Figure 6 shows die photograph of the prototype, of which chip area including probe pads is 0.88 mm × 1.12 mm. 8 GHz, the self-generated oscillation signal is adjusted to 6.9 GHz by using V ctrl = 0.2 V.The power consumption of the switching pair is about 3.13 mW and a higher power of 17 mW is consumed by the VCO core to obtain the request amplitude level for achieving the high conversion gain and low phase noise.These measured results also reveal that the LO-to-IF isolation and RF-to-IF isolation in both cases are higher than 18 and 16.4 dB, respectively.The suppressed capability of the oscillator mixer that relates to LO and RF signal leakages is not good enough.It may be due to the merged mixer-VCO structure and the imperfect layout of the switching pair.Both phase noise and tuning range were measured using an Agilent E5052A Signal Source Analyzer and an E5053A Downconverter.Figures 8 and 9 show the measured phase noise and tuning range of the oscillation signal which is delivered from CMOS buffers, respectively.The measured phase noise is −116 dBc/Hz at 1-MHz offset from the LO carrier, and the tuning range is 184 MHz.The performance of VCO is evaluated with a figure of merit defined in the work [11] FOM(dBc where S SSB is the signal sideband noise at offset frequency f offset , and f c and P diss are the carrier frequency and DC power consumption of a voltage-controlled oscillator.The figure of merit (FOM) of the prototype is about −180 dBc/ Hz. Figure 10 plots the measured 1-dB compression point (P1dB) that is about −11 dBm associated with a conversion gain of 6.5 dB while the RF input signal is 9.6 GHz.The twotone test for third-order intermodulation distortion (IIP3) is shown in Figure 11.The test is performed at the RF frequency of 9.2 GHz, and tone spacing is 10 MHz.The measured IIP3 is about 1.5 dBm.

Conclusion
A compact down-conversion oscillator mixer operated in Xband is proposed.The oscillator mixer mainly constructed with an nMOS-only VCO and a switch stage.However, to improve start-up condition and achieve high conversion gain, an additional pMOS cross-coupled pair is employed.
In this work, it was demonstrated by adjusting the ratio of I p /I sw , which is the ratio of the currents that flows into the pMOS transistors and the switching transistors, the oscillator mixer can achieve the high conversion gains and low phase noises as well.As the pMOS cross-coupled pair and the switch stage are stacked on the VCO core, these bias currents are entirely reused by the nMOS cross-coupled pair so that the total power consumption maybe reduced.A prototype was fabricated using CMOS 0.18-μm technology to validate the design concept.A summary of the measured results is provided in Table 2 along with a comparison to other oscillator mixer; it shows that the proposed configuration of the oscillator mixer demonstrates the characteristics of an moderate conversion gain and power consumption, and a low phase noise.

Figure 4 :
Figure 4: Half-circuit diagram of the oscillator mixer.

Figure 5 :
Figure 5: Conversion gains and phase noises versus different current ratio.

Figure 6 :
Figure 6: Photograph of the oscillator mixer with a size of 0.88 mm × 1.12 mm.

Figure 7 :
Figure 7: (a) Measured IF output spectrum of the oscillator mixer using the RF frequency of 8.9 GHz, and (b) the RF frequency of 9.6 GHz.

1 Figure 8 :
Figure 8: Measured phase noise of the oscillator mixer.

Table 1 :
Component design values of the proposed circuit.

Table 2 :
The performance comparisons of other oscillator mixers and the proposed circuit.The prototype was fabricated in 0.18 μm 1P6M CMOS technology provided by TSMC foundry.The chip was tested by mounting the prototype on a low-loss Teflon PCB board, which contains one RF rat-race hybrid and two bias-tees.The total drawing currents that exclude the LO buffers are 11 mA.Figures7(a) and 7(b) depict the IF output spectrums of the oscillator mixer without using additionally integrated IF buffer amplifiers.In the measurements, the RF test signals that have the same input power of −15 dBm are set to 8.9 and 9.6 GHz, respectively.To yield the IF signals of 2.1 and 2.