Finding the Energy Efﬁcient Curve: Gate Sizing for Minimum Power under Delay Constraints

A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading o ﬀ some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, ﬁnding new sizes for the gates such that the circuit satisﬁes the speed goal while dissipating minimal power. Energy/delay gain (EDG) is deﬁned as a metric to quantify the most e ﬃ cient tradeo ﬀ . The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the ﬁnal stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power e ﬃ cient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability a ﬀ ect the optimal gate sizes in the combined optimization of speed and power.


Introduction
Optimizing a digital circuit for both energy and performance involves a tradeoff, because any implementation of a given algorithm consumes more energy if it is executed faster. The tradeoff between power and speed is influenced by the circuit structure, the logic function, the manufacturing process, and other factors. Traditional design practices tend to overemphasize speed and waste power. In recent years power has become a dominant consideration, causing designers to downsize logic gates in order to reduce power, in exchange for increased delay. However, resizing of gates to save power is often performed in a nonoptimal way, such that for the same energy dissipation, a sizing that results in better performance could be achieved.
In this paper, we explore the energy-performance design space, evaluating the optimal tradeoff between performance and energy by tuning gate sizes in a given circuit. We describe a mathematical method that minimizes the total energy in a combinational CMOS circuit, for a given delay constraint. It is based on an extension of the Logical Effort [1] model to express the dynamic and leakage energy of a path as well as the delay. Starting from the minimum achievable delay, we apply the method for a range of longer delays, in order to find the optimal energy-delay relation for the given circuit. We show that downsizing all gates in a fast circuit by the same factor does not yield an energy-efficient design, and we characterize the differences between gate sizing for high speed and sizing for low power.
In trading off delay for energy, we are interested only in a subset of all the possible downsized circuits2014those implementations that are energy efficient. A design implementation is considered to be energy efficient when it has the highest performance among all possible configurations dissipating the same power [2,3]. When the optimal implementations are plotted in the energy-delay plane, they form a curve called the energy efficient curve. In Figure 1, each point represents a different hardware implementation. The implementations which belong to the energy efficient family reside on the energy efficient curve.
Zyuban and Strenski [3,4] introduce the hardware intensity metric. Hardware intensity (η) is defined to be the ratio of the relative increase in energy to the corresponding relative gain in performance achievable "locally" through 2 VLSI Design gate resizing and logic manipulation at a fixed power-supply voltage for a power efficient design. Simply put, it is the ratio of % energy per % speed performance tradeoff for an energy-efficient design. Since speed performance is inversely proportional to delay, where D is delay, E is the dissipated energy, and η represents the hardware intensity. The hardware intensity is a measure of the "differential" energy-performance tradeoff (the energy gained if the delay is relaxed by a small ΔD around a given delay and energy point on the energy efficient curve), and is actually the sensitivity of the energy to the delay. As shown in [3], each point on the energy efficient curve corresponds to a different value of the hardware intensity η. The hardware intensity decreases along the energy efficient curve towards larger delay values. According to [3], η is equivalent to the tradeoff parameter n in the commonly used optimization objective function combining energy and delay: In [5], Brodersen et al. formalize the tradeoff between energy and delay via sensitivities to tuning parameters. The sensitivity of energy to delay due to tuning the size W i of gate i is defined as where θ(W i ) is the sensitivity, D is the delay, E is the energy, ∂E/∂W i is the derivative of energy with respect to size of device i, and ∂D/∂W i is the derivative of delay with respect to size of device i. To achieve the most energy-efficient design, the energy reduction potentials of all the tuning variables must be the same. Therefore, for an energy efficient design, (3) is equivalent to (1) for all points on the energy efficient curve. The focus of this paper is on the conversion to low power of circuits that were optimized only for speed during their initial design process. Optimal downsizing is applied to each gate for each relaxed delay target, such that the whole energy efficient curve is generated for the circuit. Note that the gate sizes are allowed to vary in a continuous manner between a minimum and a maximum size. While the resultant gate sizes would be mapped into a finite cell library in a practical design, the continuous result for some basic circuits provides guidelines and observations about CMOS circuit design for low power.
The rest of this paper is organized as follows: The design scenario is described in Section 2. Usage of logical effort to analyze the delay and energy is described in Section 3. The optimization problem is formalized in Section 4. Typical circuit types are analyzed in Section 5. Section 6 concludes the paper.

Power Reduction Design Scenario
Typically, an initial circuit is given, where speed was the only design goal. In order to save energy, the delay constraint is relaxed, and the gates sizes are reduced. For example, consider Figure 1, with the initial circuit implementation 0, which is energy efficient. While relaxing the delay constraint (moving from D 0 to D 1 ), the design gets downsized, which results in circuit implementation 1.
To calculate the energy gain achievable by relaxing the delay by X percent, we define a metric we call "Energy Delay Gain" (EDG). The EDG is defined as the ratio of relative decrease in energy to the corresponding relative increase in delay, with respect to the initial design point (D 0 , E 0 ). D 0 is the initial delay (not necessarily the minimum achievable delay), and E 0 is the corresponding initial energy. Note that the EDG defines the total energy-performance tradeoff, as opposed to the differential tradeoff-the hardware intensity. Mathematically, EDG at a given delay D with corresponding energy E is defined as For example, assuming that the initial design point in Figure 1 is implementation 0, then the EDG of point 1 is Figure 2 illustrates the difference between hardware intensity and EDG. It shows the energy efficient curve of a given circuit, where D 0 is the initial delay, and E 0 is the corresponding initial energy. The hardware intensity is the ratio between the slope of the tangent to the energy efficient curve at point (D, E) to the slope of the line connecting the origin to point (D, E). The EDG is the ratio between the slope of the line connecting points (D 0 , E 0 ) and (D, E), to the slope of the  Resizing of the gates to tradeoff performance with active energy is the most practical approach available to the circuit engineer. Continuous gate sizes has been used for optimizing delay under area constraints and vice versa [6]. Other degrees of freedom include logic restructuring, tuning of threshold voltages or supply voltage, and power gating. Changing the threshold voltage affects mainly the leakage energy, and not the dynamic energy dissipation [7,8], so does power gating [9,10]. Logic restructuring of the circuit could be an effective method to trade off energy and performance, by reducing the load on high activity nets, and by introducing new nodes that have a lower switching activity [11]. However, changing the circuit topology may increase the time required for the design process to converge. Changing the supply voltage is an effective technique as well [3,5,7,[11][12][13][14]. However, in most cases, changing the supply voltage for a subcircuit requires major changes in the package and in the system and therefore is not practical. For instance, latest state-of-the art CPUs include only 1-2 power planes [15,16].
In the following sections, we set up an optimization framework that maximizes the energy saving for any assumed delay constraint in a given combinational CMOS circuit. It determines the appropriate sizing factor for each gate in the circuit. For primary inputs and outputs of the circuit we assume that fixed capacitances. Given activity factor and signal probability are assumed at each node of the circuit. The result of this optimization process is equivalent to finding the energy-efficient curve for the given circuit.

Analytical Model
The optimization problem we solve is defined as follows. Given a path in a circuit with initial delay (minimum or arbitrary) D 0 and the corresponding energy consumption E 0 , find gate sizing that maximizes the EDG for an assumed delay constraint. We use the logical effort method [1] in order to calculate the delay of a path and adapt it to calculate the dynamic and leakage energy dissipation of the circuit.
For a given path (Figure 3), we assume that constant input and output loads and an initial sizing that is given as input capacitance for each gate. For each gate we apply a sizing factor k. The input capacitance of the resized ith gate is expressed as the initial input capacitance C 0i multiplied by k i . The energy-delay design space is explored by tuning the k's.
The following properties are defined: M i : number of inputs to gate i, AF j i : activity factor (switching probability) of input j in gate i, AF i o : output activity factor of gate i, g i : logical effort of gate i, p i : parasitic delay of gate i, C 0i : initial capacitance of gate i that achieves initial path delay (corresponds to (D 0 , E 0 )), C offi : off-path constant capacitance driven by gate i, P leaki : the average leakage power for gate i, for a unit input capacitance, k i : sizing factor for gate i. The k's are used in the gate downsizing process. For each gate i, k i · C 0i is the gate size. Although specified, k 1 is assumed to be 1 (constant driver).

Energy of a Logic
Assuming that the voltage amplitude for each net in the design is the same (V cc ), we can define a parameter called dynamic capacitance (C dyn ), which is the switching energy normalized by V cc . The dynamic capacitance of a gate i (C dyn i ) is 4 VLSI Design Figure 3: Example path. Each gate is assigned with logical effort notation, initial input capacitance (C 0i ) and sizing factor (k i ).
Without loss of generality, we assume that the first input of each gate resides on the investigated path. We assume that the inputs of the gates we deal with are symmetrical (input capacitance on each input pin is equal) and the gates are noncompound (i.e., gates implementing functions like a · b + c are out of scope). Our method can be easily extended to support these types. Under these assumptions, all input capacitances of a given gate are identical. Therefore, the input where AF i is defined to be Mi j=1 AF j i -sum of activity factors for input pins of gate i. Note that unlike calculating the delay of a gate, when calculating the gate energy, all input and output nets of a gate have to be taken into consideration. The C dyn of the nets not in the desired path should not be overlooked.
The output capacitance of a gate is defined to be its self loading and is combined mainly of the drain diffusion capacitors connected to the output. The parasitic delay of gate i in logical effort method, denoted by p i , is proportional to the diffusion capacitance. The logical effort of gate i, denoted by g i , expresses the ratio of the input capacitance of gate i to that of an inverter capable of delivering the same current. It is easy to see that the output capacitance of gate i can be expressed as We can now rewrite (7) using the notation defined previously: Besides the gates in the path, we have to take into account the C dyn of the side loads. Multiplying C offi by AF 1 i results in the C dyn of the off-path load driven by gate i. We use (10) to calculate C dyn of a desired path: Substituting input C dyn with (8) and C outi with (9), and rearranging the formula, we get By defining we get The initial C dyn is achieved by setting all k i s to 1: VLSI Design 5 where T cycle is the cycle time of the circuit, and P leaki is the average leakage power for gate i, for a unit input capacitance. P leaki is a function of the manufacturing technology, gate topology, and signal probability (SP: the probability for a signal to be in a logical TRUE state at a given cycle) for each input. See [8,17,18] for leakage power calculation methods. Under a given workload, P leaki should be precalculated for each gate i. Since P leaki is sensitive to the signal probability, it needs to be recalculated whenever the workload is modified, to reflect changes in gates' signal probability. By dividing the leakage energy by V 2 cc , we can express the leakage in terms of capacitance: And the total C leak is equal to: The initial C leak is achieved by setting all k i s to 1: By combining (14), (15), (18), and (19) we can express the total capacitance and the initial capacitance of a desired path: The energy decrease rate (e dec ) due to downsizing of the gates by a factor of k is expressed as In order to estimate the upper bound of e dec , we assume an initial design point with minimum delay for C 0 path , and set the sizes of the gates in the path to minimum allowed feature size (C min ), to reflect the minimum possible C path . By defining We get By using (23), the upper bound to the EDG at a given delay increase rate (d inc )-EDG MAX (dinc) can also be calculated, simply by dividing e MAX dec by d inc : EDG MAX (dinc) can be used by the circuit designer to quickly evaluate the potential for saving power. However, the designer should note that the value of EDG MAX (dinc) is a nonreachable upper bound since the minimum sizing leads to a delay increase which is always greater than the one that the designer refers to. If the value of EDG MAX (dinc) is not sufficient, other energy reduction techniques should be considered.

Delay of a Logic
Path. When using the logical effort notation, the path delay (D) is expressed as The electrical effort of stage i (h i ) is calculated as the ratio between capacitance of gate i + 1 and gate i, plus the ratio of side load capacitance of gate i and input capacitance of gate i. For the sake of simplicity, k N+1 and k 1 are defined to be 1.
Using the notation defined earlier, the path delay D can be written as: By defining Equation (26) becomes The initial delay is achieved by setting all k i s to 1.

VLSI Design
And therefore, the delay increase rate (d inc ) due to downsizing of the gates by a factor of k i is

Optimizing Power and Performance
Given a delay value that is d inc percent greater than the initial delay D 0 , we seek the path sizing (C 02 · k 2 · · · C 0N · k N ) that maximizes the energy reduction rate e dec . From (21), maximizing e dec is achieved by minimizing C dyn . By ignoring the factors that do not depend on k i and will not affect the optimization process in (20), we define an objective function f 0 : Note that f 0 depends linearly on the dynamic and the leakage capacitances, which apply weights and determine the importance of each k i . Equation (31) can also be written as: Note that when all gates in a path are of the same type, all activity factors are equal, and average leakage power for all gates in the path is equal, both C dyn i and C leaki can be eliminated from (31) without affecting the optimization result. These conditions are satisfied on an inverter chain with input signal probability of 0.5, for instance. In this case, the leakage power of activity factor has no influence on the optimization result.
To get a canonical constraint goal, in which the constraint is less than or equal 1, we rearrange (30) to and define to get We now can use (35) to get an optimization constraint Combining (32) and (31) results in the following optimization problem: Minimize f 0 (k 1 · · · k N ), subject to f 1 (k 1 · · · k N ) 1, where However, f 1 defined above is nonconvex. We use geometrical programming [19][20][21] to solve the optimization problem, by changing variables So the equivalent convex optimization problem (which can be solved using convex optimization tools) is: The convexity of (39) ensures that a solution to the optimization problem exists, and that the solution is the global optimum point. In order to obtain the EDG curve, the delay increase rate is swept from 0 to the desired value, and for each delay increase value, a different optimization problem is solved by geometrical programming.
This result can be extended to handle circuit delay, instead of a single path delay. All paths must be enumerated, and the optimized delay should reflect the critical path delay. The critical path delay is calculated as the maximum delay of all enumerated paths. However, the MAX operator cannot be handled directly in geometrical programming, since it produces a result which is not necessarily differentiable. Boyd et al. [20] solve the general problem of using the MAX operator in geometrical programming (MAX( f 1 by introducing a new variable t, and N inequalities (N being the number of paths), to obtain t 1, This transformation can be used in order to feed the critical path into the optimizer. To calculate the energy-delay tradeoff, the C dyn of the entire circuit should be taken into account.
In the following sections, we employ this procedure to characterize the EDG and power reduction in typical logic circuits, and derive design guidelines.

Exploring Energy-Delay Tradeoff in Basic Circuits
We run numerical experiments that explore the EDG of some basic circuits. We use GGPLAB [22] as a geometrical programming optimizer, to solve the optimization problem (37) and (39). GGLAB is a free open source library and can be easily installed over Matlab. For each experiment, we provide an EDG curve which is obtained by optimizing the circuit for a wide range of increased delay values. Although the propagation delay and the active energy dissipation are technology independent, the leakage depends on the manufacturing technology and the circuit's cycle time. Throughout this section, the leakage is calculated according to the 32 nm technology node of the ITRS 2007 projection [23], in which C leakinv is calculated to be 0.5694, based on clock frequency of 2 GHz and signal probability of 0.5.

Inverter Chain.
Consider a chain consisting of N inverters, with output load of C out . C 01 is set arbitrarily to a constant value of 1 ff, and therefore the path electrical effort (H) is C out (Figure 4). We set initial gate capacitances (C 02 · · · C 0N ) that ensure minimum delay, using the logical effort methodology. The minimum delay was obtained by setting the electrical effort to be the N th root of the path electrical effort. The leakage calculation takes into account the signal probability of the inverters in the chain. Figure 5(a) shows the EDG for different combinations of path electrical effort (H) and chain length (N ) where the leakage energy is negligible. Figure 5(b) shows the same analysis, for negligible dynamic energy. In both cases, the largest potential for energy savings occurs near the point where the design is sized for minimum achievable delay. The potential for energy savings decreases as the delay is being relaxed further. This is consistent with the observation in [5]. Figure 6 shows the optimal sizing of a fixed input and output load inverter chain with an arbitrary activity factor and signal probability of 0.5, for various delay increase values. For input signal probability of 0.5, all the gates in the inverter chain have the same signal probability. Therefore, the optimization process is indifferent to the average leakage power of each gate-P leaki in (17) is constant and can be eliminated from (37).
The optimization process leads to increasing the electrical effort of the last stages and decreasing the electrical effort of the first stages, to meet the timing requirements ( Figure 6(f)). The largest energy savings, for a given delay increase value, are achieved by downsizing the largest gates in the chain (Figure 6(e)). The relative downsizing, however, is maximal around the middle of the chain (Figure 6(c)), due to the fact that the first stage and the load are anchored with a fixed size. In order to understand the behavior of the middle stages, a 16-stage inverter stage simulation is plotted    in Figure 6(d). As the delay increases, the gates towards the middle of the chain are downsized and form a plateau-like shape. Note that the optimal gate sizes might be limited by the minimum allowed size according to design rules.
Both Figures 6(a) and 6(b) (absolute sizing) and Figure 6(f) illustrate that as we move further from the minimal achievable delay (delay increase = 0, where all electrical efforts are identical), the difference between the electrical efforts of the stages increases. However, uniform downsizing (e.g., increase the delay by downsizing each gate by 5%) is sometimes used in the power reduction process by the circuit designer as an easy and straightforward method to trade off energy for performance. Figure 7 shows the energy efficient curve (optimal sizing) versus energy-delay curve generated by uniform downsizing of an 8-long inverter chain with out/in capacitance ratio of 200. The energy difference between the curves in the figure reaches up to 7%.
Most of the energy in the path is dissipated in the last stages of the chain, where the fanout factors are larger, in order to drive the large fixed output capacitance. Figure 8 demonstrates the effect of chain length on delay and energy. The external load of the circuit is relatively large-9pF, for which 8-long chain yields an optimal timing. The energy efficient curves for chains of 8, 6, and 4 inverters are plotted in the energy-delay plane. We can see that the number of stages is important when the optimal delay is required. Generally, as we move further from the smallest achievable delay, fewer inverters achieve better energy dissipation for the same delay. However, the difference in energy between the optimal number of inverters and a fixed number of inverters decreases as the delay is relaxed. Figure 9 shows good correlation between EDG MAX 10% see (24), and the actual energy delay gain. The energy saving opportunity increases when the output load is small, and when the number of stages in the path increases.

Activity and Signal
Probability Effect on Sizing. The more active a gate is, the more energy it consumes. In order to trade off delay and energy better, active gates in the timing critical path can be downsized more than inactive gates in the critical path. For instance, consider the circuit in Figure 10. The path from A to out is the timing critical. Input A has a fixed activity factor of 0.5, while the activity factor of input B is varied. In order to calculate the activity factor and signal probability of internal nodes, the method described in [24] for AF/SP propagation in combinational circuits is used-for a NAND gate with uncorrelated inputs A and B and output O, the activity at its output is calculated as: According to (41), the activity factor at the NAND's gate output is AF nand = 0.25 + 0.5AF B -the activity factor at the output of the NAND is controlled by the activity factor of input B, and monotonically rises as AF B increases. When the delay constrains of the circuit are relaxed, As AF B is increased, and with it AF nand , we expect that the gates that are driven by the NAND gate will get downsized at the expense of the gates driving the NAND gate. Figure 11 shows the sizing factor of each gate for various AF B values, for a delay increase rate of 20%. We see that as AF B increases, the sizing factor of gates 1 and 2 is increased, while the sizing factor of gates 5 and 6 is decreased.
A similar observation holds for leakage dominant circuits, where the signal probability becomes the affecting parameter instead of the activity factor. P leaki in (16) depends on the signal probability. Therefore, it is expected that the sizing of each gate during the optimization process will be influenced by the signal probability at the gate input. For example, in an inverter, where the Pmos transistor's size is twice the size of the N mos transistor, the leakage power of a single inverter can be estimated by:  Figure 11: Sizing factor to achieve 20% delay increase as AF b increases, the sizing factor of gates 1 and 2 is increased, while the sizing factor of gates 5 and 6 is decreased.
where SP is the signal probability in the input of the inverter, C in is the input capacitance of the inverter, and P leak (N mos, Pmos) is the leakage power of N mos and Pmos transistors respectively, per unit input capacitance. Figure 12 shows the sizes of the gates in a six-stage inverter chain with input capacitance of 1 ff and output load of 600 ff with a small activity factor, when the delay increase rate is varied from 0% to 50%. The optimal sizing at each stage is clearly affected  by the signal probability. Up to 50% difference in the sizing of the stages as a function of the signal probability can be observed (see delay increase of 50%, 4th stage).

Comparing Analytical and Simulation-Based Optimization.
In order to validate the correctness of the EDG optimization algorithm, the results of Section 5.1 are compared to simulation results. The simulation was performed using a proprietary circuit simulator combined with a proprietary numerical optimization environment, in a 32 nm process. The circuit was first optimized for minimum delay, which was used later as a reference. In order to get the EDG curves, the circuit was optimized by the simulation-based tool for minimum energy, for several delay constraints. Figure 13 presents the difference between the analytical computation (Section 5.1) and the simulation-based optimization. The error is small, and ranges from a maximum of 7% to a minimum of 0%. Obtaining the EDG curves using simulation-based optimization is orders of magnitude slower than running the proposed analytical method. Table 1 compares the run time of simulation-based optimization and the run time of the proposed analytical model for few inverter chain circuits. Note that simulation-based optimization run time increases dramatically as the circuit complexity increases. The analytical model was calibrated by computing the parasitics delay of an inverter (p) for the given technology, simply by comparing the output capacitance to the input capacitance of an unloaded inverter (see (9)).

Final Remarks and Conclusion
We have presented a design optimization framework that explores the power-performance space. The framework provides fast and accurate answers to the following questions.

VLSI Design
(1) How much power can be saved by slowing down the circuit by x percent?
(2) How to determine gate sizes for optimal power under a given delay constraint?
We introduced the energy/delay gain (EDG) as a metric for the amount of energy that can be saved as a function of increased delay. The method was demonstrated on a variety of circuits, exhibiting good correlation with accurate simulation-based optimizations. We have shown that around 25% dynamic energy can be gained when the delay constraint is relaxed by 5% in an optimal way, for circuits in 32 nm technology which were initially designed for maximal operation speed. An upper bound of power savings in a given circuit can be obtained without optimization, in order to quickly assess whether a downsizing effort may be justified for the circuit.
The method described in this work can be used by both circuit designers and EDA tools. Circuit designers can increase their intuition of the energy-delay tradeoff. The following rules of thumb can be derived from the experiments.
(i) Minimum Delay Is Power Expensive. By relaxing the delay, significant amount of dynamic energy could be saved. We have shown that under given conditions, for a 2-bit multiplexer up to 40% of dynamic energy could be saved when the delay constraint is relaxed by 10%.
(ii) A fixed Uniform Downsizing Factor for all Gates in the circuit would lead to an inefficient design in terms of energy. The optimal downsizing factor is not uniform.
(iii) Increase delay by downsizing the "middle" gates. In order to save energy with minimal impact on timingthe gates located in the middle (between he input and the load) are downsized the most. The downsizing factor increases as the delay constraint relaxes.
(iv) Increase Delay by Increasing the Electrical Effort towards the load. Minimum delay design requires a constant tapering factor. Typically, a "fanout of 4" is used [1]. Minimum energy design (when neglecting short circuit power) requires high tapering factor, that decreases the number of stages. When performance is compromised to save energy, the tapering factor of the stages must increase towards the external load. The tapering factor increases as the delay constraint is relaxed. Note that this result is applicable only when the external load is larger than the input capacitance.
(v) Downsizing of the Gates Reduces Both Dynamic energy and Leakage Energy Dissipation. Both dynamic energy and leakage energy dissipation depend linearly on the size of the gates. By downsizing the gates, both dynamic and leakage energy are reduced.
(vi) The Power Optimization Has to Be Performed under a Given Work-load. The activity factor and signal probability influence the optimized circuit's sizing. Different tests may result in different sizing. Using random tests, rather then typical tests to optimize the circuit may lead to sub-optimal design.