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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18

It is time we explore the well-engineered deep submicron CMOS technologies to address the challenging criteria of these emerging low-power and high-speed communication digital signal processing chips. The performance of many applications as digital signal processing depends upon the performance of the arithmetic circuits to execute complex algorithms such as convolution, correlation, and digital filtering. Fast arithmetic computation cells including adders and multipliers are the most frequently and widely used circuits in very-large-scale integration (VLSI) systems. The semiconductor industry has witnessed an explosive growth of integration of sophisticated multimedia-based applications into mobile electronics gadgetry since the last decade. However, the critical concern in this arena is to reduce the increase in power consumption beyond a certain range of operating frequency. Moreover, with the explosive growth, the demand, and the popularity of portable electronic products, the designers are driven to strive for smaller silicon area, higher speed, longer battery life, and enhanced reliability. The XOR-XNOR circuits are basic building blocks in various circuits especially arithmetic circuits (adders & multipliers), compressors, comparators, parity checkers, code converters, error-detecting or error-correcting codes and phase detector.

Adder is the core element of complex arithmetic circuits like addition, multiplication, division, exponentiation, and so forth. There are standard implementations with various logic styles that have been used in the past to design full-adder cells [

Power is one of the vital resources, hence the designers try to save it while designing a system. Power dissipation depends upon the switching activity, node capacitances (made up of gate, diffusion, and wire capacitances), and control circuit size. At the device level, reducing the supply voltage

To summarize, some of the performance criteria are considered in the design and evaluation of adder cells and some are utilized for the ease of design, robustness, silicon area, delay, and power consumption. The paper is organized section wise. Section

In recent years, several variants of different logic styles have been proposed to implement 1-bit adder cells [

Full adder circuits can be divided into two groups on the basis of output. The first group of full adders have full swing output. C-CMOS, CPL, TGA, TFA, Hybrid, 14T, and 16T belong to the first group [

There are standard implementations for the full-adder cells which are used as the basis of comparison in this paper. Some of the standard implementations are as follows.

CMOS logic styles have been used to implement the low-power 1-bit adder cells. In general, they can be broadly divided into two major categories: the Complementary CMOS and the Pass-Transistor logic circuits. The complementary CMOS (C-CMOS) full adder (Figure

C-CMOS adder cell.

The pass-transistor logic (PTL) is a better way to implement circuits designed for low power applications. The low power pass-transistor logic and its design analysis procedures were reported in [

Pseudo nMOS full adder cell operates on pseudo logic, which is referred to as ratioed style. This full adder cell uses 14 transistors to realize the negative addition function. The advantage of pseudo nMOS adder cell is its higher speed (compared to conventional full adder) and less transistor count. The disadvantage of pseudo nMOS cell is the static power consumption of the pull-up transistor as well as the reduced output voltage swing, which makes this adder cell more susceptible to noise. To increase the output swing, CMOS inverter is added to this circuit.

Newly designed full adder [

TG-Pseudo adder cell.

Another full adder is the Complementary Pass Transistor Logic (CPL) with swing restoration, which uses 32 transistors [

Some designs of the full adder circuit based on transmission gates are shown in Figure

TG adder cell.

More than one logic style is used for implementation of the hybrid full adders. The hybrid adder cells may be classified into various categories depending upon their structure and logical expression of the Sum and Carry output signals. All hybrid designs use the best available modules implemented using different logic styles or enhance the available modules in an attempt to build a low power consuming full-adder cell [

In [

Basic designs of XOR-XNOR gate found in literature.

XOR-XNOR (6T)

4T XOR (4T)

XOR (3T)

XOR-XNOR (3T)

A new set of low power four transistor (4T) XOR and XNOR circuits called powerless P-XOR and Groundless G-XNOR, respectively, is proposed in [

Generally, the main aim is to reduce the number of transistors in the adder cell and consequently to reduce the number of power dissipating nodes. This is achieved by utilizing intrinsically low power consuming logic styles like TFA, TGA or simply passing transistors. There are three main components to design a hybrid full adder circuit [

In this category, signal Sum is generated using, either two cascaded XOR or two cascaded XNOR modules. Figure

In this category, Sum and Carry are generated using intermediate signals XOR and XNOR. In this group, output Sum and Carry are generated faster than the outputs in cascaded output full adders. The key point here is to produce intermediate signals simultaneously. Otherwise, there may be glitches, unnecessary power consumption, and longer delay. Figure

In [

Another 10T full adder based on centralized structure is shown in Figure

XOR-XNOR- (3T-) based 10T full adder.

In nine transistor (9T) full adder circuit, we have only one 3T XOR gate as is shown in the Figure

9T full adder.

The above equation shows that by increasing channel width (

The design of an eight transistor (8T) full adder using 3T XOR gates is shown in Figure

8T full adder.

Another 8T full adder using centralizer output condition contains three modules—two 3T XOR gates and one multiplexer (2T). It can work at high speed with low power dissipation due to minimum number of transistors and small transistor delay.

The Majority function is a logic circuit that functions as a majority vote to determine the output of the circuits [

Boolean algebra with three variables is used to facilitate the conversion of a sum-of-products expression to minimize majority logic as shown in Table

Majority expression of standard logic functions.

Standard Boolean function | Majority expression | Function implementation diagram |
---|---|---|

The majority structure is implemented by three input capacitors. These three input capacitors prepare an input voltage that is applied for driving static CMOS buffer. The majority gates may be designed with more inputs by this method by increasing the number of input capacitors. The capacitor network is used to provide voltage division for implementing majority logic as explained below.

Total current

The input capacitors shown in Figure

Switching voltage at output node

Inputs | Voltage at | Majority Not | ||

0 | 0 | 0 | 1 | |

0 | 0 | 1 | 1 | |

0 | 1 | 0 | 1 | |

0 | 1 | 1 | 0 | |

1 | 0 | 0 | 1 | |

1 | 0 | 1 | 0 | |

1 | 1 | 0 | 0 | |

1 | 1 | 1 | 0 |

Implementation of Majority functions (MOSCAP).

In this section hardware implementation and construction of MOSCAP are discussed. Tying the drain and source of a MOSFET together results in a MOSCAP. Many realizable alternatives such as Poly-Insulator-Poly capacitors (PIPCAP), Metal-Insulator-Metal capacitors (MIMCAP), or Metal-Oxide-Semiconductor capacitors (MOSCAP) can be utilized for realizing the capacitor network. However, MOSCAP has an advantage of more capacitance; less chip area. The nMOSCAP usually has lesser capacitance in comparison to pMOSCAP for the same area, so pMOSCAP is used for implementing the capacitor network. Table

Channel width v/s MOS capacitor in 0.18

Cap | 2.89 fF | 4.89 fF | 6.89 fF | 8.89 fF | 10.91 fF |
---|---|---|---|---|---|

Width ( | 1.59 | 2.71 | 3.83 | 4.95 | 6.07 |

Figure

Majority function- (MOSCAP-) based logic gates.

There are two methods to design the NAND and NOR logic circuits. First method is the transistor sizing that shifts the voltage transfer curve (VTC) to the left and right by changing the ratio of (

Simulation results in Table

Simulation results of NAND, NOR, and majority Not logic gates at 1 V.

Design | Static Majority function | MOSCAP Majority function | ||||

Delay (ps) | Power ( | PDP (10^{−18} j) | Delay (ps) | Power ( | PDP (10^{−18} j) | |

NAND | 36 | 0.041 | 1.47 | 23 | 0.038 | 0.87 |

NOR | 40 | 0.042 | 1.68 | 27 | 0.039 | 1.05 |

Maj. Not | 43 | 0.048 | 2.06 | 18 | 0.038 | 0.68 |

The layout of Majority Not function (MOSCAP) and static CMOS bridge-type Majority function circuits are shown in Figures

Simulation layout comparisons of Majority function logic.

Bridge Majority function | MOSCAP Majority function | |||||

Layout | Length ( | Width ( | Area (^{2}) | Length ( | Width ( | Area (^{2}) |

Dimen. | 8.8 | 6.9 | 60.7 | 9.9 | 2.95 | 29.2 |

(a) MOSCAP Majority Not function layout. (b) Static CMOS bridge (Majority function) layout.

As Table

Truth table for Majority-function-based full adder.

Inputs | Full adder logic outputs | ||||

Carry | |||||

0 | 0 | 0 | 0 | 1 | 0 |

0 | 0 | 1 | 0 | 1 | 1 |

0 | 1 | 0 | 0 | 1 | 1 |

0 | 1 | 1 | 1 | 0 | 0 |

1 | 0 | 0 | 0 | 1 | 1 |

1 | 0 | 1 | 1 | 0 | 0 |

1 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 0 | 1 |

The basic logic design of a full adder includes two 3-input NAND and NOR gates with Majority Not function inputs as shown in Figure

Design methodologies for Majority-function-based full adder (MajFA1).

In six mid-states of Table

In this section full adder based on low power design of 3-input Majority Not function (MOSCAP) with standard logic gates is discussed. The Boolean expression may be expressed as

The MajFA2 full adder uses 12 transistors, and 3 capacitors are based on pseudo CMOS structure with MOSCAP Majority function. Full adder output

The full adder (MajFA3) is based on MOSCAP Majority Not function with only static CMOS inverter as shown in Figure

(a) Majority-function-based full adder (MajFA2). (b) Inverter-based Majority full adder (MajFA3).

Here if we exert a Majority function of five inputs out of which two are

Reference [

In the full adder circuit shown in Figure

3-input MOSCAP Majority full adder (MajFA4).

As reported in MajFA5, hybrid full adder circuit in Figure

5-input MOSCAP Majority full adder (MajFA5).

The general structure of a XOR-based full adder consists of one exclusive OR/NOR function (XOR/XNOR), two transmission gates in the middle, and one XOR gate to the right as shown in Figure

General structure of proposed XOR-XNOR-based adder.

The circuit is a combination of two logic styles and offers high-speed, low-power consumption and energy efficiency. Lowering the supply voltage appears to be a well-known means of reducing power consumption. However, lowering the supply voltage also increases the circuit delay and degrades the drivability of cells designed with certain logic styles. By selecting proper (

XOR- (3T-) based design 1 full adder.

XOR-XNOR- (3T-) based design 2 full adder.

In design1 full adder circuit, XOR circuit comprises M1, M2 and M3 transistors and the output of M4 and M5 transistor is XNOR circuit. TG (M6, M7) and TG (M8, M9) give the carry and restored output swing. TG (M10, M11) and pass transistor M12, M13 are used for Sum output and to restore the output swing as shown in Figure

A novel 16-transistor full adder circuit that generates XOR-XNOR outputs simultaneously is shown in Figure

In the proposed methodology, we have designed two full adder topologies, one is based on static bridge logic style and other is based on dynamic bridge logic style. The proposed adder modules enjoy advantages of the bridge style including low-power consumption and the simplicity of the design. The proposed full adder structure design (PMajFA1) is based on capacitor network and Majority Not function as shown in Figure

Majority-function-based adder design 1 (PMajFA1).

The proposed Majority-function-based adder design has some advantages which improves the metrics of the proposed design significantly. In the reported previous full adder design [

Furthermore, as in the proposed design three capacitors perform voltage summation to implement scaled-linear sum instead of five capacitors. It has larger noise margins than the previous design. Moreover, the proposed design have no threshold loss problem at its nodes and has higher noise margin compared to MajFA3 (minimum no of transistor) because its inverters has normal VTC curve, which works on inverters with shifted VTC and its operation is highly dependent on the proper operation of these inverters.

The Majority-function-based proposed design 2 (PMajFA2) adder uses 15 transistors and is based on regular dynamic CMOS bridge transistors. Full adder output

Majority function-based adder design 2 (PMajFA2).

The simulation has been performed for different supply voltage ranging from 0.8 V to 1.8 V, which allows us to compare the speed degradation and average power dissipation of the reported and newly designed adder topologies. The results of the designed circuits in this paper are compared with a reported standard CMOS full adder circuit. To compare one-bit full adder’s performance, we have evaluated delay and power dissipation by performing simulation runs on a Cadence environment using 0.18-

The simulation test bench used for load analysis is shown in Figure

Simulation test bench for load Analysis.

The transistors that are used in XOR-XNOR- (3T-) based full adder designed circuits (13T & 16T) are using 3T transistors XOR logic. Thus the area overhead of the designed circuits is lower than that of the reported conventional adders and also some other adder circuits. By optimizing the transistor size of full adders considered, it is possible to reduce the delay of all the adders without significantly increasing the power consumption, and transistor sizes can be set to achieve minimum ^{−18} j) and EDP (10^{−30} sj) are a quantitative measure of the efficiency and a compromise between power dissipation and speed. PDP and EDP are particularly important when low power and high speed operation are needed. At low voltages, design 1 is better than 9T and design 2. From the simulation results, it is perceptible that design 1 is superior in PDP to all the other designs at all simulation conditions.

Each one-bit full adder has been analyzed in terms of propagation delay, average power dissipation, and their products. By the value of delay, power, power-delay product and energy delay product of C-CMOS, hybrid and newly designed full adders are measured. The smallest voltage that could work on 10T is 1.4 V. The lowest supply voltage for simulation comparison for conventional CMOS, and newly designed full adder circuits, is 0.8 V (

High speed of the designed full adders is due to the short path between input and output logic circuit. Simulation results (Figure

(a) Delay (ps) of XOR-XNOR-based adders. (b) Power (

Figure

Simulation results (Figure

(a) Delay of Majority-function-based full adder circuits. (b) Power of Majority-function-based full adder circuits.

Output load is one of the important parameters that affects power and performance of the circuits. Here we changed the output loads from 2 fF to 500 fF. A fixed value 1 fF capacitance has been added at the output of the buffer circuit. Minimum output load for all the simulation is 2 fF, except for the case in which we study the effect of output load on full adder. The effect of output load is shown in Figures

(a) PDP and EDP of XOR-XNOR based full adder cells with load capacitance (2 fF) at 1.8 V. (b) PDP and EDP of XOR-XNOR based full adder cells with load capacitance (500 fF) at 1.8 V.

(a) PDP comparison of Majority-function-based full adder cells with capacitance load variation at 1.8 V. (b) PDP comparison of Majority-function-based full adder cells with capacitance load variation at 1 V.

9T is the best circuit in terms of power consumption since it has the least power consuming for all values of output load. The power of the designed circuits changes sharply by increasing the output load capacitance value as shown in Table

Majority-function-based design 1 full adder (PMajFA1) is the best circuit in terms of power consumption for all values of output loads. The power of the designed circuits changes sharply by increasing the output load capacitance value at 1 V. At 2 fF load, Design 2 full adder (PMajFA2) is the fastest circuit. According to the simulation results, design 1 (PMajFA1) and design 2 (PMajFA2) has the lowest PDP among the other circuits for all output load capacitors as shown in Figure

With regard to the implementation area obtained from the layouts, it can be seen that the proposed full adders require the smallest area, which can also be considered as one of the factors for the lower delay and power consumption, as it implies smaller parasitic capacitances being driven inside the full adder. Table

Area comparisons of the XOR-XNOR-based adders.

Designs | CMOS | TGA | 10T | 9T | Design 1 | Design 2 |
---|---|---|---|---|---|---|

Length ( | 17.5 | 14 | 11.2 | 10.1 | 15.5 | 15.2 |

Width ( | 7.1 | 9.6 | 6.3 | 8.2 | 5.15 | 6.6 |

Area (^{2}) | 124.2 | 135 | 71 | 82.8 | 80 | 100.3 |

(a) Layout of design 1 (13T) full adder cell. (b) Layout of design 2 (16T) full adder cell.

(a) Layout of design 1 (PMajFA1) full adder cell. (b) Layout of design 2 (PMajFA2) full adder cell.

The values of layout circuit length, width, and overall area are listed in Table

The compact designed layout of the newly design full adders using 0.18

Area comparisons of the Majority-function-based full adder cells.

Designs | MajFA1 | MajFA3 | MajFA4 | PMajFA1 | PMajFA2 |
---|---|---|---|---|---|

Area (^{2}) | 104.5 | 96 | 97 | 128 | 64 |

An alternative internal logic structure for designing full adder cells is introduced. In order to demonstrate its advantages, four full adders were built in combination with pass-transistor powerless/groundless logic styles. Different adder logic styles have been implemented, simulated, analyzed, and compared. Using the adder categorization and hybrid-CMOS design style, many full adders can be conceived. As an example, new full adders designed using hybrid-CMOS design style with pass transistor are presented in this paper that targets low PDP. The hybrid-CMOS full adder shows better performance than most of the other standard full-adder cells owing to the new design modules proposed in this paper. The compared simulation result shows that the performance of the new designs is far superior to the other reference design of full adder circuits under different load conditions and for other simulation parameters.

The authors wish to thank Professor Jose Carlos Monteiro and the anonymous reviewers for their constructive comments and suggestions.