Transformer-based shunt single pole, double-throw (SPDT) switches are analyzed, and design equations are provided. A mm-wave transformer-based SPDT shunt switch prototype was designed and fabricated in 90 nm digital CMOS process. It has a minimum insertion loss of 3.4 dB at 50 GHz from the single pole to the ON-thru port and a leakage of 19 dB from the single pole to the OFF-thru port. The isolation is 13.7 dB between the two thru ports. Large signal measurements verify that the switch is capable of handling +14 dBm of input power at its 1 dB compression point. The fabricated SPDT switch has a minute active area size of
Transmit/receives switches implemented in standard CMOS technologies are key mm-wave building blocks for demonstrating the ultimate goal of a mm-wave single chip solution. Previous works [
At mm-wave frequencies, antennas can be realized in the package or on chip due to the relatively small wavelength. Higher performance is realized from package antennas due to the smaller conductive and dielectric losses compared to a silicon substrate. Multilayer boards with high-quality metallization not only provide good design environments for the antenna array but they can also be employed to route signal, power, and ground lines and furthermore act as a heat sink to take the dissipated power off the chip.
Even when antennas are implemented on a package, having a smaller package makes the over-all solution more cost-effective and allows for easier adoption of the solution by WPAN applications such as smart phones and portable media players. But whenever the package size is a secondary issue, then removing T/R switches should result in a better overall performance, since there is no extra component after the PA to harm the TX linearity and output power nor is there a component before the LNA which degrades the receiver noise figure and consequently sensitivity. However in practical cases, for solutions without the T/R switch, the bigger size of the package means longer on-package routings to connect front ends residing on the chip to the antennas implemented on the package (Figure
A T/R switch building block in a transceiver architecture (a). An antenna array which employs T/R switches (b) has half the footprint of the one without T/R switches (c).
To have a quantitative comparison, we consider the scenarios described in Figure
As can be seen from Figure
Graph of the maximum achievable communication range in two configurations of shared or separate arrays (for both small and large arrays). For larger arrays, the routing loss is more detrimental than the T/R switch loss and higher quality packaging should be employed (T/R switches were assumed to have
By its nature, when the gate terminal of a MOS transistor is driven by a rail-to-rail voltage, it acts as a switch. In fact, this single transistor switch is sufficient for many digital and analog applications. When the switch is on, the transistor is in the triode region and a low resistive channel connects the MOS source and drain terminals. To the first order, the on resistance of a MOS switch (
Measured
There are techniques to diminish the feedthrough path by cascading multiple switches (decreasing the effective series capacitance) and adding a shunt switch in between two series switches with an inverted gate signal with respect to the series switches (shorting out the feedthrough signal). These techniques (Figures
Combinations of series and shunt switches in a
The shunt SPDT switch configuration is demonstrated in Figure
A traditional microwave shunt switch (a), the proposed miniature structure (b), and the equivalent circuit (c).
Even at mm-wave frequencies,
Even after absorbing the capacitance of the interfacing blocks and utilizing slow-wave techniques to reduce the transmission line footprint, they are still bulky and devising a lumped component counterpart for the shunt SPDT switch is highly valuable. In this work, we demonstrate and analyze a transformer based shunt switch employing a transformer and shunt NMOS switches as shown in Figure
A transformer-based shunt switching structure is demonstrated in Figure
Unlike the traditional distributed switch, this structure introduces a
The equivalent circuit model depicted in Figure
Simplified model of the SPDT network including loading effects.
To derive the transfer function, the loading network depicted in Figure
Calculating the shunt equivalent loading network.
Since a lower desired loss requires a lower on resistance and consequently a larger transistor with more capacitive loading to operate at mm-wave frequencies, the smallest realizable inductance is preferred. So from now on we assume that the transformer is a 1 : 1 structure with self-inductance of
Parallel tank equivalent network of the switch for calculating the center frequency.
Neglecting the transformed shunt equivalent of the leakage inductance with respect to the magnetization inductance reduces the parallel tank depicted in Figure
The insertion loss due to the finite on resistance of the switch (
To calculate the leakage signal, we should consider that
To calculate the isolation, the input signal is connected to the off-thru port, and the signal reaching to the on-thru port is calculated (or vice versa). The situation is depicted in Figure
Equivalent circuit for calculating the isolation between the two thru ports.
Source network is transferred to the load side (a) and then the structure is converted to a parallel tank configuration (b).
The parasitic interwinding capacitances between the two loops of the transformer were not included in this analysis in order to have the order of the network low enough, and as a result of that to reach at some design equations that can be used as a guidance for obtaining close-to-optimum transistor and transformer sizes before plugging them in to the simulators for further optimizations.
However, if there are non-negligible feed-through capacitances between the two loops, the frequency response of the network would be down shifted, and there would be asymmetries between the frequency response from the single pole to the two different thru ports. As the polarity of the signal is inverted by choosing a different thru port, the voltage appearing on the feed-through capacitance changes and due to the Miller effect, it creates two different networks that the insertion loss through them can be different whether the operation is inverting or noninverting. The inverting configuration would have a higher insertion loss compared to the noninverting scenario [
After deriving design equations of a transformer-based shunt T/R switch presented in Section
Layout concerns of a MOS transistor when it is used as a high frequency switch is different from when it is expected to function as a high frequency amplifier. When a MOS transistor is laid out to be used in a mm-wave amplifier, smaller finger widths are used to decrease the series resistance of the gate terminal and as a result of that, lower losses and higher
For MOS transistors acting as a shunt switch, the input signal is supposed to be directed to the output port that its corresponding shunt transistor is in the OFF mode (
Higher biasing impedance at the gate not only improves the insertion loss but also results in less distortion to the output signal and a higher linearity number for the T/R switch.
On the other hand, if there is a large biasing impedance placed at the gate node, the gate terminal will be an AC floating node, and hence a feed through of output signal will appear at the gate terminal via parasitic paths provided by the transistor capacitances. As depicted in Figure
In conclusion, for the interest of linearity, large biasing resistors should be placed at the gate of MOS transistors intended for transmit/receive switching. Since that gate biasing resistance is in series with device’s poly gate resistance and much larger than that, the value of intrinsic series gate resistance of the device loses significance, and therefore, larger finger widths are exploited in the layout to make the overall transistor structure more compact and the impact of parasitic inductances caused by long interconnections less effective.
The same argument applies to the bulk terminal through the back-gate effect which makes larger substrate resistances desirable. To do so one can use a deep n-well option and bias the bulk of the transistor through an inductor which makes the bulk node open at the operating frequency. However, having a triple-well transistor with a bulk resonant network is not appealing at mm-wave frequencies for the following reasons. The added deep n-well region increases parasitic capacitances of the MOS transistor and limits its operating frequency. Transformer-based switches at mm-wave frequencies are quite compact and adding two bulk resonating inductors (one for each shunt transistor) roughly triples the size of the SPDT structure. Ground shields should also be placed around inductors in order to diminish the inductive coupling among the loops.
The other method to increase the substrate resistance is by having fewer number of bulk contacts (with respect to a MOS transistor specialized for high frequency amplifier design) and place them at a relatively far distance. These few contacts will provide the correct bias voltage for the substrate. However, for latchup and substrate coupling purposes, it is still beneficial to have a well-defined ring at an outer area. The space between this ring and transistor’s few bulk contacts can be filled with a p-well blocking layer in order to have a native substrate (as opposed to a highly doped surface) around the transistor to preserve the substrate resistance at a high desirable value (Figure
Layout example of a MOS transistor to be used as a switch.
Since this is a customized layout configuration and not included in standard libraries provided by the foundry, extraction tools will not be accurate in capturing all the device parasitic parameters. To have an accurate model of the transistor, a test structure is required to be fabricated and characterized so that a measured based custom model of that transistor is available for maximum accuracy of the design.
In our design an overlay structure for a 1 : 1 transformer was used. Two equally thick top metal layers were employed. The diameter of the octagon loop is 42
The prototype uses 40
A prototype SPDT T/R switch has been fabricated in a 90 nm CMOS process. The die photo is shown in Figure
Die microphotograph of the miniaturized shunt switch employing a transformer.
Measured insertion loss, leakage (input to the off-thru port), isolation (between the on-thru and off-thru ports), and return loss performance of the switch.
Large signal measurement (
When the input is connected to an on-thru output, there is
Comparison to recently published mm-wave T/R switches.
Ref. | ||||||
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Process | This work/[ |
[ |
[ |
[ |
[ |
[ |
90 nm CMOS | 130 nm CMOS | 90 nm CMOS | 90 nm CMOS | 65 nm CMOS | 90 nm CMOS | |
Frequency (GHz) | 50 | 60 | 24 | 72 | 82 | 60 |
Insertion loss (dB) | 3.4 | 4.5 | 3.5 | 2.7 | 4.2 | 1.5 |
Tx-RX isolation (dB) | 13.7 | 24 | 16 | 27 | 25 | 25 |
Supply voltage (V) | 1 | 1.2 | 1.2 | 1 | 1.2 | 1.2 |
|
14 | 4.1 | 28.7 | 15 | N/A | 13.5 |
Area ( |
0.004 | 0.221 | 0.018 | 0.14 | N/A | 0.27 |
Switching time (nS) | 0.25 | 0.4 | 10 | N/A | N/A | 3.1 |
This transformer-based shunt switch was implemented in a
A miniature lumped-element switch topology employing only a transformer and two shunt NMOS switches has been demonstrated. Shunt-only transistors make it more suitable for mm-wave frequencies. Design equations for the operating frequency, insertion loss, leakage, and isolation were derived in terms of the transformer inductance and coupling factor as well as transistors ON resistance and parasitic capacitances. A transformer-based single pole, double throw (SPDT) shunt switch prototype was designed and fabricated in 90 nm digital CMOS process. It has a minimum insertion loss of 3.4 dB at 50 GHz from the single pole to the ON-thru port and a leakage of 19 dB from the single pole to the OFF-thru port. The isolation is 13.7 dB between the two ports and the switch is capable of handling 14 dBm of power at its 1 dB compression point. The fabricated chip has a small active area of 60
This project was funded by C2S2. The authors acknowledge sponsors of Berkeley Wireless Research Center, the NSF Infrastructure Grant no. 0403427, and the foundry chip donation of STMicroelectronics. The authors would also like to thank Ashakn Borna for his help and support.