MOS Current Mode Logic with Capacitive Coupling

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.


Introduction
The rapid advances in the VLSI technology have led to the development of high-resolution mixed-signal applications.These applications demand high performance digital circuits to be integrated with analog circuitry on the same chip.MOS current mode logic (MCML) style has been widely used in digital circuits design for mixed-signal applications as they provide an analog friendly environment due to the low switching noise [1][2][3][4].MCML circuits exhibit high switching speed, high noise immunity and better power efficiency at high operating frequencies along with a drawback of static power consumption [5][6][7][8].
In mixed-signal applications, the digital circuits are extensively used in the realization of digital signal processor functional units such as finite impulse response (FIR) filter and FFT module.The functional units are required to perform computations at high speed to efficiently use the bandwidth in communication systems which is also increasing.Therefore it is necessary to improve the speed of conventional MCML circuits.In this paper, a new MCML style with capacitive coupling that increases the switching speed of the circuits is proposed.
The paper first presents a brief introduction to conventional MCML style in Section 2. Thereafter, the architecture of the MCML style with capacitive coupling is proposed in Section 3. The mechanism of capacitive coupling is explained, and an expression for the delay is derived.The theoretical propositions are validated through SPICE simulations using TSMC 0.18 µm CMOS technology parameters in Section 4. The simulation results of several logic gates and an asynchronous FIFO are also presented in the same section.Finally, the conclusions are drawn in Section 5.

Conventional MCML Circuits
A conventional MCML circuit consists of three main components which includes a pull-down network (PDN), a constant current source, and a load circuit.The circuit of a conventional MCML inverter is shown in Figure 1.Its PDN consists of a source-coupled transistor pair MC2-MC3 with input A. The constant current source MC1 generates the bias current I SS while the load MC4 determines the output voltage swing [9].The circuit works on the principle of current steering, where the bias current I SS is steered to one of the circuit branches depending on the input voltage.When the voltage at input A is high, the bias current I SS is steered to transistor MC2 and results in a low V OL (V OL = V DD − V P ) at the output node Q and a high voltage (V OH = V DD ) at the other node Q where V P is the voltage drop across the load [9].Conversely, when the input A is low, the bias current Current source I SS is steered to MC3, and a high voltage is obtained at the node Q.  (X, Y ) as V REF .The circuit also works on the principle of current steering.The phenomenon of capacitive coupling in the proposed circuit is described in the following section.

Capacitive Coupling.
In this section, the phenomenon of capacitive coupling in the proposed circuit is described, and an expression for the delay is derived.An expression for conventional MCML inverter delay, using the same method, is also given.

Capacitive Coupling Analysis.
The phenomenon of capacitive coupling occurs in the load during the transition at output node voltage.This can be explained by considering the half circuit of the inverter (Figure 2) and identifying the capacitances at different nodes in the load (M4-M5).The capacitances are shown in Figure 3 where C gdi , C dbi and C gsi represent the gate-drain capacitance, drain-bulk capacitance and gate-source capacitance of the ith transistor in the load.The capacitances C gs4 and C gd5 can be represented by the coupling capacitance between node Q and the intermediate node whereas C gd4 and C db5 are the capacitance between node X and ground as C X (C X = C gd4 + C db5 ).Initially, let the voltage at input A is assumed to be equal to high so that the voltage at Q is low For a high-to-low transition at the input, the transistor M2 turns off and the voltage at Q(V Q ) begins to rise from V OL to V OH .This change in the output voltage gets coupled to node X through C C .
Let i CC and i CX be the transient currents flowing through C C and C X , respectively.By applying the KCL, the current equation at node X can be written as where it is assumed that negligible current flows in transistor M5.Substituting the current values which can be rearranged as It can be observe that an increase in the output voltage will result in an increase in the voltage of the node X. Multiplying (3) by dt and integrating both sides give Completing the integral on the left side and rearranging it give where m = C C /(C C + C X ) represents the capacitance ratio and V REF = V DD + V T .Further V X (t) may be expressed as 3.2.2.Delay.The delay of the proposed MCML inverter can be modeled by solving the state equation of the output node in the time domain [10].The half circuit of the proposed MCML inverter with the parasitic capacitances of the transistors is shown in Figure 4(a), where C out represents the output that includes the interconnect capacitance and the input capacitance of the subsequent stage, respectively.The total capacitance at the output node C L is shown in Figure 4(b) which may be computed as The current through capacitor C L may be written as When the input switches from high to low, the current through transistor M2 becomes zero such that C L begins to charge through the load transistor M4.Thus, (9) reduces to The rising output voltage initiates the process of capacitive coupling in the load circuit.It is clear from (7) that the gate potential of M4 remains greater than or equal to V REF during the charging process, hence M4 operates in linear region throughout the switching process.Therefore, the delay t PLH may be calculated by solving (10) as Substituting i D,4 in ( 11) results in where k n,4 is the transconductance parameter of transistor M4 Evaluating the integral yields Equation ( 14) evaluates to Similar analysis for a conventional MCML inverter (Figure 1) gives the delay as where k p,4 , and V T,p are the transconductance and the threshold voltage of PMOS transistor MC4, respectively.

Simulation Results
This section first demonstrates the phenomenon of capacitive coupling in the proposed MCML inverter (Figure 2) to verify the theoretical propositions presented in Section 3.
Thereafter, the performance of the proposed MCML logic style is compared with the conventional MCML logic style by simulating different logic gates.Lastly, the simulation results for an asynchronous FIFO based on the proposed style are presented.All the simulations are performed by using TSMC 0.18 µm CMOS technology parameters with V T = 0.5 V and a supply voltage of 1.8 V.The bias current of all the circuits is taken as 100 µA uniformly. of node X which confirms the relation between voltages at node Q and X (3).Also, it can be observed that during a low-to-high transition at the output, for an output voltage V Q = 1.8 V the potential at node X raises V X = 2.54 V and is in accordance with (7) in Section 3. The delay of the proposed MCML inverter expressed by ( 15) is validated for different values of m ranging from 0.1 to 1.The error in the predicted and the simulated delay is plotted for different values of m in Figure 6 and is always is less than 12%.Thus, the simulation results are in close agreement with the theoretical values.

Performance Comparison.
Several logic gates such as inverter, five-stage ring oscillator (RO5), NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed MCML style and conventional MCML style are implemented for the purpose of comparison.The aspect ratios of the transistors in the PDN of the two styles are taken to be same.It may be noted that since all the circuits are implemented with the same supply voltage and bias current, therefore they will consume the same static power which is computed as the product of the supply voltage and bias current [4].The delay of the gates based on both the logic styles is listed in Table 1.It can be observed that an improvement varying from 16% to 23% can be obtained in delay by using the proposed MCML logic style.
Input A Voltage at node X, V X Voltage at output node Q, V Q Then, a request signal Req(out) is generated by the last stage to the receiver to enable the receiver to accept the data.This is followed by an acknowledge signal, Ack(in) from the destination to the last stage.The circuits of the control unit elements based on the proposed logic style are shown in Figure 8.The waveforms obtained through the simulation of a four-stage asynchronous FIFO are shown below in Figure 9.The first three waveforms correspond to the input data Data(in), request signal (Req in), and acknowledge signal (Ack out) at the sender section.The last three graphs are the acknowledge signal Ack(in), data Data(out) and request signal Req(out).It can be found that the asynchronous FIFO based on the proposed logic style outputs the sampled data correctly.

Conclusion
In this paper, a new MCML style with capacitive coupling to increase the speed of the digital circuits is proposed.The phenomenon of capacitive coupling occurs in the load of the proposed style.The coupling phenomenon has been explained and analyzed.An expression for the delay has also been derived and validated through SPICE simulations using TSMC 0.18 µm CMOS technology parameters.Several logic gates based on the proposed logic style are implemented and their performance is compared with the conventional logic  gates.It is found that a delay reduction of up to 23 percent delay reduction can be achieved by employing the proposed MCML style in the design of logic circuits.

Figure 3 :
Figure 3: Parasitic capacitances of the transistors M4 and M5 in the load circuit.

Figure 4 :
Figure 4: (a) Different capacitances in the half circuit of the proposed MCML inverter.(b) Half circuit of the proposed MCML inverter with load capacitance C L .

Figure 5 :Figure 6 :
Figure 5: Voltages at different nodes of the proposed MCML inverter.

Figure 9 :
Figure 9: Transient response of the 4-stage asynchronous FIFO based on the proposed MCML style.

Table 1 :
Delay comparison of logic gates.