Single OTRA Based AnalogMultiplier and Its Applications

This paper presents an analog multiplier using single operational transresistance amplifier (OTRA). The proposed circuit is suitable for integration as it does not use any external passive component. It can be used as a four-quadrant multiplier. Theoretical propositions are verified through PSPICE simulations using 0.5 μm CMOS parameters provided by MOSIS (AGILENT). The simulation results are in close agreement with theoretical predictions. The workability of the proposed multiplier is also tested through two applications, namely, a squarer and an amplitude modulator.

Recently the OTRA has emerged as an alternate analog building block [13][14][15][16][17][18][19][20][21][22][23][24][25][26] which inherits all the advantages of current mode techniques.The OTRA is a high gain current input voltage output device.The input terminals of OTRA are internally grounded, thereby eliminating response limitations due to parasitic capacitances and resistances [13] at the input.Several high performance CMOS OTRA topologies have been proposed in the literature [13][14][15][16].In the recent past OTRA has been extensively used as an analog building block for realizing a number of analog signal processing [17][18][19][20][21] and generation circuits [22][23][24].This paper presents a single OTRA based low voltage analog multiplier which does not use any external passive components and hence is suitable for integration.The proposed circuit can be used as a four quadrant multiplier without any change of topology.The workability of the proposed multiplier is demonstrated through two applications, namely, a squarer and an amplitude modulator.

The Proposed Multiplier Circuit
2.1.OTRA.OTRA is a three-terminal device, shown symbolically in Figure 1 and its port relations are characterized by the following matrix: where R m is transresistance gain of OTRA.For ideal operations R m approaches infinity and forces the input currents to be equal.Thus OTRA must be used in a negative feedback configuration.
Figure 2 Shows the CMOS realization of OTRA [15] which consists of the cascaded connection of the modified differential current conveyor (MDCC) [8] and common source amplifier.MDCC performs the current differencing operation and forces the two input terminals to be virtually grounded whereas the common source amplifier provides high gain.

Basic Multiplier Circuit.
where k is transconductance; W and L respectively represent the channel width and length of the of the MOSFET.The other terms have their usual meaning.Using (2) the currents through p and n terminals of OTRA, that is, i p and i n , respectively, can be expressed as (4) As R m approaches infinity the input currents are forced to be equal resulting in where K is a proportionality constant and is the inverse of difference of gate voltages of M 3 and M 4 .

Implementation Scheme for Superimposition of a Small
Signal on DC Bias.As can be seen from Figure 3 the gate voltage of M 1 is (V DC + v 1 ) which is a small signal superimposed over a dc bias.This voltage addition can be implemented using a scheme proposed in Figure 4 wherein v x is a small signal voltage and V C is a bias voltage.If M P1 and M P2 are matched transistors and are operating in saturation then their drain currents will be equal resulting in which gives The voltage given by ( 7) can be used as the gate voltage for transistor M 1 of Figure 3. Similarly gate voltage for transistor M 2 can be obtained from (7) by making v x = 0. Substituting these values of gate voltages in (5) the output of the multiplier gets modified to 2.4.The Proposed MOS Based Multiplier Structure.The complete MOS based multiplier structure is depicted in Figure 5 which incorporates the voltage addition scheme of Figure 4.
Figure 4: Scheme for implementing an ac superimposed on dc bias.As the transistors M 1 , M 2 , M 3 , and M 4 need to operate in the triode region for proper operation of the multiplier the following conditions should be satisfied: Now using (7) along with (9) the conditions for input signals v 1 and v 2 can be computed as These equations suggest that the dynamic input range of the multiplier is controlled by V C .

Nonideal Analysis
In this section the effect of finite transresistance gain of OTRA on multiplier is considered and compensation is employed for high frequency applications.Ideally the transresistance gain R m is assumed to approach infinity.However, practically R m is a frequency dependent finite value [13].
Considering a single pole model for the transresistance gain, R m can be expressed as For high frequency applications the transresistance gain R m (s) reduces to For high frequency applications the effect of transistor capacitances needs to be considered.Taking this effect into account the currents i p given by (3) modifies to where C gs1 is the gate to source capacitance of M 1 ; however, the current i n remains the same as (4).The effect of C gs1 can be compensated by adding a MOSFET M 9 , operating in triode region, at the inverting terminal of OTRA as shown in Figure 6.The effective gate to source capacitance of M 9 should be equal to C gs1 .This would result in i n as The third term in ( 14) results due to gate to source capacitance of M 9 .Substituting ( 12), (13), and ( 14) in ( 1), v o , the output of multiplier can be evaluated as And hence the 3 dB bandwidth of the multiplier can be expressed as

Simulation Results
The performance of the proposed multiplier of Figure 5 is verified through SPICE simulation using 0.5 μm CMOS process parameters provided by MOSIS (AGILENT).CMOS implementation of the OTRA [15] shown in Figure 2 is used and supply voltages are taken as ±1.5 V. Aspect ratios used for different transistors of OTRA are the same as in [15] and are given in Table 1.All the transistors M 1 -M 8 were used with equal aspect ratios having W/L = 1 μ/0.5 μ.Control voltage is taken as V C = 2 V, V C1 = 1 V, and V C2 = 1.25 V. Figure 7 depicts the dc transfer characteristics of the proposed multiplier.The transfer curve v o versus v 1 , with v 2 kept constant at 250 mV, is shown in Figure 7(a).It is observed that v o varies almost linearly with v 1 .The nonlinearity curve representing maximum percent deviation of the ideal transfer characteristic as a function of input voltage v 1 is shown in Figure 7(b).It is observed that the maximum nonlinearity over the entire input range does not exceed 2.05%.In Figure 7(c) v o is plotted with respect to v 1 for different values of v 2 .Voltage v 1 is swept from −300 mV to 300 mV while v 2 is varied from −150 mV to 150 mV in steps of 50 mV.It shows that the proposed circuit is a fourquadrant multiplier.
The frequency response of the proposed multiplier is shown in Figure 8 for which v 1 is kept constant at 200 mV whereas v 2 is taken as an ac source having amplitude 250 mV.The 3 dB bandwidth is found to be 8 MHz.
Figure 9 shows the total harmonic distortion (THD) as a function of input signal amplitude when a constant dc voltage (250 mV) is applied to v 2 while a 1 KHz sinusoidal signal is applied to v 1 with varying amplitude.It can be seen that the maximum THD remains under 0.2% for the entire input range.Total power consumption of the proposed multiplier is 0.83 mw when

Applications
5.1.Squarer.The proposed multiplier can be used as a squarer circuit if v 1 = v 2 = v in .The output of the multiplier is given by  Figure 10 shows the square transfer characteristics wherein v in is varied from −400 mV to 400 mV.
The observed output of the squarer is shown in Figure 11.The input signal is taken as a 300 mV, 500 KHz sinusoid.The squared output is shown in Figure 11(a) and the spectrum of the squared output is shown in Figure 11(b).

Amplitude Modulator.
The proposed multiplier, being a four-quadrant multiplier, can be used as an amplitude modulator (AM).A 5 KHz signal with 200 mV amplitude is multiplied by 250 mV, 50 KHz signal.Figure 12 shows the output of the proposed multiplier confirming the modulation function.The time domain response of the multiplier is shown in Figures 12(a

Conclusion
A single OTRA based analog multiplier is proposed which can be used as a four-quadrant multiplier also.The circuit does not require any passive element thus making it suitable  for integration.Its application as a squarer and an amplitude modulator is also discussed.Theoretical propositions are verified through PSPICE simulations using 0.5 μm CMOS parameters provided by MOSIS (AGILENT).Various performance parameters are analyzed through simulations and are found in close agreement to theoretical predictions.

Figure 3
Shows OTRA based multiplier structure.The transistors M 1 , M 2 , M 3 , and M 4 are matched transistors and operate in the linear region.In this paper v 1 and v 2 represent small signals, whereas V C1 , V C2 , and V DC are the bias voltages.OTRA inputs keep the sources of the two transistors M 1 and M 2 virtually grounded.The drain current for the MOS transistor operating in triode region is given by[27]

Figure 6 :
Figure 6: Complete multiplier circuit with C gs compensation of transistor M 1 .

v o versus v 1 with v 2
v o versus v 1 when v 2 is varied from −150 mV to 150 mV
) and 12(b) displays the frequency spectrum.

Table 1 :
Aspect ratio of the transistors in OTRA circuit.