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A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13 um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07 mm^{2}, and the synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility.

Over the past several years IEEE 802.11a/g wireless local area network (WLAN) [

Interleaver is mandatory in the physical layer of 802.11n. It plays a key role in exploiting spatial diversity and frequency diversity [

The remainder of this paper is organized as follows. Section

The interleaver used in IEEE 802.11a/g/n WLAN is block interleaver with block size corresponding to the number of bits in a single OFDM symbol. For 802.11a/g or 802.11n single-stream mode, the interleaving algorithm is defined by two permutations. If more than one spatial stream exists in the 802.11n physical layer, a third permutation called frequency rotation will be applied to the additional spatial streams. Let

The deinterleaver, which performs the inverse rotation, is also defined by three permutations. The first permutation reverses the third permutation of the interleaver. It is defined as

The second permutation reverses the second permutation in the interleaver. It is defined as

The third permutation reverses the first permutation of the interleaver. It is defined as

Generally, the implementing approaches for interleaver and deinterleaver can be classified in two categories, look-up-table- (LUT-) based approach and address-generation-unit- (AGU-) based approach [

For the hardware implementation of interleaver with AGU, the main challenge is to simplify address computation for AGU and at the same time meeting the high-speed requirements. In general, interleaving operation is realized by writing the incoming data stream into a memory matrix according to the permuted address, and then simply reading out data with sequential address [

Principle of the proposed design methodology.

Due to complex mathematical computation in (

In (

To describe the recursion of (

Permuted sequence from (

For the 16QAM case, the parameter

First the permuted sequence

Permuted sequence from (

For the 64QAM case, the parameter

We analyze (

Permuted sequence from (

It can be seen that the sequences inside brackets are identical for all the three cases. Hence, the permuted sequence from (

Submatrixes for (a) 16QAM and (b) 64QAM.

Proposed hardware structure for (

In (

Starting values for different modulation schemes.

Channel bandwidth | Spatial Stream | BPSK | QPSK | 16QAM | 64QAM |
---|---|---|---|---|---|

20 MHz | 1 | 0 | 0 | 0 | 0 |

2 | |||||

3 | |||||

4 | |||||

40 MHz | 1 | 0 | 0 | 0 | 0 |

2 | |||||

3 | |||||

4 |

Proposed hardware structure for (

The proposed hardware architecture for the IEEE 802.11a/g/n interleaver/deinterleaver is shown in Figure

Hardware architecture for interleaver/deinterleaver.

The state transition diagram for the control finite state machine (FSM) is shown in Figure

State diagram for the control FSM.

Since the deinterleaving operation is inverse of interleaving operation, the deinterleaver can be realized by alternating write address and read address of interleaver. Instead, we implement the deinterleaver via alternating the request signals of write address and read address in the control FSM. Whether the proposed design acts as interleaver or deinterlever is controlled by the input signal

At first, the proposed interleaver/deinterleaver is modeled in Verilog. The functional verification is done by comparing the results from ModelSim simulator with the results from original equations. After functional verification, the proposed interleaver/deinterleaver is synthesized into a 0.13

The implementation details and comparison results are shown in Table

Implementation details and comparison results.

IWCMC’05 [ | ASICON’09 [ | ISCAS’09 [ | This work | |
---|---|---|---|---|

Function | Int. | Int. & Deint. | Int. & Deint. | Int. & Deint. |

Standard | WWiSE Proposal to802.11n | 802.11n | 802.11n | 802.11a/g/n |

Parallel streams | 1 | 1 | 4 | 1 |

Parallel bits | 24 | 3 | 6 | 6 |

Technology | 0.18 | 0.13 | 65 nm | 0.13 |

Ping-pang buffer | Yes | Yes | No | Yes |

Memory area (^{2}) | 564587 | 53630 | 25136 | 63273 |

AGU and logic area (^{2}) | 168658 | 11270 | 9690 | 7049 |

AGU number | 1 | 1 | 3 | 1 |

Total area (^{2}) | 733245 | 64900 | 34824 | 70322 |

Max frequency (MHz) | 200 | 350 | 225 | 400 |

Normalized complexity | 5.205 | 0.667 | 0.765 | 0.417 |

The parameter MFS is the minimum feature size of target technology. In [

This paper presents a high-speed low-complexity interleaver/deinterleaver for IEEE 802.11a/g/n WLAN. Currently, it has been successfully integrated into a 2-stream 802.11a/g/n transceiver chip fabricated by SMIC. The proposed design methodology and hardware architecture can also be used to implement other block interleaver/deinterleaver. The interleaver/deinterleaver complaint to IEEE 802.16d/e standard or HiperLAN/2 standard can be obtained just by updating the parameter LUT in the proposed design. The comparison results show that the proposed interleaver/deinterleaver has lower hardware complexity and can run at higher working frequency compared with three other similar works, which makes it suitable for the IEEE 802.11a/g/n WLAN.

This work was supported by the Major National Science and Technology Program of China under Grant no. 2010ZX03005-001 and the National Natural Science Foundation of China under Grant no. 60976022.