Design of CDTA and VDTA Based Frequency Agile Filters

This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA).The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μmTSMCCMOS technologymodel parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage.


Introduction
The rapid evolution of wireless services has led to demand for one-fits-all "analog" front end solution.These services use different standards and therefore necessitate development of integrated multistandard transceivers as they result in reduction of size, price, complexity, and power consumption.The parameters of integrated transceiver can be modified in order to be able to adapt to the specifications of each standard [1].Practically, the designs employ either elements handling various standards in parallel or reconfigurable elements.The frequency agile filter (FAF) [1][2][3][4][5][6][7][8][9][10] characterized by adjustment range, reconfigurability, and agility may be used in transceivers.The term shadow filters is sometimes used in literature to refer to FAF [11,12].The literature survey shows that a limited number of topologies of active FAF are available and are based on op-amp [1] and current mode active block [2,3] and CMOS [4].
There is a wide range of current mode building blocks available in open literature.Among these blocks current difference transconductance amplifier (CDTA) [11] is most suitable for current mode signal processing owing to its low input and high output impedances, respectively.The VDTA is yet another recently introduced building block which works on a principle similar to that of CDTA except that the input current differencing unit is replaced by the voltage differencing circuit.Many applications such as filters and oscillators based on CDTA and VDTA are available and have been reported in the literature [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27] and references cited therein.
The main intention of this paper is to present CDTA and VDTA based frequency agile filter topologies.The proposed filters are suitable for integration as these employ grounded capacitors and a resistor.The paper is organised as follows.The FAF implementation scheme is briefly reviewed in Section 2. The CDTA based Class 0, Class 1, and Class 2 FAF are presented in Section 3. Section 4 deals with the realization of VDTA based Class 0, Class 1, and Class 2 FAF.In Section 5, nonideal analysis of filters is presented.Simulation results are provided in Section 6 to substantiate the proposed FAF topologies.The performance characteristics of filter topologies are described in Section 7. The paper is concluded in Section 8.

Implementation Scheme of FAF
The implementation scheme of frequency agile filter (FAF) [3] is briefly reviewed in this section.Class 0 FAF [3].The transfer functions of Class 0 FAF are given by (1) The center frequency ( 0 ) and quality factor () of the filter are represented by ( 2) and (3), respectively:

Class 1 FAF.
The basic block diagram of Class 1 FAF is shown in Figure 2 wherein the low pass output of the Class 0 FAF is amplified (with variable gain ) and fed back to the input.The characteristic frequency ( 0 ) and quality factor (  ) of Class 1 FAF are given by ( 4) and ( 5), respectively: =  √ (1 + ). (5)

Class n FAF.
The method outlined for Class 1 FAF realization can be extended for Class  FAF implementation as shown in Figure 3.This requires  amplifiers each with gain  ( 1 =  2 = ⋅ ⋅ ⋅ =  −1 =   ) to be placed in  feedback paths obtained in the same way as done in Class 1 implementation.The characteristic parameters of Class  FAF are given by Class (n − 1) FAF

CDTA Based FAF
The CDTA [11][12][13][14][15][16][17][18] consists of a unity-gain current source controlled by the difference of the input currents and a transconductance amplifier providing electronic tunability through its transconductance gain.The CDTA symbol is shown in Figure 4 and its terminal characteristics in matrix form are given by where  is transconductance of the CDTA.The CMOS implementation of CDTA [16] is given in Figure 5.
which can be adjusted by bias current  Bias of CDTA.3.1.CDTA Based Class 0 FAF.The CDTA based second order filter employing two CDTA blocks and two grounded capacitors is shown in Figure 6.The second CDTA block uses additional TA block with its current output terminals denoted by  +  and  −  .It provides both low pass and band pass responses at high output impedance and can be used as Class 0 FAF.The current flowing through  + and  − is controlled through transconductance  2 whereas current flowing through terminals  +  and  −  is controlled through  3 .The low pass and band pass transfer functions of CDTA based Class 0 FAF are given by ( 9) and (10), respectively: The center frequency and quality factor of Class 0 FAF are expressed as It may be noted that the  of the Class 0 FAF can be controlled independent of  0 by varying  3 .

CDTA Based Class 1 FAF.
The CDTA based Class 1 FAF is shown in Figure 7.It employs Class 0 FAF of Figure 6 along with an additional TA block (provides an output current which is product of its transconductance and voltage difference between noninverting (+) and inverting (−) terminals) and one grounded resistor.The TA block in the feedback path functions as an amplifier with tunable gain  as given in where  4 is the transconductance of TA block and is given by √2  (/) 19,21  Bias4 .
The low pass and band pass transfer functions of CDTA based Class 1 FAF are given by ( 14) and (15), respectively: The center frequency and quality factor of the CDTA based Class 1 FAF are expressed by ( 16) and (17), respectively:   amplifier is given by (18).The second CDTA block uses two additional TA blocks.It provides both low pass and band pass responses at high output impedance and can be used as Class 0 FAF.The current flowing through  + ,  − ,  +  , and  −  is controlled through transconductance  2 whereas current flowing through terminals  +  and  −  is controlled through  3 : The low pass and band pass transfer functions of CDTA based Class 1 FAF are given by ( 19) and (20), respectively: The center frequency and quality factor of the CDTA based Class 1 FAF are expressed by ( 21) and (22), respectively: The proposed filter uses grounded resistor of value  (= 1/) which can easily be implemented using the TA based structure given in Figure 9.

The VDTA Based FAF
The circuit symbol and the CMOS realization of VDTA [20,21] are shown in Figures 10 and 11, respectively.The VDTA consists of two transconductance (TC) stages termed as input and output stages.The input differential voltage (  −   ) is converted to current   through TC gain ( 1 ) of input stage and second stage converts the voltage at  terminal (  ) to current (  ) through its TC gain ( 2 ).The port relations of VDTA can thus be defined by the following matrix: The TC  1 and TC  2 are expressed by (24) which can be adjusted by bias currents  Bias1 and  Bias2 , respectively: 4.1.VDTA Based Class 0 FAF.The VDTA based Class 0 FAF employing single VDTA and two grounded capacitors is shown in Figure 12.This circuit configuration is based on second order filter presented in [21].However, to allow independent control of quality factor and center frequency an additional TA block with transconductance  2 is included in VDTA.The current flowing through  terminal is controlled by transconductance  1 whereas current flowing through   terminal is controlled by  2 .The terminal characteristics of the modified VDTA block are given by (25).The low pass and band pass transfer functions of VDTA based Class 0 FAF are given by ( 26) and ( 27), respectively: The center frequency and quality factor of Class 0 FAF are expressed by (28).The center frequency can be controlled by   Bias1 and  Bias3 whereas quality factor can be independently controlled by  Bias2 :

Advances in Electronics
and can be adjusted by varying  Bias3 and  Bias4 .
The low pass and band pass transfer functions of VDTA based Class 1 FAF are given by ( 30) and (31), respectively: The center frequency and quality factor of the CDTA based Class 1 FAF are expressed by (32) and (33), respectively.The center frequency can be independently controlled by varying  Bias2 without changing center frequency:   The low pass and band pass transfer functions of CDTA based Class 1 FAF are given by ( 35) and (36), respectively: The center frequency and quality factor of the CDTA based Class 1 FAF are expressed by (37) and (38), respectively:

Nonideal Analysis
In this section, nonideal analysis of CDTA and VDTA based Class 0 FAF is presented.6 shows that the parasitic capacitances present at  terminal can be easily accommodated in external capacitances.

Nonideal Analysis of
Reanalysis of the proposed circuit (Figure 6) yields the following nonideal transfer functions: where  Choosing operating frequencies below min(1/    , 1/    ) (as     ≪ 1 and     ≪ 1) the terms  1 and  1 would not affect the transfer function.For frequencies below min(  / 1eq ,   / 2eq ), (39c) modifies to and transfer functions (39b) and (39c) change to  The center frequency, quality factor of Class 0 FAF can be expressed as It is clear that the transfer functions and filter parameters ((40a), (40b) and (41a), (41b)) deviate from the ideal value in presence of nonidealities.The change can, however, be accommodated by adjusting bias currents.
Reanalysis of the proposed circuit in Figure 12 yields the following nonideal transfer functions of Class 0 VDTA based FAF.
Then where As   +   +   ≪  2 , (43c) modifies to Choosing operating frequencies below min (  / 1eq ,   / 2eq ) (44) reduces to and the transfer function (43b) simplifies to   And the filter parameters are calculated as It is clear that the transfer functions and filter parameters ((46a), (46b) and (47a), (47b)) deviate from the ideal value in presence of nonidealities.The change can, however, be accommodated by adjusting bias currents.

Simulation Results
In this section, the functionality of the proposed filters has been verified.The SPICE simulations results for CDTA and VDTA based filters have been presented using TSMC 0.25 m CMOS process model parameters and supply voltages of  DD = − SS = 1.8 V.
6.1.Simulation of CDTA Based FAF.The CMOS schematic of Figure 5 is used for verifying CDTA based FAF and the aspect ratios of the MOS transistors are given in Table 1.The additional TA blocks in CDTA providing current ports ( +  ,  −  ,  +  , and  −  ) use aspect ratios same as that for  + and  − .The capacitors  1 and  2 are chosen as 50 pF each.

Performance Evaluation
The performance of proposed CDTA and VDTA based FAF circuits is studied in terms of power dissipation, output noise voltage, and SNR.The overall performance characteristics are summarized in Table 3. Figures 27 and 28 depict the signal to noise ratio (SNR) for the proposed CDTA and VDTA based filter topologies for Class 0, Class 1, and Class 2, respectively.The VDTA based FAF proved to be optimum concerning the power dissipation and signal to noise ratio.The maximum output noise voltage is better in VDTA based FAF.

Conclusion
In this paper CDTA and VDTA based frequency agile filters are presented.The proposed FAF configurations employ Advances in Electronics grounded passive components and are suitable for integration.The filter configurations are designed in such a way that quality factor can be independently controlled without changing the center frequency.The simulation results are included to demonstrate the workability of the circuits.The performance of the proposed FAF is evaluated in terms of power dissipation, SNR, and noise performance.The VDTA based FAF proved to be optimum concerning the power dissipation and signal to noise ratio.

Class 0 Figure 19 :
Figure 19: Electronic center frequency control of CDTA based FAF.

Class 0 Figure 25 :
Figure 25: Electronic center frequency control of VDTA based FAF.
, respectively.The analytical and simulated responses describing variation of quality factor are shown in Figure18for different values of  Bias3 while setting  Bias1 and  Bias2 to 30 A.
Figure 19 depicts the analytical and simulated responses for center frequency variation for different values of  Bias1 and  Bias2 ( Bias1 =  Bias2 ) while setting  Bias3 to 0.5 A.To plot responses for Class 1 and Class 2 CDTA based FAF the bias current  Bias4 is taken as 10 A.The transient behaviour of proposed CDTA based FAF is also studied by applying input signals of frequencies 100 KHz, 500 KHz, 1 MHz, and 10 MHz, each having an amplitude of 10 A.The responses for Class 0 FAF are obtained by setting bias currents  Bias1 and  Bias2 each to 10 A and  Bias3 to 0.5 A.

Figure 20
shows the input and output waveforms along with their frequency spectrum for CDTA based Class 0 FAF.It may clearly be noted that the CDTA based Class 0 FAF allows only 1 MHz signal to pass and significantly attenuates signals of frequencies 100 KHz, 500 KHz, and 10 MHz.Similar responses for Class 1 and Class 2 FAF were also obtained.6.2.Simulation of VDTA Based FAF.The CMOS schematic of Figure 12 is used for verifying VDTA based FAF and the aspect ratios of the MOS transistors are given in Table 2.The capacitors  1 and  2 are taken as 50 pF each.In the realization of Class 2 FAF, the grounded resistor is implemented by TA block.The frequency responses of VDTA based Class 0, Class 1, and Class 2 FAF topologies are shown in Figures 21, 22, and 23, respectively.The responses are obtained by keeping  Bias2 to 5 A and setting bias currents  Bias1 and  Bias3 ( Bias =  Bias1 =  Bias3 ) to 5 A, 10 A, 30 A, and 60 A.In Figure 25 depicts the analytical and simulated responses for center frequency variation for different values of  Bias1 and  Bias3 ( Bias1 =  Bias3 ) and keeping  Bias2 to 5 A.To plot responses for Class 1,  Bias4 is set to a value in such a manner that  4 / 3 = 3 whereas  Bias5 is set equal to  Bias1 .The Class 2 FAF responses are plotted by setting  Bias6 to value such that  6 =  3 +  4 whereas  Bias7 is equal to  Bias4 .The transient behaviour of proposed agile filter is also studied by applying input signals of frequencies 100 KHz, 500 KHz, 1 MHz, and 10 MHz, each having an amplitude of 10 A.The responses for Class 0 FAF are obtained by setting bias currents  Bias1 ,  Bias2 , and  Bias3 each to 30 A.The input and output waveforms along with their frequency spectrum for VDTA based Class 0 FAF are shown in Figure 26.It may clearly be noted that the VDTA based Class 0 FAF allows only 1 MHz signal to pass, partially attenuates signal of frequency 500 KHz, and significantly attenuates signals of frequencies 100 KHz and 10 MHz.Similar responses for Class 1 and Class 2 FAF are also obtained.

)
4.3.VDTA Based Class 2 FAF.The VDTA based Class 2 FAF is shown in Figure14which employs three VDTAs, two grounded capacitors and one grounded resistor.The second VDTA block is used as amplifier with tunable gain .The gain  of VDTA based amplifier is given by (34).The proposed filter uses grounded resistor which can easily be implemented using the TA with transconductance equal to  3 based structure given in Figure9.To realize second order filter,  Bias7 is set to value of  Bias4 such that  7 is equal to  4 and  Bias6 is set to value such that  6 is equal to sum of  3 and  4 ; that is,  6 =  3 +  4 .Consider which can be adjusted by varying  Bias3 and  Bias2 , thereby making  0 tunable.
Class 0 CDTA Based FAF.In practice, the transfer functions (9) and (10) modify due to nonidealities which are classified as tracking errors and parasites.The tracking errors cause current transfer from  and  ports to  port to differ from unity value and are represented by   and   .There is deviation in transconductance transfer from  to + and  − ports which is modeled by   .The parasites denoted by resistances   and   are at  and  terminals; shunt output impedances (//) are present at terminals ,   ,  + and  − , and  +  and  −  .The effect of the parasites is highly dependent on the topology.A close inspection of the circuit of Figure

Table 1 :
Aspect ratios of MOS transistors used in CDTA.The grounded resistor of Figure7is realized using TA block.The bias current is set as 0.85 A to realize a resistor of value 10 kΩ.The frequency responses of CDTA based Class 0, Class 1, and Class 2 FAF topologies are depicted in Figures15, 16, and 17, respectively.The responses are obtained by varying bias currents  Bias1 and  Bias2 ( Bias =  Bias1 =  Bias2 ) to 1 A, 10 A, 30 A, and 60 A while keeping  Bias3 and  Bias4 , respectively, at 0.5 A and 10 A.It can be clearly noticed that center frequency  0 increases on increasing the bias current.The electronic tunability of quality factor and center frequency for proposed Class 0, Class 1, and Class 2 CDTA based FAF is plotted in Figures18 and 19

Table 2 :
Aspect ratios of MOS transistors used in VDTA.Bias4 is set to obtain  4 / 3 = 3 while keeping  Bias5 equal to  Bias1 .In realization of Class 2 FAF,  Bias6 is selected such that  6 =  3 +  4 while  Bias7 is equal to  Bias4 .The electronic tunability of quality factor and center frequency for proposed Class 0, Class 1, and Class 2 VDTA based FAF is plotted in Figures24 and 25, respectively.The analytical and simulated responses describing variation of quality factor are shown in Figure24for different values of  Bias2 while setting  Bias1 and  Bias3 to 30 A in Class 0. To plot responses for Class 1,  Bias4 is set to get  4 / 3 = 3 and  Bias5 is set equal to  Bias1 .Class 2 FAF responses are plotted by selecting  Bias6 to obtain  6 =  3 +  4 while  Bias7 is equal to  Bias4 .

Table 3 :
Performance characteristics of CDTA and VDTA based Class 0, Class 1, and Class 2 FAF.