On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

We propose an approach to design of an algebraic signature analyzer that can be used formixed-signal systems testing.The analyzer does not contain carry propagating circuitry, which improves its performance as well as fault tolerance. The common design technique of a signature analyzer for mixed-signal systems is based on the rules of an arithmetic finite field. The application of this technique to the systems with an arbitrary radix is a challenging task and the devices designed possess high hardware complexity. The proposed technique is simple and applicable to systems of any size and radix. The hardware complexity is low. The technique can also be used in arithmetic/algebraic coding and cryptography.


Introduction
Signature analysis has been widely used for digital and mixedsignal systems testing [1][2][3][4][5][6][7][8][9][10][11][12].Mixed-signal systems consist of both digital and analog circuits; however the signature analysis method is only applicable to the subset of these systems that have digital outputs (such as analog-to-digital converters, measurement instruments, etc.).Signature analysis can be employed as an external test solution or can be embedded into the system under test.In the built-in implementation, a circuit under test (CUT) of digital or mixed-signal nature is fed by test stimuli, while the output responses are compacted by a signature analyzer (SA), as illustrated in Figure 1.The actual signature is compared against the fault-free circuit's signature and a pass/fail decision is made.A signature of a fault-free circuit is referred to as a reference signature.If the CUT is of a digital nature, the SA essentially constitutes a circuit that computes an algebraic remainder.The reference signature has only one, punctual value, and the decision making circuit consists of a simple digital comparator.If the CUT is of a mixed-signal nature, the SA computes an arithmetic residue.In this case, the reference signature becomes an interval value and the decision making circuit uses a window comparator.
Design methods for an algebraic signature analyzer have been well developed in error-control coding [13].A remainder calculating circuit for an arbitrary base (binary or nonbinary) can be readily designed for a digital CUT of any size.In contrast, it is much harder to design a residue calculating circuit, specifically for a nonbinary base [14].Furthermore, due to the presence of carry propagating circuitry, the implementation complexity and error vulnerability of the residue calculating circuit are higher compared to the remainder calculating circuit.
We propose an approach to design of an algebraic signature analyzer that can be used for mixed-signal systems testing.Due to an algebraic nature, the analyzer does not contain carry propagating circuitry.This helps to improve its error immunity, as well as performance.

A Conventional Signature Analyzer
An algebraic signature analyzer is designed on the basis of a polynomial division circuit, as shown in Figure 2 [3,13,15].This circuit divides the incoming sequence of nonbinary symbols (digits),  −1 , . . .,  1 ,  0 , treated as a polynomial: by the polynomial The remainder constitutes a CUT signature.Each digit,   , 0 ≤  ≤  − 1, consists  bits and is considered to be an element of the field (2  ).The degree of the polynomial (2), or the number of stages, , in Figure 2, depends on the desired probability of undetected error in the sequence of incoming digits.For long sequences with independent errors, this probability is estimated as   ≈ 2 − .In practice,  ≥ 8 and even for the one-stage circuit,   ≤ 2 −(1×8) = 0.0039, which is quite low.Therefore, a multiple-input signature analyzer normally contains only one stage.Such an analyzer is presented in Figure 3 [14], where  is a primitive element of the field (2  ), that is, a root of a primitive polynomial () =  −1  −1 + ⋅ ⋅ ⋅ +  1  +  0 .Each element of the field can be represented by a power of .Let   be the incoming digit and   the content of the analyzer.Then, each operational cycle of the analyzer is described by the expression Without a loss of generality, we will consider a 3-bit signature register ( = 3), with  being a primitive element of ( 23 ), in particular a root of a primitive polynomial () =  3 +  + 1.Then, a symbolic scheme of Figure 3 will transfer to the logic level circuit of Figure 4, where (5) This expression indicates the relationship between the power and vector representations of a field element, as reflected in Table 1 (where  = ).
If the preliminary "cleared" analyzer receives, for example, the following sequence of 3-bit output responses from + ×  k  j  i  Figure 3: A symbolic presentation of a one-stage algebraic signature analyzer.
The power representation of the field element, , corresponds to the vector representation, 010, which is the actual signature of the CUT.
In contrast to a digital CUT, the output responses of a mixed-signal CUT are distorted even in a fault-free case.Small permissible variations in the responses cause a significant deviation of the final signature.For example, if in the above sequence of output responses the least significant bit in the first response changes from 1 to 0 (i.e., the vector 111 changes to 110, or power  5 changes to  4 ), then the actual signature will change from 010 to 101 (or from  to  6 in power form).
Apparently, the conventional SA represented in Figures 3  and 4 cannot be employed for mixed-signal circuits testing.
In the known methods, output responses of mixedsignal circuits are compacted by a circuit referred to as a modulo adder (or accumulator, or digital integrator) [4][5][6][7][8].It should be noted that a modulo adder is a special case of a residue computing circuit [14].A residue computing circuit is represented in Figure 5.Here   is the current content of the register,   is the incoming (arithmetic) symbol, and  is the base of the system.This circuit divides the incoming sequence of symbols,  −1 , . . .,  1 ,  0 , treated as a number: by the modulus As in the case with the algebraic SA, we consider a singlestage device; that is,  = 1,  =  0 <  = 2  , where  is the number of bits occupied by the symbol.The residue,  0 , constitutes a signature.
An operational cycle of the circuit in Figure 5 can be described by the expression Although the circuits of Figures 3 and 5 look similar, their implementation is quite different.In general case, the designing procedure for the arithmetic circuits is more complicated and their hardware complexity is greater.
As an example, Figure 6 represents the circuit that computes a modulo 5 residue of the incoming sequence of 3-bit symbols treated as an octal number [14].Here   is the incoming octal digit and  is a combinational circuit which generates the following next state signals: Each shift of this circuit implements the operation   ×8+   (mod 5).
In addition to high hardware complexity, the arithmetic compactor contains carry propagating circuitry (shown in red color in Figure 6) that delays the operation and aggravates the effect of a single fault.
Below, we design an algebraic circuit that can be employed for mixed-signal data compaction.It does not contain carry propagating circuitry.

A Novel Approach
Polynomial (1) in conjunction with the reference signature can be considered as a code word of the code whose minimal distance is defined by the ().The distance here is the Hamming distance.This distance characterizes algebraic errordetecting properties of the code and is not convenient for arithmetic errors that occur in mixed-signal systems.Indeed, a small permissible deviation of the data to be compacted causes the reference signature to span the entire space.Under these conditions, the decision making circuit in Figure 1 must be able to compare the actual signature with the entire set of possible reference signatures.This increases the analyzer complexity.
To decrease the complexity, an arithmetic SA treats the sequence of output responses from a mixed-signal circuit as a number (7).In conjunction with the reference residue, this is considered as a code word of an arithmetic errorcontrol code.The properties of this code depend on the arithmetic minimal distance which in turn depends on the modulus .The arithmetic residue calculating analyzer does not search the entire space, since the space of arithmetic reference signatures is now contiguous.To make a decision, it employs a window comparator.This simplifies the circuitry.However, the hardware complexity of the arithmetic SA can still be quite high, as it was illustrated above.
In the rest of this paper, we will show how to design an algebraic SA, which generates a contiguous space of algebraic reference signatures.
In order to be contiguous, the space of signatures must be ordered.A signature can be represented in the vector or power forms.We will use the power exponent as the criterion for ordering the signature set.The distance between two vectors (signatures) will be evaluated as the arithmetic difference between the corresponding exponents.For example,  j  j+i  i × Figure 7: A symbolic form of an algebraic SA for a mixed-signal CUT.
the distance between the signatures 010 and 101 will be 5, because the exponents of powers  6 and  differ by 5. We can interpret these exponents as output responses of a mixedsignal CUT, since they possess arithmetic properties.At the same time, the corresponding vectors (signatures) possess algebraic properties.Therefore, arithmetic data is mapped into algebraic data.Figure 7 represents the circuit which performs the mapping and computes an algebraic signature.
The circuit of Figure 7 can be obtained from the circuit of Figure 3 by the following transform: Since the finite field (2  ) is closed and errors are independent, this mapping will not change the probability of undetected error.
The logic level implementation of the circuit of Figure 7 is more complex compared to the circuit of Figure 3, but it is less complex than that of the circuit of Figure 5.
Prior to designing the circuit, we have to make a few observations.
The first observation is that Let us denote an output response from a mixed-signal CUT by .The second observation is that the response  can be considered as an exponent of the power, that is,   .Essentially, this means that the arithmetic values  are mapped into algebraic values   .
Based on these observations, we can design a signature analyzer in the way shown in Figure 8.Here  is a primitive element of a finite field (2  );  coincides with the bit-length of the output responses.The lower and upper inputs of the multiplexer in Figure 8 are connected together, since  2  −1 =  0 in (2  ).
Considering the case when the analyzer is fed by 3-bit data, its more detailed implementation will have the form of Figure 9.
Here the buses consist of 3 lines, as indicated by the appropriate number.The initial content of the SA before the shift is   , or  2  2 +  1  +  0 in the polynomial form (we have omitted the superscripts for the sake of simplicity).The notations   and  +  , where index  can be one of 0, 1, and 2, indicate the present and next states, respectively.A multiplier by  in (2 3 ) is realized bearing in mind that () =  3 +  + 1,  corresponds to , and This operation is shown by crosslines in Figure 9.The multiplexer inputs "0" and "7" are tied together, because  7 =  0 in the field ( 23 ).
In order to demonstrate how to use this analyzer, we will assume that it receives only two values from a CUT, in particular  and .Since the CUT is of a mixed-signal nature, there is an unavoidable (and thereby permitted) deviation of these values by ±1 (the greater tolerances can also be considered).The analyzer will map the received data into  ±1 and  ±1 , respectively.If we assume that the initial content of the SA is 001 (versus 000 for a conventional SA), then after the first shift the content becomes  0  ±1 =  ±1 .After the second shift, it changes to  ±1  ±1 =  +±2 .This expression is derived using the interval arithmetic rules.It states that for the fault-free CUT the actual result must match one of the values from the interval [ +−2 ,  ++2 ], that is, one of the following: To further simplify the SA operation, we will assume that instead of  0 (i.e., 001) the initial SA content is  −(+) .We will refer to this value as the seed value.Then, by the same reasoning, the SA content after two shifts will match one of the following powers: Due to the closure property of the field ( 23 ), this power set is equivalent to Consequently, the decision making circuit in Figure 3 will work as follows.If the actual signature does not match any value from set ( 16), the CUT is considered to be faulty.Since these values are ordered (and surround the power  0 ), the decision making circuit can employ a comparator, thereby reducing the hardware complexity of the SA.
As in any signature analyzer, some errors in the CUT output responses may escape detection.The aliasing rate can be estimated as described in [16] and will coincide with the aliasing rate of the conventional analyzer.
Example.Let us consider a 3-bit CUT, which is fed by two input stimuli.Under the fault-free operation, the CUT produces the output responses  = 101 ± 1 and  = 110 ± 1. Therefore, the seed value will be  −(+) =  −(5+6) =  −11 =  3 , or 011 in the vector form.If the CUT is fault-free, then after 2 shifts the SA content must match one of the elements in set (16).For example, if the actual responses are 101+1 = 110 (or  6 ) and 110 + 1 = 111 (or  7 ) (i.e., the variations are within the tolerance bounds), the signature will be  3  6  7 =  2 which belongs to set (16).And the decision making circuit will generate a pass signal.The validity of such a decision is determined by the aliasing rate.
Let us assume that a fault in the CUT has made the following changes in the output responses: 110 → 011 ( 6 →  3 ) and 111 → 100 ( 7 →  4 ).Then the actual signature will become  3  3  4 =  3 .This element does not belong to set (16), so the fault is detected.
There are two distinct ways of designing the decision making circuit depending on the optimization criteria (time or hardware overhead).
Hardware Overhead.If performance is paramount and time overhead is not desirable, the following approach can be employed.Let  be the number of output responses.All of the 2 + 1 -multiplier outputs (see Figure 8) that belong to set (16) are connected to the first inputs of the 2+1 comparators of a similar type.The second inputs of these comparators are shared and fed by the vector 0 ⋅ ⋅ ⋅ 01.If the CUT is fault-free, one of the comparators will produce a logic "1" signal.The logic OR of the comparator outputs will constitute a pass/fail signal.The above procedure is based on the fact that the faultfree CUT produces one of the signatures from set (16).If the actual signature is  0 , the comparator connected directly to the signature register produces a logic "1, " thus indicating that the CUT is fault-free.If the actual signature is  6 , then the product  6 , generated at the output of the first -multiplier, equals 1, which is detected by the next comparator.The same reasoning applies to the rest of the signatures from set (16).The logic diagram of the -bit comparator is shown in Figure 10.Time Overhead.If time overhead is allowed, the hardware complexity can be further reduced.In terms of implementation, it is more convenient to use the following seed value:  −(+++1) , where  is the number of output responses.For the above example,  −(11+3) =  0 , and set (16) will transform to After the last output response has been shifted in, the SA continues to shift its content 2 + 1 more times, while the input  is forced to 1.This ensures that the SA content is multiplied by  with each shift.For the above example, 2 + 1 = 5.If, within this time, the match with an element of set (17) has been determined, the CUT is considered to be fault-free.Otherwise, it is faulty.
If the CUT is fault-free and its output responses have not exceeded their tolerances, then while cycling through the states during the extra 2 + 1 shifts, the output of the multiplexer in Figure 8 will go through the power  0 or vector 0 ⋅ ⋅ ⋅ 01.The match with the vector 0 ⋅ ⋅ ⋅ 01 is detected by the comparator of Figure 10 connected to the multiplexor's output.The comparator output is actually producing a pass/fail signal.
The implementation complexity of the circuit of Figure 8 increases significantly with the growth of the data width, .Therefore, this circuit can only be implemented for the output responses with relatively low values of .For greater values of , we will modify the circuit of Figure 8 to the one shown in Figure 11.The modified circuit contains binary-weighted stages and is more economical in terms of hardware.The complexity of the multiplier ×  is comparable with that of the multiplier ×, whereas the number of multipliers drops from 2  to .The economy increases with the growth of .
For the case of 3-bit data, the circuit of Figure 11 transfers to the one shown in Figure 12.This circuit operates much in the same way.The   -multipliers structure is determined from the following expressions:  (18)

Experimental Results
The experimental setup to test the proposed method of signature analysis is shown in Figure 13.The setup includes the microcontroller system board Adapt9S12D (Technological Arts Inc.) based on Freescale's 9S12DG128 microcontroller and the Altera DE2 Development board based on the Cyclone II EP2C35F672C6 field-programmable gate-array (FPGA) device.We have selected 16 input test stimuli (voltages  in ) equally distributed over the range (0 ∼ 5.12) and applied them to the analog-to-digital converter (ADC) of the 9S12 microcontroller (which served as a mixed-signal system).Each input voltage,  in , was measured by a high-precision voltmeter and regarded as a nominal test input value.The circuit in Figure 13 operates as follows.Every time the switch S is closed, the system performs 8 measurements of the same test signal and averages the result by accumulating the sum of the eight 8-bit measurements and shifting it right three times, which eliminates noise.The ADC transfer characteristic is presented in Figure 14 [17].According to this characteristic, each conversion result for a properly operating device can deviate from the nominal value by ±1, which is an implication of the fact that the permissible differential nonlinearity can range from −0.5 to +0.5 LSB (see shadowed boxes in Figure 14).For example, if  in = 40 mV, the conversion result can be $01, $02, or $03 (in the worst case, the points  and  coincide).Therefore, each of the thirty-two 8-bit average results contains an error of at most ±1 count.The test stimuli have been selected equal to the midpoints of the quantization bins, thereby increasing the uncertainty and worsening the probability of undetected error.If the test stimuli would have been selected at the transition points of the characteristic, the probability of undetected error (aliasing rate) would improve.This follows from the observation that each conversion would result in 2 possible values as opposed to 3 possible values in the previous case.
As soon as average values of the conversion results are computed by the microcontroller, they are transferred to the DE2 board.The transfer of each datum is accompanied by a high-to-low transition of the strobe signal .The  signal serves as a clock for the state machine that implements the signature analyzer (in its 8-bit configuration).The signature, , is displayed on a two-digit 7-segment display in hexadecimal form.
The first experiment was performed on the properly operating device.In the second experiment, the average results were corrupted digitally in the microcontroller (thereby simulating random faults in the ADC) and sent to the analyzer.The analyzer has correctly identified the faulty device.
The relationship between input voltages and output codes is presented in Table 2. Based on this table and taking into consideration that () =  8 +  4 +  3 +  2 + 1, the seed value is calculated as follows:  In addition to test experiments, the operation of the analyzer (the DE2 part of the test setup) was simulated using Altera Quartus II software.Based on the two experiments represented in Table 2, the signatures that correspond to fault-free and faulty ADCs are, respectively, 233 and 201 (in decimal form).The process of calculation of these signatures is demonstrated in Figures 15 and 16.Figures 17 and 18 represent the fault detection process.The actual final signatures are shifted additionally 32 times.If the value 1 appears in the analyzer during these shifts, the system is fault-free.Otherwise it is faulty.
The simulation results matched the experimental results.

Conclusion
We examined an algebraic signature analysis method that can be employed for mixed-signal circuits testing.We demonstrated how to design the appropriate device.This device does    not produce arithmetic carries and is therefore less prone to errors.The absence of carry propagating circuitry also contributes to the higher performance of the device.The proposed scheme can also be used in arithmetic and algebraic error-control coding, as well as cryptography.

Figure 1 :
Figure 1: Built-in signature analysis of a circuit under test.

Figure 4 :
Figure 4: A logic level presentation of the algebraic 3-input signature analyzer.

Figure 5 :
Figure 5: A symbolic presentation of a one-stage arithmetic signature analyzer.

Figure 8 :
Figure 8: A more detailed symbolic form of the SA.

Figure 9 :
Figure 9: A register transfer level implementation of the SA.

Figure 11 :
Figure 11: A binary-weighted version of the SA.

Figure 12 :
Figure 12: A register transfer level implementation of the 3-bit SA.

Figure 15 :
Figure 15: All output code deviations are within the tolerance bounds.

Figure 16 :
Figure 16: Some of the output code deviations exceed the tolerance bounds.

Table 2 :
Relationship between input test stimuli and output responses.