Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.
Electromagnetic radiation effects can cause several types of errors on traditional SRAM-based registers and DRAM-based memory such as single event upset (SEU) and single event functional interrupt (SEFI). Especially in aerospace where radiation is quite intense, the stability and correctness of systems are strongly affected. It is therefore essential to make electronic components and systems resistant to damage or malfunctions caused by ionizing radiation. Previous studies have shown that nonvolatile memories such as Spin-Torque Random Access Memory (STT-RAM), Phase Change Memory (PCM), Domain Wall Memory (DWM), and Flash memories [
During compilation, the decision of which variables to be kept in registers at each point in the generated code is called
For MLC STT-RAM-based registers, the programming costs of variables with different state transitions vary significantly [ To the best of our knowledge, this is the first work which integrates the write state-transition cost of MLC STT-RAM into the spilling policy of register allocation. A cost model is proposed to quantify the spilling cost of variables in the potential spilling list. A SSCM algorithm is proposed to select the best spilling candidate with the goal of reducing the overall programming energy of MLC STT-RAM. Experiments are conducted to quantitatively evaluate the effectiveness of the proposed approach.
The rest of this paper is organized as follows. The background of STT-RAM and register allocation are introduced in Section
This section firstly describes the resistance state transition of MLC STT-RAM and its nature of antielectromagnetic radiation and then presents the traditional graph coloring algorithm for register allocation. Finally, previous spilling heuristic is discussed.
Among all the emerging NVMs, the spin-transfer torque RAM (STT-RAM) is considered as a promising candidate for on-chip memory because of its advantages, such as low leakage, high density, fast read speed, nonvolatility, and immunity to radiation-induced soft errors [
In a (SLC) STT-MRAM device, the spin of the electrons is changed using a spin-polarized current. This effect is achieved in a magnetic tunnel junction (MTJ). An MTJ device consists of a reference layer and a free layer. The magnetization direction (MD) of reference layer is unchanged while the MD of free layer can be flipped by applying a current through the MTJ. The MLC STT-RAM comprises 2-bit MLC cell which is adopted in this work. Two MTJs with different sizes are stacked vertically atop an NMOS transistor. The four resistance states are defined by the four combinations of different MDs of the two MTJs [
For comparison, Table
Parameters of SRAM, SLC STT-RAM, and MLC STT-RAM.
Parameters | SRAM | SLC STT-RAM | MLC STT-RAM |
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Read latency (cycles) | 7.43 | 9.08 | S:6.73, H:9.80 |
Read dyn. eng. (nJ) | 0.161 | 0.216 | S:0.22, H:0.43 |
Write latency (cycles) | 5.78 | 25.58 | S:25.31, H:56.50 |
Write dyn. eng. (nJ) | 0.156 | 0.839 | S:0.843, H:2.502 |
Leakage power (mW) | 295.58 | 18.39 | 7.02 |
Array area (mm2) | 7.28 | 1.86 | 1.01 |
In conventional random access memory (RAM) technologies, data are stored as electric charge or current flows. For STT-RAM, data are stored by magnetic storage elements
The resistance of an MTJ can be changed by injecting a switching current. In particular, MLC STT-RAM has two domains, a hard domain and a soft domain. The magnetic direction of the soft domain can be changed by a small current, while applying a larger current to MTJ affects both hard and soft domains. In this paper, the first bit of a 2-bit data indicates the magnetization direction of the hard domain and the second bit indicates the magnetization direction of the soft domain. States transitions of MTJ resistance can be presented in Table Zero transition (ZT): neither bit is changed. Soft transition (ST): only the magnetic orientation of the soft domain is switched. Hard transition (HT): the magnetic orientation of the hard domain is switched, and two domains have the same orientation. Two-step transition (TT): transition completes with two steps, including one HT followed by one ST.
Write transitions.
Zero transition (ZT) |
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Require no current |
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Soft transition (ST) |
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Require small current |
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Hard transition (HT) |
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Require large current |
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Two-step transition (TT) |
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Require sum of two-step current |
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Table
Switching currents of MLC STT-RAM cell (
To | ||||
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From |
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0 | −38.3 | — | −56.7 |
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26.3 | 0 | — | −56.7 |
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66.4 | — | 0 | −9.1 |
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66.4 | — | 39.3 | 0 |
It can be seen from Table
A graph coloring based register allocation approach was designed by Chaitin et al. [
A critical issue of register allocation is which node
In this section, a motivational example is presented to show how the unbalanced costs of different write state transitions impact the spilling decision for MLC STT-RAM-based registers.
The example in Figure
A 2-coloring example in conventional register allocation.
In this work, since we consider registers built by MLC STT-RAM where writes with different state-transitions cost different energy, the conventional approach is not appropriate any more. Table
A statistic study of two consecutive writes to registers of eight 2-bit MLLC STT-RAM cells.
Node |
Node |
Node |
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Old value | 0001000100010110 | 0001100010100001 | 0100000010000001 |
New value | 1010110100011110 | 0011100011000000 | 0000010011110001 |
Number of transactions | |||
ZT | 4 | 5 | 4 |
ST | 0 | 1 | 3 |
HT | 2 | 2 | 1 |
TT | 2 | 0 | 0 |
Statistics of transactions | |||
Soft transitions |
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1 | 3 |
Hard transitions |
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2 | 1 |
The observation indicates the impact of different state-transition costs on the potential spilling decision during register allocation.
This section first describes the framework overview of the proposed approach and then presents the spilling cost model driven by state transition of MLC STT-RAM. Finally, the algorithm for SSCM-based register allocation is presented.
Previous heuristics as described in Section
In this paper, we propose a cost-based method to choose spilling variables when MLC STT-RAM is employed as the register. In order to build a formal spilling cost model, we explore the unbalanced writes to the hard domain and soft domain of MLC STT-RAM cells and the exact state-transition cost to identify the spilling cost of each node. Then, spilling candidates are selected according to their spilling costs in the
In this subsection, a spilling cost model is presented to illustrate the spilling priority, determined based on state-transition profiling information of MLC STT-RAM.
We assume that the write frequency or the number of transitions of each state can be obtained through profiling. Considering a MLC STT-RAM with 2 bits per cell, the state
The number of the four state transitions can be collected by the following model:
Subsequently, the cost model of a variable can be constructed as the linear combination of
Here,
We calculate the write energy of every energy in MLC STT-RAM at
Once the parameters have been finalized, we can obtain the cost for each node in graph
Overall, the procedure of building spilling cost model is shown in Figure
The procedure of building spilling cost model.
The spilling cost model provides a sound basis for selecting potential spilling nodes. By keeping the node (variable) with less transition energy in register instead of memory, it helps avoid expensive spills when considering the state-transition costs of MLC STT-RAM.
This subsection describes the proposed SSCM-based register allocation algorithm. The basic idea is to choose the potential spilling candidate with the high spilling priority which is determined by the variable’s write transition cost. The goal is to spill the node with relatively expensive write cost to memory so as to relieve the register pressure and maximize energy saving during program execution. The SSCM-based register allocation mainly consists of four steps.
An interference graph
It is assumed that
The number of different write state transitions of the remaining nodes is counted through profiling. Then the cost of each variable can be obtained by (
If no color is available for the spilled variable, then stop. Otherwise, the allocator will insert the spill node, rebuild the interference graph, and start over.
The algorithm is shown in Algorithm
As discussed previously, the proposed optimistic coloring can lead to more energy-efficient register allocation by considering the nonuniform state transitions of MLC STT-RAM-based registers.
One typical concern with most profiling-based optimizations is input-dependence, that is, whether the optimizations made for a specific set of inputs will be preserved for other inputs of the same application. For the proposed SSCM scheme, it is clear that the spilling cost models are fixed given a specific programming strategy, while the write state-transition frequencies of each state vary across different applications and across different inputs. However, the optimality of SSCM depends not on the values of
In the experimental evaluation, this paper, same as the work in [
In this section, the experimental setup is introduced first. Then, the experimental results for evaluating the efficacy of proposed SSCM methods are presented.
We evaluate how the proposed SSCM impacts on dynamic energy and lifetime of MLC STT-RAM. The architectural parameters of the MLC STT-RAM registers are listed in Table
The configurations of MLC STT-RAM.
MLC STT-RAM | |
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Total read time (ns) | S:1.25 H:1.63 |
Total write time (ns) | S:7.18 H:14.86 |
Read energy | S:0.018 H:0.023 |
Write energy | S:0.087 H:0.14 |
Wearing/per write | Hard domain: 0, 0, 1, 1 for ZT, ST, HT and TT, respectively |
Soft domain: 0, 1, 1, 2 for ZT, ST, HT and TT, respectively |
Benchmarks are selected from DSP programs and Livermore benchmarks in the experiments. Using the LLVM [
Typically, a register file is accessed in a single cycle. The cycle length is sized for the worst case. Thus, all accesses take the same amount of time. In this section, the proposed SSCM-MLC STT-RAM scheme is evaluated against the MLC STT-RAM with traditional register allocation in terms of energy efficiency and lifetime.
The consumed energy is accumulated by each 2-bit state transition in the register. Each register is 64-bit long and the bits in the same register can be programmed simultaneously [
Energy evaluation under C-MLC and SSCM-MLC register design.
The best endurance test result for SLC STT-RAM devices so far is less than
Normalized total write times under C-MLC and SSCM-MLC register design.
This paper has proposed a state-transition-aware spilling cost minimization (SSCM) scheme for energy reduction in MLC STT-RAM-based register design. First an energy cost model is built to quantitatively calculate spilling cost of each variable with a degree larger than
The authors declare that there are no conflicts of interest regarding the publication of this paper.
This work is supported by the grants of Beijing Advanced Innovation Center for Imaging Technology, National Natural Science Foundation of China [Project no. 61502321], and the Project of Beijing Municipal Education Commission [Project no. KM201710028016].