Transformation of Holes Emission paths under Negative Bias Temperature Stress in deeply scaled pMOSFETs

In this paper, the impact of negative bias temperature (NBT) stress on the IG-RTN and ID-RTN were studied for deeply scaled pMOSFETs. It is observed that low NBT stress only results in ID-RTN while high NBT stress triggers additional IG-RTN. By the analysis of the field dependence of emission constant, it is found that under low NBT stress, the stress generated traps exchange holes with the channel while under high NBT stress, at least some of traps discharge holes to the gate side.


Introduction
Negative bias temperature instability (NBTI) degradation is one of the most important reliability issues in modern complementary metal-oxide-semiconductor (CMOS) technologies [1][2][3][4][5][6][7].Recently, much attention has been paid to NBTS generated oxide traps, which could significantly increase the failure probability in deeply scaled pMOSFETs.Furthermore, these traps are currently considered to not only cause the  th degradation but also increase the gate leakage current (  ) [8][9][10].However, someone considers the   fluctuations are probably not to be explained as the results of NBT induced switching traps [11][12][13].Tsujikawa reported that the observed transient   and   signal simultaneously in small size pMOS devices are not linked directly with each other [11].Wagner et al. [12] pointed out that the increases of   fluctuation are probably caused by the beginning of oxide breakdown which should not be explained as the results of NBT induced switching trap while Gao et al. [14] have reported that   increases only when part of the switching hole traps transform to the permanent bulk traps with increasing NBT stress or stressing time.To date, the impact of negative bias temperature stress condition on   and   fluctuation has not been systematically evaluated yet.
In this paper, we examine the impact of stress on the   -RTN and   -RTN for deeply scaled pMOSFETs, using carrier separation measurement to identify the type of   -RTN.The characteristic of time constants and amplitude in RTN under the various stress regions is investigated and a trap-assisted tunneling model through NBT stress-induced switching traps is proposed to explain the mechanism of   -RTN.The results illustrate that, under the relative high NBT stress, at least some of the holes are discharged from the traps to the gate side.

Experiment
Plasma nitric oxide (PNO) pMOSFETs used in this study were fabricated with a standard CMOS process technology.The devices size ( × ) is 30 nm × 70 nm and dielectric thickness is about 2.6 nm.And the   -  curve of this device is shown in the inset of Figure 1.The measurements were conducted using a Keithley 4200 semiconductor characterization  system and a Cascade Summit 12000 probe station with a built-in temperature controller.

Result and Discussion
Figure 1 shows the time traces of   and   monitored simultaneously under the relative low (  = −1.3V,  ox = 3.1 MV/cm) and high (  = −2.1 V,  ox = 6.2 MV/cm) NBT with  DS of 50 mV at room temperature stress for pMOSFETs.  -RTN is clearly detected in both cases, which should be contributed by the traps in the gate oxide layer.But there are two major differences between the two stress conditions.One is that the higher stress voltage triggers   -RTN, which has the strong reverse correlation with   -RTN; for example, the low drain current RTN level corresponds to the high gate current RTN level.The correlation suggests that   -RTN and   -RTN share the same traps induced by NBT stress, or a trapped hole results in the simultaneous increase in   and decrease in   under the relatively high NBT stress condition.By using the carrier separation measurement as shown in Figure 2, the drain and source electrodes were connected together and the gate electrode was biased under the stress condition [15][16][17].In that case, the   current could be divided into hole (source/drain) part and electron (substrate) part.The hole current, electron current, and and synchronize with that in the   trace.Therefore, holes are the major contributors to   -RTN.To conclude, the switching hole trap generated in high NBT stress could induce a larger amount of hole from channel to gate.Another major difference for the two stress conditions is the electrical behaviors of   -RTN.Figure 4 shows the field dependence of the average value of capture time (  ) and emission time (  ) for the   -RTN within the gate voltage of (−1.0 V∼ −1.3 V) and (−1.8 V∼ −2.1 V).The average values of   and   are obtained from the exponential distribution of the single   and   .As shown in Figure 4(a), for the low stress range,   and   are found to exponentially decrease and increase with   , respectively.As shown in Figure 4(b), for the high stress range,   keeps weakly dependent with the field even though   exhibits similar behaviours as these observed in the low stress.The strong field dependence of both   and   in   -RTN under low stress could be explained by the extended nonradiative multiphonon (eNMP) theory [18][19][20][21][22].In this theory, when the negative gate bias is applied for pMOSFETs, the switching trap states can be created from Si-Si precursors in the oxide state by capturing a hole via a multiphonon emission (MPE) process [18,20].The increase of the gate field results in a lower MPE barrier.The latter enhances the charge transfer reaction, leading to the dramatic reduction of hole capture time, which could be described as follows [23][24][25]: Here Δ  is the multiphonon emission (MPE) barrier for hole capture,  ox is the applied field in the oxide layer, and   is the characteristic field in MPFAT process.The red solid lines in Figure 4(a) present the fitting results with   being about 2.5 MV/cm which is analogous to that measured in NBTI [20,26].On the other hand, increasing the stress field will raise the hole traps' energy level and prevent the hole back to channel, which finally increases the emission time of RTN which is corresponding to the result in the low stress range.However the electrical behaviour of   in the high stress range is hard to be explained by this theory.One possible explanation is that the hole emission from trap is not to the Si substrate side but to the gate side by tunneling [27,28].In this case, increasing the stress field not only could prevent the hole back to channel but also will encourage it to be emitted to gate, which finally results in a weakly field dependence.Therefore, these switching traps behave as hole current path from channel to gate at high gate bias, which is consistent with the reverse correlation of   and   -RTN.
For verifying the current path induced by switching traps under high gate bias, the field and temperature dependence of the   -RTN is measured.As shown in the inset of Figure 5, the extremely weak temperature dependence was observed in Δ  , which is the typical behavior of elastic tunneling.In one-step elastic TAT model, channel charges could tunnel to gate side with the assistance of a trap in oxide.And the TAT probability in the model is described as [27,29] ]) . ( Here Φ  is the energy depth of the trap from the valence band of dielectric,  ox is the hole effective mass in dielectric,  ox is electric field in oxide, and  is the trap's distance from the interface of gate and oxide.When  = 1.5 nm and Φ  = 4 V, it is observed that it provides a good description of the experimental data in Figure 5, which verifies that these switching traps could perform as hole tunneling paths.Finally, the step-like fluctuations detected in Figure 1(b) are investigated.To avoid the mixture of several fluctuations, we selected the device which has only one active trap under the measurement condition.The gate voltage dependence of Id fluctuation of this trap is measured.Under the high bias of −1.7 V, the emission of the carriers from the trap is not detected until the end of measurement time of 300 s.Therefore the step-like behavior at −1.7 V is presented.When the gate bias is reduced from −1.7 V to −1.5 V, the emission of carriers from the trap occurs at about 210 s and the emission time (  ) is about 170 s.Further decreasing the gate bias reduces the emission time to about 70 s at   = −1.4V and about 10 s at   = −1.2V (Figure 6).The voltage dependence of the emission time observed here is consistent with the field behaviors of   -RTN in Figure 4(a).The results clearly inform that   -RTN transforms to   -step when the gate bias is increased.In other words, both   -step and   -RTN are originated from the switching traps.
According to the above analyses,   -RTN,   -RTN, and   -step observed in NBTI degradation are due to the generated NBT traps.Under the relatively low NBT stress, the

Conclusions
In this paper, the fluctuations including   -RTN,   -RTN, and   -step are studied under various NBT stress.Note that, under the relative low NBT stress, only   -RTN could be detected while under the relative high NBT stress the   -RTN,   -RTN, and   -step are observed.Through the analysis of the field dependence of emission constant and the carrier separation measurement, it is found that under the relative high NBT stress some traps keep charged state for very long time, as observing step-like behaviors in   , while other traps emit charged holes to the gate side through TAT process, which originate both   -step and   -RTN.

Figure 1 :
Figure 1: The time trace of   and   fluctuation under the gate voltage   of −1.3 V and −1.9 V with  DS of 50 mV.The inset shows the   -  curve of the experimental device.

Figure 2 :Figure 3 :
Figure 2: Configuration of the circuit diagram in carrier separation measurements.The gate electrode is biased for the stress condition, and drain and source electrodes are connected together.

Figure 4 :Figure 5 :
Figure 4: Field dependence of the average value of   and   of the RTN under (a) higher and (b) lower gate bias regions.The red lines present MPFAT simulation results for   .

Figure 6 :
Figure6: The transformation of transience signal from   -Step to   -RTN could be seen by decreasing the gate bias from −1.7 V to −1.5 V.And the emission time of this trap is obviously decreased from larger than 300 s to about 10 s when gate bias is decreased from −1.7 V to −1.2 V.

Figure 7 :
Figure 7: Schematic view of the switching traps in pMOSFETs.Under low gate bias, the switching traps in oxide layer could only be recovered by exchanging hole with channel and induce only   -RTN.Under the high gate bias, part of generated switching traps can capture and hold the hole while some others transform the hole from the channel to gate by TAT mechanism.