Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications

Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y 2 O 3 /Ta 2 O 5 /SiO 2 /Si (MYTOS).TheMYTOS field effect transistors were fabricated using Ta 2 O 5 as the charge storage layer and Y 2 O 3 as the blocking layer.The electrical characteristics of memory window, program/erase characteristics, and data retention were examined.The memory window is about 1.6 V. Using a pulse voltage of 6V, a threshold voltage shift of ∼1 V can be achieved within 10 ns. The MYTOS transistors can retain a memory window of 0.81 V for 10 years.


Introduction
One of the most attractive candidates for nonvolatile memory applications is the charge-trapping device in which multilayered dielectrics are used.The semiconductor-oxidenitride-oxide-semiconductor (SONOS) memory is typical of the charge-trapping devices.The advantages of SONOStype charge-trapping devices include smaller cell size, lower programming voltage, and better cycling endurance compared with the floating-gate devices.By reducing the tunneling oxide thickness in the SONOS-type devices, faster programming speed and lower operating voltage can be accomplished [1][2][3][4].However, the issues of poor retention time and low erase speed still remain in the SONOStype memory devices.To improve the retention time of SONOS devices, several researches have been reported.Hsu et al. indicated that HfO 2 can replace Si 3 N 4 and obtain a higher conduction band offset for better retention [5].Reports showed that the retention of memory devices can be improved using a chemical-vapor-deposited blocking oxide [6] or implementing a high-temperature deuterium annealing [7].Additionally, using a high-k dielectric as the blocking oxide, the program/erase speed and retention characteristic can be improved [8,9].In the study using Si 3 N 4 , HfO 2 , and HfAlO as the charge storage layer, Tan et al. showed that larger band offset can improve the program speed and reduce the overerase phenomenon [10].Furthermore, using the structures of TaN/HfO 2 /T 2 O 5 /HfO 2 /Si (MHTHS) and TaN/Al 2 O 3 /Ta 2 O 5 /HfO 2 /Si (MATHS) both program speed and retention time can be improved as compared to the traditional SONOS devices [11,12].
In this work, charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications.The structure is metal-yttrium oxidetantalum oxide-silicon oxide-silicon (MYTOS), that is, Al/Y 2 O 3 /Ta 2 O 5 /SiO 2 /Si.The MYTOS devices were fabricated using Ta 2 O 5 as the charge storage layer and Y 2 O 3 as the blocking oxide for both high energy barrier at Al/Y 2 O 3 interface and large dielectric constant.The expected advantages of MYTOS device include longer retention time and faster program/erase speed.Figure 1 shows the energy band diagrams of the MYTOS memory device.The conduction band offset between the tunneling oxide and the high-k charge storage layer is 2.25 eV at the Ta 2 O 5 /SiO 2 interface.The large conduction band offset is expected to improve the data retention property because the tunneling electrons Advances in Materials Science and Engineering  V GS (V) Postmetallization annealing (PMA) was performed at 400 ∘ C in N 2 for 30 seconds.The crystalline phase of the high-k dielectric films was identified by X-ray diffraction (Shimadzu XD-5) using Cu K  radiation.Separate MHHOS capacitors were also fabricated.The - characteristics were measured using Keithley 236 electrometer and the - characteristics using high-frequency - meter MegaBytek Mi-494.

Results and Discussion
Figure 2 shows the  ds - gs memory window measurement for MYTOS transistors.The  ds - gs memory window after a 8 V, 0.01 s program pulse is 1.6 V.The memory window can also be estimated by the capacitance-voltage (-) hysteresis curves for the MYTOS capacitors.Using a sweep voltage range of ±10 V, the - memory window of 1.6 V can be achieved due to the electron trapping (not shown here).Figure 3 shows the programming characteristics of the MYTOS transistors.Pulse voltages of 6 V or 8 V are first applied to the gate.Thus, the electrons can tunnel from Sisubstrate into Ta   DS = 0.1 V.The transistor is defined as "programmed" when the  th shift is larger than 0.5 V.For MYTOS transistors, the  th shift of more than 0.5 V will occur at an applied voltage of 6 V and with a pulse width 10 ns.For MHTHS [11] and MATHS [12], the  th shift of more than 0.5 V will occur at an applied voltage of 10 V and with pulse widths of 1 ms and 100 ns, respectively.Therefore, low program voltage and fast programming speed were achieved with the MYTOS transistors in this work.The MYTOS transistors thus have faster programming speed and lower program voltage than MHTHS and MATHS memory devices.This is most likely due to the larger conduction band offset of 2.25 eV at the Ta 2 O 5 /SiO 2 interface compared with 1.2 eV at the Ta 2 O 5 /HfO 2 interface.At the same gate bias where Fowler-Nordheim tunneling is dominating, the electron tunneling distance from Si-substrate to the conduction band of the storage dielectric is therefore shorter for structures with Ta 2 O 5 /SiO 2 .The large conduction band offset is expected to give better blocking efficiency which will improve memory window and programming speed.In addition, large conduction band offset can also relieve overerase problem.The program voltage of MYTOS transistor can be as low as 6 V, which is lower than that of 10 V for MHTHS [11] and MATHS [12].The programming time of 10 ns is also faster than that of 1 ms and 100 ns of MHTHS and MATHS, respectively.As for the erase event, the negative pulse voltage is applied to the Al gate.Hence, the holes can tunnel from Si-substrate into Ta 2 O 5 and recombine the electrons stored into the Ta 2 O 5 layer.Figure 4 shows the erase characteristics of the MYTOS transistors.The transistor is defined as "erased" when the  th reduces more than 0.5 V. Obviously, an applied gate voltage of −6 V is not enough to do the erase process.Meanwhile, the  th reduced more than 0.5 V at an applied voltage of −8 V with a pulse width of 0.1 s.

Conclusion
In

2 O 5
Figure2shows the  ds - gs memory window measurement for MYTOS transistors.The  ds - gs memory window after a 8 V, 0.01 s program pulse is 1.6 V.The memory window can also be estimated by the capacitance-voltage (-) hysteresis curves for the MYTOS capacitors.Using a sweep voltage range of ±10 V, the - memory window of 1.6 V can be achieved due to the electron trapping (not shown here).Figure3shows the programming characteristics of the MYTOS transistors.Pulse voltages of 6 V or 8 V are first applied to the gate.Thus, the electrons can tunnel from Sisubstrate into Ta 2 O 5 and be stored into the Ta 2 O 5 charge storage layer which forms a potential well between Si-substrate and Y 2 O 3 , as shown in Figure1.In the program event, Y 2 O 3 is the blocking layer which can prevent the tunneling electrons from passing across the Y 2 O 3 layer since the Y 2 O 3 /Ta 2 O 5 interface barrier is high enough.Accordingly, the tunneling electrons can be reserved into the Ta 2 O 5 charge storage layer.The pulse widths are from 10 −8 s to 10 −2 s.After applying the gate pulse, the threshold voltage of the transistor was monitored by measuring the  DS - GS characteristics. th is defined as the gate voltage at 1 A drain current with
cm resistivity were used as the starting substrates.A 3 nm tunneling oxide (SiO 2 ) was thermally grown by dry oxidation at 900 ∘ C. The charge storage layer (Ta 2 O 5 ) was deposited by RF magnetron sputtering under a pressure of 1.1 × 10 −3 torr at room temperature in argon gas.The purity of Ta 2 O 5 target is 99.9%.The thickness of the Ta 2 O 5 layer is 20 nm.The Ta 2 O 5 films were either as-deposited or annealed at 400 ∘ C, 500 ∘ C, and 600 ∘ C. The annealing was performed in nitrogen at a flow rate of 3 standard cubic centimeters per minute (sccm).After annealing, the blocking layer Y 3 N 4 .The deeper trap level is expected to further improve data retention characteristic.Aside from the retention property, the SONOS-type devices with highk blocking dielectrics can increase the electric field for the tunneling oxide at the same operating voltage used.Hence, the program/erase speed can be improved using a high-k blocking layer.In this work, Y 2 O 3 is chosen to be the blocking oxide in which the charge injection efficiency in the tunneling oxide can be increased; meanwhile, the blocking function can be maintained.The dielectric constant of Y 2 O 3 blocking oxide is about 15 and the conduction band offset at the Ta 2 O 5 /Y 2 O 3 interface is about 1.35 eV.This large conduction band offset is expected to give better blocking efficiency which may improve the memory window characteristic.Besides, this high-k blocking layer is expected to increase the program/erase speed as well as to reduce the program/erase voltage.2.ExperimentP-type, (100) orientation, and 4-inch diameter silicon wafers with 1-10 Ω 2 O 3 was deposited by RF magnetron sputtering under a pressure of 1.1 × 10 −3 torr at room temperature in argon gas.The thickness of the Y 2 O 3 blocking layer is 10 nm.For transistor processing, a 500 nm oxide was first grown by wet oxidation and used as the field oxide.The source and drain windows were defined by wet etching and doped by nm)/Ta 2 O 5 (20 nm)/SiO 2 (3 nm)/p-Si Figure 2:  ds - gs memory window characteristic.arsenic implantation (5×10 15 cm −2 , 40 keV).The implant was annealed at 950 ∘ C in N 2 for 30 minutes.The contact region in Ta 2 O 5 was etched by reactive ion etch (RIE) and in SiO 2 and Y 2 O 3 by buffered oxide etch (BOE).The 300 nm thick top aluminum electrodes were evaporated by DC sputtering.
nm)/Ta 2 O 5 (20 nm)/SiO 2 (3 nm)/p-Si Figure 4: Erase characteristics of the Al/Y 2 O 3 /Ta 2 O 5 /SiO 2 /Si transistors.Figure 5: Retention characteristic of the Al/Y 2 O 3 /Ta 2 O 5 /SiO 2 /Si transistors.theoriginal threshold voltage.Pulse voltages of ±8 V at 1 ms duration were then applied for program and erase operations.The threshold voltage shift is measured at different time periods.The MYTOS transistors are projected to have a Δ th window of 0.81 V after 10 years.Table 1 lists the comprised memory parameters of the charge-trapping devices in which the adopted trapping layers include Ta 2 O 5 , Y 2 O 3 , HfO 2 , ZrO 2 , La 2 O 3 , and Dy 2 O 3 summary, Al/Y 2 O 3 /Ta 2 O 5 /SiO 2 /Si field effect transistors were fabricated and investigated.The electrical properties, memory window, program/erase characteristics, and data retention time, were measured.The  ds - gs memory window after ±8 V, 0.01 s programming pulse is 1.6 V.The  th shift of the MYTOS transistors at an applied gate voltage of 6 V with a pulse width of 10 ns is about 1.0 V.As for retention properties, the MYTOS transistors are projected to have a Δ th window of 0.81 V after 10 years.The excellent performance of the MYTOS transistors is most likely due to the larger conduction band offset at the Ta 2 O 5 /SiO 2 and the Y 2 O 3 /Ta 2 O 5 interfaces and the large dielectric constant of Y 2 O 3 .
CL: charge loss.including