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A generic charge-based compact model for undoped (lightly doped) quadruple-gate (QG) and cylindrical-gate MOSFETs using Verilog-A is developed. This model is based on the exact solution of Poisson’s equation with scale length. The fundamental DC and charging currents of QG MOSFETs are physically and analytically calculated. In addition, as the Verilog-A modeling is portable for different circuit simulators, the modeling scheme provides a useful tool for circuit designers.

According to Moore’s law, CMOS transistors continue to scale. The transistor size scaling provides for increased packing density, improves circuit speed, and lowers power consumption. However, many small-geometry effects have surfaced such as short-channel effects, limiting the device performance. In order to overcome these issues, improving device gate controllability is necessary. Multigate transistor architecture is regarded as one of the most effective ways to improve the short-channel effects and to enhance the gate controllability [

We propose a scale-length based GAA MOSFET model. The schematic diagram of the QG MOSFET for modeling is shown in Figure

The schematic diagram of the QG MOSFET.

Unlike most models limited to a certain specific type of the gate, the proposed model is highly scalable and is generic to both quadruple-gate (QG) and cylindrical-gate structures. Poisson’s equation for potential can be written as [

The calibration flow for model parameters.

Simulated drain current as a function of gate voltage at low and high drain biases.

The terminal charges are based on previous potential equation. The boundary conditions used for (

Channel charge density (per unit area) at the source end (

We then use

Figure

Charging current network diagram.

Total gate capacitance as a function of gate voltage extracted from AC simulation.

To ensure the validity of the model for IC simulation, different types of circuit simulation including inverters and static random access memory (SRAM) are used for verification [

DC simulated inverter transfer curve.

Transient simulated inverter response.

Figure

Conventional 6T SRAM.

Read and hold SNMs [

Figure

Predicted SRAM hold and read SNM curves.

A generic and charge-based compact modeling approach applicable to both quadruple-gate and cylindrical-gate structures was proposed. The model can be used straightforwardly with physical parameters such as gate work function and structural parameters. The model is analytical and efficient enough for circuit applications.

The authors declare that there is no conflict of interests regarding the publication of this paper.

The authors are grateful to the National Chip Implementation Center and National Center for High-Performance Computing for computational facilities. This work is supported in part by the Ministry of Science and Technology of Taiwan.