A Three-Phase Interleaved Floating Output Boost Converter

High step-up dc-dc converter is an essential part in several renewable energy systems. In this paper, a new topology of step-up dc-dc converter based on interleaved structure is proposed.The proposed converter uses three energy storing capacitors to achieve a high voltage gain. Besides the high voltage gain feature, the proposed converter also reduces the voltage stress across the semiconductor switches.This helps in using low rating switching devices which can reduce the overall size and cost of the converter.The operating principle of the proposed converter is discussed in detail and its principle waveforms are analyzed. An experiment is carried out on a 20V input, 130V output, and 21W power prototype of the proposed converter in the laboratory to verify the performance of the proposed converter. An efficiency of 91.3% is achieved at the rated load.


Introduction
Several applications require high step-up dc-dc voltage conversion.One of the most common applications is the photovoltaic energy sources where the low input voltage should be stepped-up to high dc-link voltage.Other applications include fuel cell, hybrid electric vehicle (HEV), high-intensity discharge lamp ballasts, and uninterruptible power supplies.A high step-up dc-dc converter is essential for such kind of applications.For such type of high step-up dc-dc voltage conversion, a traditional boost converter shown in Figure 1 will operate at very high duty cycle (above 80%) as the voltage gain of a simple boost converter is 1/1 − .Such high duty cycle will cause severe reverse recovery problem of the output diode.Also the switches in the simple boost converter will experience a high voltage stress as their voltage stress is equal to the output voltage.Moreover, it needs large filter elements to minimize the ripples as it has only one inductor with no ripple cancellation.For this purpose, various high step-up topologies have been reported in the literature [1][2][3].
Two-stage/quadratic boost converter comprising two boost converters can be used to achieve high voltage gain as the voltage gain is equal to the product of the gains of two boost converters, that is, 1/(1−) 2 .However, using two boost converters may degrade the overall efficiency as the overall efficiency is also equal to the product of the efficiencies of two boost converters [4][5][6].Inductorless switched capacitor circuits can give high step-up voltage conversion ratio, but they use a large number of switches and gate drives.The efficiency of switched capacitor circuit also is poor [7,8].Interleaved or parallel structure is well known for reducing the ripples due to its well-known feature of ripple cancellation among the phases.Moreover, it can handle more power, but it does not help in increasing the step-up voltage gain or reducing the voltage stress on switches [9].
Tapping among the inductors and coupling of various inductors can achieve high step-up voltage conversion ratio by adjusting the turn ratio.However, it is very difficult to perfectly couple inductors and the existence of leakage inductance can create problems of large voltage overshoots [10][11][12][13][14]. Boost converter employing voltage multiplier and three-state switching cells can achieve high voltage gain and also reduces ripple in input current.But the voltage gain of one multiplier cell is not much high and for a very high stepup voltage conversion more numbers of multipliers cells will be needed [15,16].Isolated converters such as half-bridge, full-bridge, and flyback can achieve high step-up voltage conversion by adjusting the turn ratio of the transformer.But they have their own problems related to transformers and are more expensive as compared to nonisolated types [17].
To achieve high voltage gain and lower switch stress, a new topology of dc-dc converter is presented in this paper.The circuit diagram is shown in Figure 2. The proposed converter is a three-phase interleaved boost converter with an intermediate capacitor and two output capacitors which forms the floating output.The proposed converter can achieve a very high voltage gain as well as reduce the voltage stress of switches.

Operating Principle of the Proposed Converter
Figure 2 shows the circuit diagram of the proposed converter.It consists of three phases with  1 being the filtering inductor of phase #1,  2 being the inductor of phase #2, and  3 being the filtering inductor of phase #3.Transistors  1 ,  2 , and  3 are the main switches of phase #1, phase #2, and phase #3, respectively.Similarly,  1 ,  2 , and  3 are the rectifying diodes of three phases.  is the supply voltage,   is the output voltage, and   is load resistor.For the analysis of the proposed converter the following assumptions are made: (i)  1 =  2 =  3 =  (where  is the inductance/phase), (ii)  1 =  2 =  (where  is the filter capacitor), (iii) all capacitors and inductors are very large, so that their ripples are very small, (iv) the converter always operates in continuous conduction mode (CCM).
The operation of the converter is done at a fixed switching frequency   and it has a fixed switching period of   .The operation is such that switches  1 ,  2 , and  3 are turned on and off by two PWM signals which is 180-degree phase shifted.One PWM signal is applied to the gate of  2 and another PWM signal which is 180-degree phase shifted from the first one is applied to the gates of  1 and  3 .There is no phase shift between phase #1 and phase #3 and both these phases are at 180-degree phase shift with phase #2.The converter is analyzed for a duty cycle  greater than 50%.There are total four switching states in one switching period.Figure 3 shows the circuit diagram of the proposed converter formed in each state and Figure 4 shows steady state waveforms for the proposed converter.Capacitor  2 also discharges to load and its voltage falls with a slope of −  /(  ).This state ends at  =  4 .

Steady State Analysis of the Proposed Converter
To simplify the analysis of the proposed converter, the time of each state is expressed in terms of duty cycle  and switching period   as (1)

DC Conversion Ratio. For the voltage conversion ratio
of the proposed converter we will apply the principle of inductor volt second balance (VSB) on inductors  1 ,  2 , and  3 .By VSB of inductor  1 we get The solution of (2) gives By VSB of inductor  2 we get The solution of (4) gives From ( 3) and ( 5) we get By VSB of inductor  3 we get The solution of (7) gives The output capacitors  1 and  2 remain in series with the supply voltage   and therefore the output voltage   of the proposed converter is given by By ( 6), (8), and ( 7) we get And the voltage conversion ratio  is

Voltage Stress of Semiconductor Devices.
Switches  1 and  3 are off in state-II and remain on in the rest of switching period.Referring to Figure 3(b), the off-state voltage (voltage stress) of switches  1 and  2 can be obtained as Switch  2 is off only in state-IV.Referring to Figure 3(c) the voltage stress   3 of switch  3 is given by In similar way the maximum voltage drop (voltage stress) of the diodes  1 ,  2 , and  3 can be found out and is given by

Ripple Current and Ripple Voltage.
Referring to Figure 4, the peak to peak ripple Δ 1 in the current  1 , peak to peak Advances in Materials Science and Engineering ripple Δ 2 in current  2 , and peak to peak ripple Δ 3 in current  3 are expressed as Similarly, the peak to peak ripple Δ  in in voltage   in can be expressed as The peak to peak ripple Δ  1 in voltage   1 and Δ  2 in voltage   2 are given by The peak to peak ripple Δ  in the output voltage   is given by

Experimental Results
To verify the effectiveness of the proposed converter, the parameters listed in Table 1 are used to obtain the theoretical and experimental results of the proposed converter.Using ( 3), ( 6), (8), and ( 11) and using the parameters of Table 1, the following results are obtained: Similarly using the parameters of Table 1 in ( 12), (13), and (14) gives the voltage stress of semiconductor devices: To verify the results and performance of the proposed converter an experiment has been carried out in the laboratory on a 21-watt prototype of the proposed converter using the parameters listed in Table 1.A photograph of the hardware of proposed converter is shown in Figure 5.
Figure 6 shows the experimental waveforms of the proposed converter for a duty cycle of 60%.The gate signals   1 and   2 are shown in Figure 6(a).It can be seen that these two signals are at 180-degree phase shift with each other both have 60% duty cycle.Figure 6(b) shows the waveforms of input and output voltages of the proposed converter.As clear from Figure 6(b) the supply voltage   to the proposed converter is 20 volts and the output voltage   is 121.5 volts which is close to the ideal value of 130 volts.Thus the proposed converter is able to produce 130 volts output from 20 volts input at 60% duty cycle and easily achieves a step-up voltage conversion ratio of 6.5. Figure 6(c Traditional interleaved boost converters whether of two phases or three phases have step-up voltage conversion ratio of 1/(1 − ) and the voltage stress across their switches (transistors and diodes) is equal to the output voltage [18,19].Thus, for producing an output voltage of 130 volts from an input voltage of 20 volts, the traditional interleaved boost converter must operate at a duty cycle of 84.6% which is very high as compared to the proposed interleaved boost converter.Also for 130-volt output voltage, the voltage stress across the transistors and diodes of traditional interleaved boost converter will be 130 volts which is also very high as compared to the switch stresses of the proposed converter.
From experimental results, it is clear that the proposed converter has very good performance as compared to the traditional interleaved boost converter.It nearly produces 130-volt output voltage from an input voltage of 16 volts with a duty cycle of 60% whereas the conventional interleaved boost converter will produce the same output at a duty cycle of 84.6% which is very high and can result in severe reverse recovery problems.Thus the proposed converter has considerably higher step-up voltage conversion ratio as compared to traditional interleaved boost converter and it easily overcomes the extreme high duty cycle operation and reverse recovery problem of the output diodes which appear in traditional interleaved boost converter.The voltage stress on the semiconductor devices of the proposed converter is also reduced considerably.Except the voltage stress of diode  1 which is 100 volts, the voltage stress of all other switches in the proposed converter is 50 volts; thus low rating devices can be used which results in reducing the overall cost and size of the converter whereas the voltage stress of the switches of traditional interleaved boost converter is equal to the output voltage, that is, 130 volts.Thus the voltage stress across the switches of the proposed converter is 2.6 times lower than that across the switches of traditional interleaved boost converter.
Figure 7 shows a plot of experimentally measured efficiency of the proposed converter against the load.The load resistor is varied to change the power and efficiency is measured at different loads.An efficiency of 91.3% is achieved at the rated power of 21 watts and a maximum efficiency of 92.5% is achieved at 16-watt output power.At 38-watt output power, the efficiency is lowered to 87.7% due to increased conduction losses.

Conclusion
A new topology of interleaved boost converter is presented in this study.Besides the well-known feature of ripple reduction/cancellation of the interleaved converters, the proposed topology has several additional advantages over the traditional interleaved boost converter.The analysis shows that traditional interleaved boost converter will undergo high duty cycle operation and reverse recovery problem, whereas the proposed converter can achieve the same voltage gain at appropriate duty cycle.The voltage stress on switches of the proposed converter is 260% less than that of traditional interleaved boost converter.An efficiency of above 90% is achieved which is considered good.These features make the proposed converter a more suitable candidate for renewable energy generating system where high step-up dc-dc voltage conversion is required.

Figure 1 :
Figure 1: Circuit diagram of traditional boost converter.

Figure 2 :
Figure 2: Circuit diagram of the proposed converter.

Figure 3 :
Figure 3: Operating circuits of the proposed converter.(a) State-I and state-III, (b) state-II, and (c) state-IV.

Figure 4 :
Figure 4: Steady state waveforms of the proposed converter.

Figure 5 :
Figure 5: Photograph of prototype of the proposed converter.

Figure 7 :
Figure 7: Experimentally measured efficiency of the proposed converter.
proposed converter formed in this state.Inductors  1 ,  2 , and  3 get charged by the supply voltage   and the currents  1 ,  2 , and  3 through them increase with slopes of   /.Capacitor  in is disconnected from the supply as well as from the load; it neither charges nor discharges and its voltage   in is constant.Both the output capacitors  1 and  2 discharge to the load and their voltages   1 and   2 fall with slopes of −  /(  ).State-II ( 1 ≤  ≤  2 ).State-II begins when switches  1 and  3 are turned off at  =  1 .The switch  2 is still on.Diodes  1 and  3 start conducting, whereas diode  2 is still off.Figure3(b)shows the circuit topology formed in this state.Inductor  2 is still in charging mode and its current  2 rises with a slope of   /.Inductors  1 and  3 are in discharge modes and their currents  1 and  3 fall with slopes of (  −   in )/ and (  −   2 )/, respectively.Capacitor  1 is still in discharge mode and its voltage   1 is still decreasing with same slope of −  /(  ).Capacitors  in and  2 are charged up by the supply and their voltages   in and   2 rises with slopes of  1 / in and  3 / −   /(  ).This state ends at  =  2 .
≤  ≤  1 ).State-I starts at  =   when all the transistors  1 - 3 are turned on.During this state all the diodes  1 - 3 remain off.Figure3(a) shows the circuit topology of the State-III ( 2 ≤  ≤  3 ).This state is similar to state-I.Again all the transistors are on and all the diodes are off.The circuit diagram is the same as in state-I (Figure3(a)).State-IV ( 3 ≤  ≤  4 ).This state begins when switch  2 is turned off at  =  3 .Switches  1 and  3 are still off.Diode  2 starts conducting and diodes  1 and  3 remain off.Figure3(c) shows the circuit topology formed in this state.Inductors  1 and  3 are charged by the supply and their currents  1 and  3 rise with slopes of   /.Inductor  2 discharges and its current  2 decreases with a slope of (  +   in −   1 )/.Capacitor  in discharges to load and its voltage   in falls with a slope of − 2 / in .Capacitor  1 gets charged and its voltage   1 rises with a slope of  2 / −   /(  ).

Table 1 :
Paramaters used for experiment.
) shows the waveforms of the voltages across the capacitors  1 ,  2 , and  in .The voltage   1 across capacitor  1 is 93 volts and the voltage across each capacitor  2 and  in is 47 volts which are also close to ideal/theoretically calculated values.The waveforms of the voltage stresses   1 ,   2 , and   3 across the MOSFETs  1 ,  2 , and  3 are shown in Figure6(d).It can be seen that all the three voltages are equal to 50 volts.Thus the voltage stress across the MOSFETs is almost 2.6 times lower than the output voltage.Figure6(e) shows the waveforms of the voltage stress across the diodes  1 ,  2 , and  3 .As clear from Figure6(e), the voltage stress   1 across diode  1 is −98 volts, the voltage stress   2 across diode  2 is −46 volts, and the voltage stress   3 across diode  3 is −48 volts.Thus the voltage stress across the diodes is also reduced considerably.