Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Being one of the promising techniques for future computing systems, quantum-dot cellular automata (QCA)-based circuit design has gained massive interest among researchers due to which numerous QCA-based full adder (FA) circuits have been designed. Due to numerous QCA FA circuits available in the existing literature, researchers fnd it difcult to invest the time to search, implement, simulate, and analyze QCA FAs to fnd the best-suited design according to their needs. Existing review articles do not present a complete overview and performance comparison of QCA FAs. Also, the existing articles do not include quite a number of QCA FA designs in the literature review. As a result, a detailed review including all possible QCA FAs becomes essential. Terefore, rather than going for a new QCA FA design, this research aims to aid researchers by providing an extensive literature review and comprehensive study on existing QCA FAs. A total of 47 QCA FAs have been considered for analysis. Te QCA FA implementation method and performance parameters are summarized in a tabular manner to provide a quick overview and comparison of the QCA FAs.


Introduction
Due to short-channel efects, quantum efects [1], and power consumption, scaling down in the microscopic world is truly a challenging approach.Traditional CMOS and FinFET processes have their limits due to which they are unable to go deeper into the deep submicron level after a certain point is reached [2][3][4].Terefore, researchers are seeking alternative robust solutions.Among all the latest emerging technologies, the quantum-dot cellular automata (QCA) is representing itself as the future of nanotechnology by surpassing and removing the barriers associated with the conventional transistor fabrication process [5][6][7].
QCA is a nanoscale level evaluating method that makes use of electron tunneling to represent binary information [8,9].It proposes a new perspective on data transmission, in which data are transmitted through polarization transmission between QCA cells.Te most remarkable advantage of QCA devices is the easiest association between cells, with only adjacent cells obtaining a correlation [10].As a consequence, the full connection is not essential [11,12].
As QCA is among the potential candidates for upcoming computing systems, researchers are focusing on circuit design methods to represent binary data [13,14].Te Arithmetic Logic Unit (ALU) is an essential part of modern microprocessors [15].Terefore, a major focus has been given to QCA-based ALU component design [16].In ALU design, addition is a fundamental operation [17,18].In binary addition, full adder (1-bit adder) is considered the basic unit cell [19,20].Moreover, wide word length adders are mainly implemented based on a 1-bit FA cell [21,22].In addition, diferent arithmetic functions need addition in their internal nodes.For these reasons, a major focus has been given to develop efcient FA cells in QCA [23][24][25].
Being one of the most frequently used blocks in ALU, numerous QCA FA circuits have been developed over the course of time.However, as more designs come in, it often becomes quite difcult and time-consuming task for circuit designers to search for QCA FA designs from existing literature.Also, it takes a lot of time for circuit designers and researchers to build, analyze, and simulate every circuit to determine the optimal QCA FA circuit based on their design constraints and requirements.Existing review papers only contain a handful number of circuits [25][26][27].Also, they fail to provide a comprehensive performance comparison of QCA FAs based on various metrics.Moreover, existing review papers have not used all the important performance parameters of a QCA circuit to evaluate and compare QCA FAs.Terefore, a comprehensive study and performance comparison of existing QCA FAs is necessary to aid QCA circuit designers and researchers in selecting the suitable cell as per the system requirement.Moreover, it will reduce the time that researchers spend to fnd and simulate QCA FA cells to select their suitable designs.Tis research aims to fll up the research gaps of existing review papers by providing a comprehensive literature review and performance comparison of a wide number of QCA FA designs.
In this research, a comprehensive study on QCA FA cells has been conducted.All QCA FA cells are implemented and simulated using the QCA Designer software.Based on the simulated results, a summary table highlighting performance parameters of QCA FA cells has been provided which will aid QCA circuit designers and researchers.

QCA Overview
Te QCA technology was frstly introduced in 1993 [24].QCA circuits consist of an array of QCA cells.Each of the QCA cells contains nanoparticles or crystalline quantum dots.Basic information on QCA is provided in the following subsections.

2.1.
Basic QCA Cell.As demonstrated in Figure 1(a), a QCA cell is like a square-shaped box that contains four quantum dots stationed at four individual corners [13].Two electrons are present in each cell.Because of Coulombic interaction, the electrons of a cell are positioned diametrically into two opposite quantum dots (also called antipodal dots).As a result, electrons can occupy the quantum dots P 1 and P 3 or P 2 and P 4 .Tunnel junctions link the dots through which the electrons can change their diagonal positions.Based on the position of charges (electrons), two distinct conditions or states are possible.In Figure 1(a), the state where electron pairs occupy quantum dots P 2 and P 4 is known as positive polarization (polarization � 1).Tis positive polarization state represents binary 1.On the other hand, the state where electron pairs occupying quantum dots P 1 and P 3 is known as negative polarization (polarization � −1).Tis negative polarization state represents binary 0. Te QCA cells utilized in this research have length � 18 nm, width � 18 nm and dot diameter � 5 nm.
Based on the orientation of the quantum dots, QCA cells can be two types: 90 °cells and 45 °cells (Figure 2).Te number of quantum dots and electrons is the same in both cells.Te main diference is in the orientation of the quantum dots.Polarizations and their respective binary equivalent states of 90 °cells, and 45 °cells are shown by using Figure 2.

QCA Wire and Data Transmission.
To transmit data in QCA confgurations, an interconnection architecture among elements must exist.As per the orientation of the QCA cell, QCA wire or interconnect can be divided into two groups: 90 °wire and 45 °wire (Figure 3).From Figure 3(a), it can be perceived that the input provided is a binary 1 logic [13].Coulombic repulsion force among the electrons in the input cell and the cell adjacent to the input cell enables the electrons to get arranged diagonally so that maximum distance can be maintained between two electrons in two adjacent cells.Since the binary state of the output cell is equivalent to the binary state of the input cell, it can be said that the QCA wire in Figure 3(a) is passing binary logic 1 from input to output.Exactly, in the same manner, binary logic 0 is passed in the QCA wire shown by Figure 2(b).Here, Figures 3(a) and 3(b) represent 90 °wire.Now, in Figure 3(c), binary logic 1 is provided in the input cell.To maintain diagonal distance due to Coulombic repulsion, the electrons in the adjacent cell get arranged in the opposite manner to the input cell.In this way, data gets transmitted through a 45 °wire.It can be observed from the output cell in Figure 3(c) that the electron pair position is exactly the same as the input cell.Terefore, the 45 °wire in Figure 3(c) is passing binary logic 1.Using the same methodology, 45 °wire in Figure 3(d) is passing binary logic 0.
As per wire crossing, QCA wire can be classifed into two groups: single layer crossing and multilayer crossing [26].Single-layer and multilayer QCA wire crossings are presented in Figure 4.As perceived from Figure 4(a), a single layer QCA wire crossover is realized using both 90 °and 45 °wires.
On the other hand, a multilayer QCA wire crossing requires at least 3 layers of QCA cells to transmit data without interacting with the wire below it.In this type of wire crossing, a layer is added above or below another.Tis sort of wire crossing is quite identical to the conventional interconnect system in the CMOS process, where several metal layers are being used.In the case of two parallel wires/ lines containing diferent signals, the spacing of one QCA cell is required [25,27].Terefore, the distance between two QCA wires/lines is equivalent to the length/width of a QCA cell (18 nm).For a 3-input majority gate, the logic function can be expressed as follows [21]: Schematic of two majority gates (3-input and 5-input) are shown in Figures 5(a) and 5(b).Te design of a 2-input AND gate can be done by utilizing a 3-input Majority Gate.If a logic 0 is provided to any of the inputs of a 3-input majority gate, then it behaves like an AND function.Conversely, implementation of a 2-input OR function using a 3-input majority gate can be done by providing logic 1 in any of the inputs.In FA, the output carry circuit signal can be easily generated by using a 3-input majority gate.Two types of inverter circuits are possible in QCA logic design which is shown in Figures 5(c  Advances in Materials Science and Engineering 2.4.QCA Clocking.QCA circuits require clock pulses to operate.Te clocking scheme of a QCA technology can be understood using Figure 6.QCA clocking is divided into four phases: switch, hold, release, and relax [13].Te switch process begins with unpolarized QCA cells having low potential barriers.However, the barriers get higher as the phase progresses.In the hold phase, the barriers are kept high.But in the release phase, the barriers are reduced.In the relax step (fnal step), the barriers are kept lowered which allows the cells to remain unpolarized.Tat inter-dot barrier inside a clocking zone and the activity of a QCA wire in separate clock zones are shown in Figure 6.A crucial distinction between QCA circuit architecture and traditional CMOS technology is that, unlike CMOS, QCA circuits have no control over the clocks [28].As a result, information is only passed through each cell and therefore not stored.In every clock cycle, each cell erases its state.

QCA-Based Full Adder (FA)
A literature review on QCA FAs and the general logic design aspects are presented in the following subsections.

Literature Review.
A QCA-based FA is the fundamental unit to design a multibit adder.Terefore, numerous QCA full adders have been designed.Some of the full adders have low complexity, and some of them have high.Some of them require more or less time for the generation of output.
Te QCA-based architectures can be divided into two major types: coplanar (single layer) and multilayer.Coplanar designs have only one layer, whereas multilayer designs can have three or more layers.Te frst QCA FA was presented by Tougaw and Lent [29].Tey have used three inverters and fve three-input majority logic gates.Te designed FA was coplanar-type.However, this design is incompatible with implementing larger circuits.With three inverters and fve 3input majority gates, another coplanar FA design is proposed in [30].With the implementation of fve majority gates and six inverter gates, a QCA FA is designed in [31].New architectures of QCA-based FAs are shown in [32][33][34][35][36][37][38][39].Tese QCA FAs are coplanar-type designs.With the help of only three majority gates, another QCA FA is implemented in [40].No inverter gate is used in this design [40].By using one inverter and two majority function gates, two QCA FAs   Advances in Materials Science and Engineering are shown in [41,42].With one 5-input majority gate, two 3input majority gates, and two inverters, another coplanar type FA is shown in [43].
A new design of FA using QCA reversible logics is implemented in [28].Another schematic of QCA FA is shown in [44].More designs are demonstrated in [45][46][47], where one XOR gate and one majority gate are used.By using only two XOR gates, another schematic of FA is presented in [48].Another coplanar type FA with an inverter and a three-input majority gate is shown in [49].Another new two FA schematic was presented in [50][51][52].Tis coplanar type full adder was designed with a fve-input majority gate, two inverters, and a three-input majority gate.By using reversible logic, another schematic of FA is presented in [52].One inverter and three majority gates are used in this design.With one three input majority gate, one fve-input majority gate, and one inverter, another coplanar type QCA full adder is presented in [53].
With the use of three majority gates and two inverter gates, multilayer crossover types QCA FAs are proposed [54,55].Tese designs have three layers.With three majority gates and two inverter gates, three more multilayer QCA FA are implemented in [56][57][58].Further, with the help of three majority gates and one inverter circuit, three multilayer QCA FAs are designed in [59][60][61].A new design for decreasing the delay with the combination of three 3-input majority gates is implemented in [62] without using any inverter gate.
In [63,64], highly area-efcient multilayer crossovertype QCA FAs have been proposed.Tese designs utilized 3input and 5-input majority function gates.A FA with the combination of a 3-input majority gate, inverter, and 5-input majority gate is proposed in [65].Tis full adder is a multilayertype design (three layers).Tree more schematics of multilayer QCA FAs are presented in [66][67][68].Tese schematics have been designed with a three-input majority gate, an inverter circuit, and a fve-input majority gate.Tese multilayer designs do not incorporate more than three layers.Two QCA FAs are presented in [69,70] which are implemented using one 5-input majority gate, one 3-input majority gate, and two inverter gates.Te QCA FA presented [71] is implemented with only one 3-input majority gate and one XOR gate.With the combination of one conventional three input majority gate, one fve-input majority gate, and one inverter, another multilayer type full adder is presented in [72].

General Logic Design
Aspects of QCA FA.Truth table of a QCA FA is exactly the same as a CMOS-based FA.Also, unlike CMOS-based FA, there are three input bits and two output bits in QCA FA.Among the three input bits, two are addend bits, and the remaining one is the input carry bit.On the output side, sum and carry-out are the output bits.
As per the analysis conducted in Section 3.1, it can be observed that majority gate and inverter are the major components in the QCA FA design.As stated in [21], the carry-output bit of a 1-bit FA follows the logic characteristics of a 3-input Majority Gate.Hence, for the QCA FA design, the carry-out bit can be implemented with a single 3-input majority gate.Due to this reason, majority gate plays a major role in designing the QCA FA.Now, diferent implementation methods of majority gates result in diferent cell count and layout area.For example, in general, a coplanar type majority gate requires more area than a multilayer majority gate.Moreover, multiple designs of majority gate are possible due to which the QCA FAs have diferent levels of complexity.As a result, being a major part of QCA FA design, the number of majority gates used and their design method play a major role in the complexity of QCA FA.

Design and Performance Comparison
Parameters of the QCA Full Adder Te main performance parameters for the QCA FA comparison are discussed in the following subsections.Te parameters listed below are the key attributes of a QCA circuit due to which existing papers have extensively used these parameters to compare QCA FAs.Tus, this research compares the QCA FAs based on the same parameters, which are extensively used by researchers in existing papers for QCA circuit comparison.

Complexity.
In QCA design, the complexity is measured by the number of cells required for implementing a circuit.
Tere is a proportional relationship between the complexity and the cell of the circuit.If the complexity of the circuit increases, the cell numbers also increase.

Area.
Te area of a QCA FA can be calculated by the total area covered by the circuit.Te area of the QCA circuits is usually measured in μm 2 .Te formula for area measurement is simply the length multiplied by the breadth.

Wire Crossing Type.
For transmitting the data from input to output, QCA wires are the basic needs.Two types of wire crossings are used: one is the coplanar type wire crossing, and the other one is the multilayer type of wire crossing.In the coplanar type of wire crossings, only one layer is being used, whereas for designing the multilayer type wire crossing, at least three layers are needed.
4.4.Delay/Latency.Delay is the required number of total clock cycles required to transit the data from input to output in the critical path of a QCA circuit.

Cost.
Te cost functions of QCA FA designs are calculated using the efective cost function calculation process presented in [7].

Simulation Result, Comparison, and Discussion
Numerous QCA full-adders have been designed so far.In this section, these previously designed QCA full-adder circuits will be investigated based on their complexity, Advances in Materials Science and Engineering wire crossing type, area requirement, delay, and quantum cost.To compare QCA FAs, the designs are implemented and simulated using QCADesigner software [28].Te result, discussion, and comparison of QCA FAs are presented in the following subsections.Latency, majority gate and crossover types may infuence the full adder design.Power dissipation, latency what should be considered in choosing the ideal full adder for use in higher-order designs or other applications.

Design and Performance
Parameters of QCA FAs.A coplanar type QCA full adder is designed in [29] that are consisting of 192 QCA cells.Te circuit covered an area of 0.2 μm 2 .Tis design requires 14 clock cycles for which the latency is 14.Another coplanar type full adder is presented in [30], which requires 105 QCA cells and 0.17 μm 2 area.Tis circuit also requires 4 clock cycles for the output of the design.Te quantum cost required for that circuit is 0.17.A circuit with a high cell count is presented in [31].Tis design required 292 QCA cells with a 0.62 μm 2 area and 14 clock cycles.Te quantum cost required for that circuit is 2.17.
Another QCA FA requiring 102 cells is proposed in [32], which covers a 0.1 μm 2 area with a latency of 8. Te quantum cost required for that circuit is 0.4.FA in [33] requires only 145 QCA cells that cover 0.16 μm 2 area.Tis design also has a latency of 4 and a quantum cost of 0.16.Another 220-cellbased QCA FA is presented in [34], which requires 0.36 μm 2 area.Tis requires 3 clock cycles to compute output for which its latency is 3. Te quantum cost required for that circuit is 0.27.QCA FA consisting of 108 cells is presented in [35].Tis design covered 0.28 μm 2 area, required 4 clock cycles and had a 0.08 quantum cost.An area-efcient QCA FA is proposed in [36].Tis design has 78 QCA cells covering 0.22 μm 2 area.Latency for the circuit is 3. Te cost of the design is 0.0675.A 59-cell based QCA FA coveting 0.08 μm 2 area with 4 clock cycles latency is presented in [37].Tis design has 0.043 quantum cost.Five clock cycles based QCA FA consisting 124 QCA cells is presented in [38].Tis QCA FA circuit covers 0.4 μm 2 , and the cost is 0.125.A low complexity QCA FA using 102 cells is proposed in [39].Te adder circuit covers 0.097 μm 2 area.QCA FA in [40] covers 0.154 μm 2 area and requires 4 clock cycles.Te cost of the circuit is 0.07.A robust area-efcient QCA full adder is proposed in [41], which covers 0.087 μm 2 area with 95 QCA cells.Tis circuit also requires 16 clock cycles and the quantum cost is 0.35.QCA FA consisting 61 cells and 0.07 μm 2 area coverage is presented in [42].Tis circuit requires 2 clock cycles and has a quantum cost of 0.035.In [43], a QCA FA with low complexity is presented.Tis circuit covers 0.31 μm 2 area, requires clock cycle 2, and has a quantum cost 0.05.A high cell count coplanar QCA FA is demonstrated in [28].Te required number of cells is 396.Tis circuit covers 0.65 μm 2 area.Te latency is 16 clock cycles and cost are 10.2.In [44], an 86-cell-based QCA FA circuit is demonstrated which covers 0.08 μm 2 areas.Te latency for this circuit is 4. Te cost of the circuit is 0.08.A circuit presented in [45] consists 60 cells and covers 0.11 μm 2 .Tis circuit with 4 clock cycle latency has a cost of 0.06.Another FA with high cell count is shown in [46].Tis circuit requires 28 QCA cells.Te latency of the circuit is 2 and area coverage is 0.02 μm 2 .Also, the cost of the circuit is 0.01.A 61-cell-based QCA FA is further presented in [47].Tis circuit covers 0.06 μm 2 area, requires 3 clock cycles for the output and the cost is 0.0225.A circuit having 124 cells, covering area 0.12 μm 2 and having 12 clock zone latency is presented in [48].Te cost of the circuit is 0.27.A 63-cellbased FA is presented in [49].Tis circuit required 3 clock cycles for the output and covers 0.1 μm 2 .Te quantum cost of the circuit is 0.0375.A low complexity FA with 71 cells is presented in [50], which covers 0.12 μm 2 with a latency of 3. Te cost of the circuit is 0.045.In [51], a QCA FA with low complexity is presented.Tis circuit covers 0.04 μm 2 area, requires clock cycle 4, and has the quantum cost 0.04.Another FA having high quantum cells is presented in [52].Tis circuit requires 118 QCA cells.Te latency of the circuit is 3 and area coverage is 0.4 μm 2 .A 95-cell-based QCA FA is further presented in [73].Tis circuit covers 0.037 μm 2 area, requires 4 clock cycles for the output, and the cost is 0.12.With 59 QCA cell, another design is presented in [53].Tis design covers an area of 0.04 μm 2 , having the latency 3, and the quantum cost is 0.03.All QCA FAs presented in 73] are coplanar type.
A multilayer type QCA full adder is presented in [54], which consists 93 cells covering an area of 0.087 μm 2 .Tis design requires 4 clock cycles at a cost of 0.087.Another efcient QCA FA is presented in [55], which requires 135 QCA cells with a latency of 5. Tis circuit covers 0.61 μm 2 area with 0.175 as quantum cost.Te QCA FA design in [56] is implemented with 73 cells which cover 0.09 μm 2 .Te latency for the circuit is 3, and the cost is 0.03.In [57], the QCA FA proposed covers 0.14 μm 2 with a latency of 6. Tis calculated quantum cost for this circuit is 0.08.An 82-cellbased QCA FA is further presented in [58].Tis circuit covers 0.24 μm 2 area, requires 3 clock cycles for the output and the cost is 0.0675.A low quantum cost based QCA FA schematic is presented in [59], which required 86 cells with an area of 0.17 μm 2 .Te quantum cost is 0.06.A design with a 0.16 μm 2 area is presented in [60].Delay for this circuit is 1 and cost is 0.0175.An area-efcient design is presented in [61] that requires 38 QCA cells covering an area of 0.02 μm 2 .Te circuit is also efcient in terms of speed since its latency is 6.Te quantum cost for this circuit is 0.011.QCA FA presented in [62] requires only 79 cell which accounts for 0.064 μm 2 area.Te latency for the circuit is 4 and the cost is 0.064.A QCA FA having area 0.076 μm 2 , is presented in [63].Tis design required 58 QCA cells which produce a latency of 3. Te cost of this QCA FA circuit is 0.03.Te schematic of QCA FA presented in [64] has 23 QCA cells with an area of 0.01 μm 2 and latency 3. Te cost of this design is 0.0075.A QCA FA having a low area (0.03 μm 2 ) and low quantum cost (0.02) is presented in [65].Te cell count for this design is 51.Te latency of the circuit is 3. Another 79-cell-based QCA 6 Advances in Materials Science and Engineering FA design is proposed in [65].Te 79 cells cover 0.05 μm 2 area.Tis circuit needs 5 clock cycles for the output generation.Terefore, the calculated cost is 0.08.Te design in [66] 0.02 μm 2 area due to having 31 QCA cells.Tis design requires only 2 clock cycles for output generation.As a result, the calculated cost is 0.01.A QCA FA design having 33 cells and 0.02 μm 2 area covered is shown in [67].Te latency of the circuit is 3 and quantum cost is 0.015.QCA FA in [68] requires 30 QCA cell to implement which corresponds to an area of 0.004 μm 2 .Te latency of the circuit is 4 and the cost is 0.004.With 22 QCA cells and 0.01 μm 2 area, a QCA FA is presented in [69].Te latency of this design is 3 for which the cost becomes 0.0075.Another QCA FA circuit having 61 QCA cells and 0.06 μm 2 area is presented in [70].Tis design requires 3 clock pulses from the input to the output data transition.As a result, the cost is 0.0225.A QCA FA implemented with 31 cells is presented in [71], which covers 0.02 μm 2 .Te latency for the design is 2 for which the calculated quantum cost becomes 0.01.Another low area covering QCA full adder is presented in [72].Te full adder requires 33 QCA cells [74], 0.01 μm 2 area, has a latency 2, and the quantum cost 0.005.Te design [75] requires 28 QCA that cover a 0.01 μm 2 area.Te delay of that FA is 3 and its quantum cost is 0.007.For designing a 0.02 μm 2 FA, only 18 QCA cells were required [76].Te latency of that design is 2, which requires a 0.01 quantum cost.A 128 QCA cell requiring FA is presented in [77], which covers 0.15 μm 2 area with a latency of 3. [78] requires 82 QCA cells for that FA design, which covers a 0.06 μm 2 area.Te quantum cost for that design is 0.045.Another low cell requiring multilayer type FA is presented in [79], which covers only 0.01 μm 2 area and whose latency is 3 and quantum cost is 0.007.All QCA FAs presented in [55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][74][75][76][77][78][79] are multilayered.
In circuit design, it becomes necessary to have a comparison of the performance parameters [80][81][82][83].Based on the performance comparison parameters of QCA FAs discussed above, a summary is provided in Table 1.Latency, majority gate, and crossover types may infuence the full adder design.Power dissipation and latency should be considered when choosing the ideal full adder for use in higher order designs or other applications.

Discussion
. Since there are several performance parameters of a QCA circuit, the application of a QCA circuit will depend on the system requirement.sFor example, systems with space constraints will use QCA FAs with a low cell count and area.On the other hand, systems, where speed is the most crucial parameter will focus on using QCA FAs with low latency.In brief, a designer needs to pick up the most suitable circuit by considering tradeofs among QCA circuit parameters to meet the design and system requirements.
Based on the design and performance parameters presented in Table 1, it can be observed that QCA FA in [69] has the lowest cell count (22).QCA FA in [81] utilized only 1 more cell than QCA FA in [64].Moreover, QCA FAs in [66-68, 71, 72] have a low cell count.On the other hand, QCA FA design in [28] has the highest cell count (396).Moreover, the cell counts of the QCA FA designs in [29,31,34] are very high.For systems that require a low QCA cell count, QCA FAs in [66-69, 71, 72] can be considered.
In terms of area coverage, the QCA FA designs in [64,69] jointly achieved the best result.Conversely, FA [28] accounted for the highest area coverage compared to the other designs.Tus, for systems having area constraints, researchers and circuit designers may consider using QA FAs [64,69] because they have less area coverage due to their low number of QCA cell count.
Implementation of a multiple-bit adder using 1-bit QCA FA can be realized by using C out signal of one bit cell as the C in signal of the next bit.Tis sort of approach is known as ripple carry adder (RCA) [74].Research works conducted in [28,30,32,38,39,41,44,47,52,54,66,73] used RCA style to implement 4-bit adder.FAs in [40,67] were extended to 8bits using RCA style.Moreover, some of the QCA FAs are extended to multiple bits using advanced adder topologies such as Carry Look-Ahead (CLA Adder [75,76].Research works in [36] showed an extension to a 4-bit CLA adder.Authors in [56] extended their QCA FA to a 16-bit CLA adder.64-bit CLA adder extension using QCA FA is shown in [59].Other than CLA, researchers in [60] showed QCA FA-based 8-bit adder extension process using Brent-Kung, Kogge Stone, Ladner Fischer, and Han-Carlson methods.In systems where scalable architectures are required, these mentioned QCA FAs are to be considered for implementing wide word-length QCA adders.

Future Research.
Energy dissipation in circuits is a major concern for circuit designers.Tis research only focused on the physical parameters of QCA FA cells.As a part of future research, the energy dissipation of QCA FA cells can be considered.To measure energy dissipation, QCAPro can be utilized as a simulation tool [84].Te hamming distance technique explained in [85] can be considered as another way to estimate energy dissipation of QCA FA cells; however, QCADesigner Pro in [86] is used by most of the researchers.

Conclusion
Since quite a number of QCA FA circuits have been developed over the course of time, it becomes quite essential to provide an extensive review of the designs.However, existing review articles on QCA FA provide only a little information on the overall circuits and their performance parameters.Terefore, a study to fll up the research gap of existing QCA FA review papers becomes the need of the day.
Terefore, a comprehensive study on existing QCA FA circuits has been conducted in this research.A total of 47 QCA FA circuits have been chosen for analysis and comparison.A brief overview of the QCA-based logic design method has been provided to understand QCA-based FA design methodology.Te circuit design methods of QCA FA circuits have been analyzed.Moreover, a summary table of all parameters related to QCA FA performance comparison has been provided to have a swift overview of QCA FA circuits.Above all, the extensive literature review and performance comparison summary table provided in this research will aid researchers by cutting of their time to search, implement, analyze, and compare the numerous QCA FA circuits to fnd the best possible cell as per the system requirements.

Table 1 :
Performance parameter comparison of QCA full adder circuits.