A HIGH SPEED ECL MULTIPLEXER IN BEAM LEAD , HYBRID TECHNOLOGY

A high speed ECL multiplexing unit which accepts 4 channels of data and control information is described. Compatibility with commercial circuits to facilitate economic interfacing at low speed data rates is an integral design criterion. Built from flip-flops and gates made in a 5 GHz fT chip technology which includes two-level metallisation and gold beam leads, the multiplexer is mounted on a ceramic substrate and contained in a standard DIL package. Dissipating less than 0.75 watt it outputs data faster than 300 Mb/s. Some conclusions concerning the merits of combining hybrid and monolithic technology are drawn.


INTRODUCTION
These include methods for tackling various multiplexing problems such as jitter, justifica- tion, error checking and channel synchronisation.This paper describes one part of a high speed multi- plexing unit, the unit which accepts data streams from several channels and transmits them in a single ordered stream over a broadband link.The input channels, previously synchronised, would need to contain in addition to the data, any necessary control information such as frame words and justification digits.
Unless a system can be made on a single chip careful partitioning into subsystems is necessary to obtain the maximum speed benefit from the available technology.Propagation delays due to line lengths on ceramic substrates and printed circuit boards must be borne in mind when deciding on the subsystem packaging.Further constraints on packaging are set by dissipation limits.These are closely linked to reliability which is an important requirement of the national telecommunications authorities.185 2. SYSTEM AND CIRCUIT DESIGN Partitioning of the multiplexer into several chips was necessary because of technology limitations.Fifty high definition transistors per chip was the maximum complexity possible with the available mask making facility.The multiplexer, built of two standard logic elements, viz: gates and flip-flops in a shift register arrangement, is shown in Figure 1.There are 4 input channels and these accept the 4 data streams which are sequentially gated to the output by timing pulses generated when the shift register is clocked.
High speed logic systems invariably involve emitter coupled, current mode circuits.Enhanced speed can usually be obtained by increasing dissipa- tion subject to temperature limits set by systems packaging.In this particular design the objectives were to mount the multiplexing function on a single substrate to minimise interconnection delays, and to keep the power level below 0.75 watt to enable standard DIL packaging on printed circuit board to be used.This would ensure, even without forced cooling, a chip temperature rise no higher than 30C above ambient.
Figures 2 and 3 show the gate and flip-flop circuits which are conventional in design and operate at standard ECL levels to permit easy interfacing with commercially available circuits.Dissipation is close to ECL OK series logic viz: 50 mW per dual gate and 100 mW per flip-flop.When choosing transistor geometries and d.c.biasing conditions for high speed switching circuits consideration must be given to the variation offT with current.The transistor should not be operated at currents significantly beyond those giving maximum fT.

CHIP AND SUBSTRATE TECHNOLOGY
The silicon integrated circuit chips are made using a high fT (5 GHz), double level metallisation, beam lead technology.Beam lead terminations, besides offering low inductance connections, simplify the practical aspects of chip assembly and replacement.
Conventional silicon technology is used to make Dual input gate FIGURE 2 Dual 4 input gate.the active device and resistor regions on the chip.An epitaxial n layer f2cm to 2 2cm resistivity and 3.5/am thick is deposited on a 15 2cm p-type <100> orientation slice.For deep regions (3>0.8 um) deposi- tion and diffusion processes are used.For the emitter and base regions implantations are employed.Emitter window width is 2/m, the smallest practicable size, and first level metallisation is AI(1%Si).Molybdenum is then deposited and defined to form a connecting bridge between aluminium and the subsequently sputtered and plated upper level gold, thus preventing unpleasant intermetallic compound formation.
To form separate chips the wafers are mounted on a glass plate face downwards and etched to a thick- ness of 40 gm.After pattern definition using infrared microscopy a preferential etch is applied so that crystal planes define the sides of the chips.A sum- mary of the technology parameters and a schematic section through a silicon device is shown in Figure 4.
At this stage the beam leads are available for probing.The chips are still held to the glass plate by a wax glue and complete testing, marking and recording of the array position is necessary at this point.Failure to test thoroughly a chip that is to form part of a complex of circuit chips can lead to serious difficulty in the analysis of system faults.After probe test the chips are removed by a process which retains the array pattern so that computerised pick-up tools can be used for selcting good devices.Figures 5 and 6 show gate and flip-flop chips.
M.R.C. "Superstrate" ceramic substrate (0.5 mm) is the base material for chip assembly.The first operation is to make holes by laser beam or ultrasonic drilling at points that require connection to the underside ground plane.These cavities are then plugged with gold wire.The subsequent processes of deposition, photolacquering and plating-up to produce thin film resistors, gold conductors and ground plane are conventional.The nichrome sheet resistance is 100 f2/ and trimming is by spark erosion.Resistor temperate coefficient is < 100 ppm/C and stability is maintained better than 99.9% for 1,000 hours at 150C.Assembly begins by mounting the substrate in the header using an epoxy conducting compound.Next chip capacitors are soldered into position to be followed by the beam lead components which are pressure bonded using a thermal wedge tool (300C).Connection from substrate to package pins is by a gold wire ball bond.The assembled multiplexer is shown in Figure 7.

RESULTS
For gate circuits a simple d.c.probe test was sufficient to determine good chips but the flip-flops oscillated under similar test conditions.Instead a toggle test circuit using 502 microstripline probe connections to the chips was preferred.The output was observed on a sampling oscilloscope and, although a tedious method, it was always dependable.higher than 450 MHz and the complete multiplexer performed no higher than 350 MHz as is demon- strated by the divide-by-four pattern in Figure 11.Total dissipation of the multiplexer package was 700 mW for a supply voltage of 5.2 V. Calibration of a chip resistor over a temperature cycle of 100C above ambient allowed a direct measure of chip temperature and hence an evaluation of the thermal impedance of the beam leads.This gave a figure of 640C per watt per beam lead.For the flip-flops, with 16 leads and a dissipation of 100 mW, less than Measurements were also made of S-parameters of a control transistor included in the layout of the flip- flop chip.A 502 microstripline mounting in a common emitter configuration was used.Figure 8 shows a plot offT variation with emitter current obtained by calculation from the S-parameters.A peak of 5 GHz occurs at 4 mA which is the nominal bias of the current switch in the chip circuits.
The gate performance can be judged from the waveform to be seen in Figure 9. Propagation delay is 400 ps and rise and fall times average 900 ps.The flip-flop toggle frequency waveform is shown in Figure 10.Toggle frequencies as high as 750 MHz (typical 700 MHz) were observed in a toggle test circuit.When placed in the multiplexer package and operated as a divide-by-two function the maximum clocking rate was reduced to 550 MHz.5C rise above the ceramic substrate temperature can be expected.For the gates an even smaller tempera- ture rise results.
performance.For this ECL system design higher speed can be achieved only by higher current opera- tion i.e. higher dissipation, or a higher speed (higher intrinsic fT) technology.
A measure of appreciation of the difficulties and advantages in marrying high speed integration tech- nologies has been gained in making this multiplexer.
Monolithic integration (i.e.single chip) when prac- ticable is of course to be preferred.Nevertheless, by judicious partitioning, by building systems from standard or simplified chips, and by using a hybrid technology well suited to rapid changes in design one can arrive quickly at the optimum operating condi- tions for the total function.Such an approach to systems work is especially advantageous when tech- nological device yield sets the rate of progress.To have technology, circuit and system development proceed concurrently is a desirable though not often realised objective.REFERENCES 5. CONCLUSIONS Completion of the multiplexer meeting the design objective has allowed several conclusions to be drawn.Maximum clock frequency is considerably lower than the toggle frequency of individual components even when interconnection distances can be discounted as causes of delay.Although package parasitics contribute to delay, it is the loading of the logic functions on one another which most degrades

FIGURE 1
FIGURE 1 System architecture.

FIGURE 5
FIGURE 5 Dual gate chip.