DESIGN OF A 108 PIN VLSI PACKAGE WITH LOW THERMAL RESISTANCE KANJI OTSUKA

The design of a 108 pin VLSI package is described. The package has low thermal resistance and can, therefore, dissipate 4 watts of power. The package design is now being used commercially in high-end computers made by Hitachi.


INTRODUCTION
The increasing circuit/gate density of LSI chips presents a variety of challenges to packaging technology.The package must absorb an increasing amount of power and an ever growing number of interconnections.Packaging engineers have discussed a number of different packages, but there is no simple formula to determine the most cost effective and reliable combination of package types.
One such approach has developed a package for the ECL VLSI, which has 550 gates, 4W of power and 108 pins.

PACKAGE DESIGN
The requirement for this package design is, simply stated: A 550 gate ECL logic VLSI with 4W of power must be mounted in a single package to effect maximum performance.Therefore, the package should be designed as follows: 1) number of pins: 108 2) package size: as small as possible 3) thermal resistance: less than 10C/W 4) electrical resistance: less than 0.2 2 from inner to outer leads 5) stray capacitance: less than 3pF 6) sealing: hermetic seal 7) cost: less than the cost per pin on a side brazed dual in line package.A study has been undertaken to ascertain the feasibility of the above design concept and has achieved a package with high cost-performance.

THERMAL RESISTANCE
As stated above, the package requires very low thermal resistance.Therefore, the primary consideration in the package design had to be from the thermal standpoint.
The main thermal path for the power consumed in the chip is from the base to its surface, and from the surface to the ambient atmosphere.The former thermal conductive path had a resistance (RcD) dependent upon the thermal conductivity of the base materials.The latter is heat transfer by convection with resistance (Rcv) dependent upon the surface area of the base.Thus the main thermal resistance (RT) is determined by the following formula: RT Rcv + RCD The resistance, Rcv, is indicated by the following equation: Rcv Af.ot.
Where, Af is the surface area of the base, 0t is a heat transfer coefficient and is fin efficiency.
An experimental measurement for Rcv was studied using the comb configuration fin structure shown in Figure (a).Thermal resistance, Rcv, is well correlated to be in inverse proportion to the surface area available for heat transfer as shown in Figure (b).
The objective for the thermal resistance of the design was set at 10C/W maximum (RTMAX), but should be kept at a nominal value of 8C/W (R'rNoM) in actual performance.
Thus, a large surface area (ie.20 cm2) is required.Still, RxNoM can not equal Rcv.There must be an allowance made for RCD.The following formula was developed: RTNOM 8C/W Rcv + RCD 7C/W + IC/W _heat source On the other hand, to keep good air flow conductance, for cooling, between boards mounted with LSI's, the package height should be as small as possible.A height of 8 mm was determined for the package considering stacked plug in board spacing as shown in Figure 2, and 21.6 mm was chosen as the size of the base (square) to provide a 20 mm 2 surface area for the fin assembly, according to the design data as shown in Figure 3.
Package size reduction is desirable in high density circuits.However, there is a limitation due to the need for a large surface area for heat transfer.
Thermal resistance, RCD the remainder of RT, can have only a value up to IC/W.
Proper materials for good thermal conductivity from base to fin assembly must be chosen to achieve this value.Resistance RCD can be defined by the following equation when thermal flow flux is in parallel: ti RCD _ where, t is the thickness of each material and li is the length of each material which is assumed to be a value approximately equal to chip size.Xi is the thermal conductivity of each material.To achieve an RCD under IC/W, structure model A, from Table 1, is the only solution.This resulted in the thermal dissipation structure is shown in Figure 4.

DESIGN OF THE PACKAGE STRUCTURE
Because the size of the base area is limited by thermal dissipation, a side length of 21.6 mm was determined for the base.This in turn led to a lead pitch determined by the number of leads, as shown in Figure 5.For a 550 gate logic LSI with 108 pins, a 30 mil pitch is necessary (Fig. 5).The package structure must be an almost flat package type due to the previously mentioned height limitations (8 mm).
The glass sealed ceramic structure (similar to the cerdip) was chosen from the con- sideration of both reliability and cost.The structure can achieve hermetic seal and the objective cost compared to cofired ceramic structure.
Furthermore, the thermal dissipation metal (model A) should be built into the base ceramic without any stress.However, there is a mismatch in thermal expansion in that expansion of molybdenum in model a is too low and the expansion of copper is too high compared to an alumina ceramic base.Thus, a Kovar ring is utilized to manage the thermal expansion mismatch between the molybdenum and the alumina ceramic base, as shown in Figure 4. 2) Temperature cycle test (600 cycles,-55 -/ 150C: No hermeticity failure in 10 pieces.

CONCLUSION
The main features of this new package are as follows: 1) Flat package type 2) Outer lead pitch: 30 mil 3) High thermal conductive metal radiation with fin assembly 4) Ceramic body size: 21.6 x 21.6 mm 5) Package height: 8 mm These package features are shown in Figure 6, and package performance is as follows: 1) Thermal resistance from junction to ambient atmosphere at 5m/sec air flow: average 8C/W, maximum 10C/W.
3) Stray capacitance between the leads: 1.7-2.9pF4) Electrical resistance of the leads: .1-.5 2 FIGURE FIGURE 3 Relationship between package base dimensions and fin surface area.