COMPREHENSIVE SUMMARY OF PERFORMANCE-AFFECTING FACTORS OF CCDS

In the performance of a CCD the most important factor is the CTI (charge transfer inefficiency), which reflects the ability of the device to maintain the integrity of the charge as they travel through the device. In this paper four factors have been considered and their effect on the functioning of the SCCD has been analyzed. The factors considered here are: the interface states, feed forward due to barrier modulation, surface potential fluctuations, and the avalanche multiplication in a CCD. A computer program has also been developed to analyze the performance of a CCD. The computer program and the result listing is attached at Appx A. The factor analyzed are the CTI due to interface states, edge effect, feed forward, and the variable transfer time. The minimum frequency limit imposed due to dark current is also calculated in the program. The various losses involved with the above phenomena have also been calculated in the program. The reduction of the diffusion constant as a result of surface potential fluctuations is also calculated.


INTRODUCTION
In the performance of a CCD the most important factor is the CTI (charge transfer inefficiency), which reflects the ability of the device to maintain the integrity of the charge as they travel through the device.In this paper four factors have been considered and their effect on the functioning of the SCCD has been analyzed.
The factors considered here are: the interface states, feed forward due to barrier modulation, surface potential fluctuations, and the avalanche multiplication in a CCD.A computer program has also been developed to analyze the performance of a CCD.The computer program and the result listing is attached at Appx A.   The factor analyzed are the CTI due to interface states, edge effect, feed forward, and the variable transfer time.The minimum frequency limit imposed due to dark current is also calculated in the program.The various losses involved with the above phenomena have also been calculated in the program.The reduction of the diffusion constant as a result of surface potential fluctuations is also calculated.

CHARGE TRANSFER INEFFICIENCY DUE TO SURFACE STATES
The free charge transfer model predicts a very small transfer inefficiency for rel- atively low clock frequencies.In fact, according to the model, an arbitrarily high transfer efficiency can be obtained simply by reducing the clock frequency, thereby allowing enough time for the carriers to transfer to the next electrode.The ex- perimentally-measured values of the transfer efficiency on early devices, however, showed that transfer efficiency greater than 99.9% were extremely difficult to obtain even at low frequencies.The reason for this limit is the trapping of signal carriers at the surface states.The interaction of the signal carriers with the surface states, therefore, is the most important aspect of charge coupled devices from a practical point of view.
In a CCD such as shown in Fig. 1, the signal electrons are stored at the interface under an electrode.Some of the electrons will then make a transition from the conduction band to the surface states that are lower in energy and will be trapped there.Since the MOS capacitor is in deep depletion, there are no free holes that can recombine with the trapped electrons.When the remainder of the electrons in the conduction band are transferred to the next electrode, the surface states start to emit electrons to the conduction band.If the emission occurs while the surface potential profile is still moving the charge to the next electrode, the emitted electrons will join the remainder of the electrons and will not cause transfer inef- ficiency.If an electron is emitted from the surface state to the conduction band when the surface potential profile is no longer pushing to the next electrode, the electron cannot join the main charge packet and will cause transfer inefficiency.If no signal charge packet is directly following the main charge packet, the surface state will continue to emit the trapped electrons until a new charge packet comes along.The new charge packet will then fill up all the empty surface states.The number of electrons required to fill the surface states is a monotonically increasing function of the time interval between the two charge packets.These electrons are coming from the new charge packet and some of the trapped electrons cannot join the new charge packet because they are emitted too late.Therefore, the amount of charge lost due to the surface-state trapping depends on the number of empty charge packets even at a constant clock frequency.This property can be used to distinguish the transfer inefficiency due to the surface state trapping from free charge transfer.
Let Nss(E) surface state density (no. of states cm -2 eV-) ss (E)   electron density trapped at the surface states (no. of electrons cm -2 eV-1) The capture and emission process of electrons can now be described.
dnss VthO'n(Nss-//nn)r VthO'nNcr/ss exp () Thus dt where: r/is the number of electrons per unit volume in the conduction band (signal electrons) E Energy the trapped electron has to jump to make a transition from the surface state to the conduction band edge (E Ec Ft) If the signal electrons are stored under an electrode for a long time, a steady state is reached where dns/dt 0. In this situation Nss r/ss 1 + (Nc/r/)exp(-E/T) ( Suppose now that r/s is altered from the steady state value by nss.The variation of 8ns with time is governed by dt --[YthO'n/ + vthnN(exp(-E/KT))] 6r/ss which says that nss decreases to zero with a time constant Zc.
Z -1= VthO'.r/+ vtha.Nc(exp(-E/KT)) (4) when a new charge packet arrives at an empty energy well, the surface states trap electrons and a steady state is reached in a time which is of the order of Zc.For the surface states near the conduction band edge, the second term is dominant and Zc is of the order of 1 ps.For those states located deeper in the bandgap, the second term becomes smaller and the time constant is longer.Due to the first term, however, Zc, in the presence of a signal charge is usually very small (<1 ns), even for the deep surface states.Therefore, one can safely simplify the electron-capture process as being instantaneous.The energy level up to which electrons are trapped can be found by comparing equation (4) with Fermi-Dirac distribution functions.From the comparison, one notes that an energy level similar to the Formi level can be defined as In terms of the energy, equation ( -1 + exp[(Eff-E)/kTI Therefore, the surface states that are located deeper than Elf for normal charge density are very small: one can assume as an approximation that all the surface states are filled in the presence of the signal charge.
As the signal electrons in the conduction band are transferred to the next elec- trode, the number of electrons under the original electrode decreases and equation (6) becomes dss dt VthO'nNcqss exp(-E/KT) (7) which says that the emission of electrons from the surface states to the conduction band is now dominant.The emission time constant is dependent on the energy level of the surface state as Z-VthNcan exp( E/KT) ( If we assume that the surface states are completely filled at t 0, the total number of electrons that are emitted in time t, N(t) is This integral can be evaluated approximately for the case where Ns and O" are not varying with energy, by noting that the quantity inside the brackets is close to either unity or zero, except around This implies that the filled states at t 0 will empty to an energy level indicated by equation ( 10) by the emission process during a time period as illustrated by Fig. 2. For silicon, (VthO'nNc) is about 10" s -1.If the surface states are allowed to emit electrons for 1/ts, those surface states within about 0.3eV from the conduction band edge will emit electrons.When a new charge packet arrives, these surface states will be filled again.It is clear therefore, that the states that contribute to the transfer inefficiency in a CCD are those near band edges rather than the midgap states.The distribution of the peak will determine the transfer inefficiency.
Let us now estimate the transfer inefficiency due to the surface states.Suppose signal charge packets of magnitude Q separated by Nz empty packets, are being shifted in a 3-phase CCD at a clock frequency f0.The magnitude Q can be expressed as Q AsC0x AVs where As Area of the signal charge packet under an electrode Cox oxide capacitance per unit area AVs charge in surface potential due to signal charge (12) Let us now subdivide one clock period, To l/f0, into three time intervals as shown in Fig.
(la) and consider the surface states under one particular electrode of tkl.During T1 electrons are stored under the electrode: these by lowering the surface potential by V.All the surface states are filled except those very close to the conduction band edge.During T2, most of the electrons are transferred to the next  electrode by the free charge transfer model.If the clock frequency is low, one can asume that all the electrons in the conduction band are transferred to the next electrode in a very short time at the beginning of T2.During the remaining period of T2, surface states emit electrons and these electrons will be transferred to the next electrode joining the main-charge packet.The number of electrons emitted during this time period will be approximately N(T2) AsNssKT ln(TEVthCrnNc) During T3, emitted electrons can move forward or backward depending on the exact position of surface state surface potential profile.Here we assume that all the electrons emitted during T3 do not join the main charge packet.This as- sumption gives the worst case estimate of the transfer inefficiency.During T3 and the next NzT0 time periods, the surface-states continue to emit electrons.The total number of electrons emitted before the second charge packet arrives is then N(T2) + N(T3) + N(NzTo)= AsKTNss ln[(T2 + T3 + NzTo)s]vthO'nNc] ( when the second charge packet arrives, the surface states are filled again.If we neglect those surface states very near the conduction band edge that are not filled, the number of electrons used to fill the surface states is the same as equation (14).
When the second charge packet is transferred to the next electrode, some- trapped electrons are emitted and join the main charge packet; a process similar to that which occurred during T2 when the first charge packet was transferred.Thus, the net loss for the second charge packet is N,os AKTNss ln[(T2 +T3 + NzT0)VthO'nNc]-AsKTNss ln[T2VthO'nNc] (15) Since T1 T2 T3 T0/3 for normal operation of a 3-phase CCD Nos AsKTNs In [2 + 3Nz]   (16) The transfer inefficiency is simply the ratio of qNo to Qs.
qKTNss In[2 + 3Nz] Co,, AV (17) Note here that the transfer inefficiency is independent of the clock frequency.Therefore, when the clock frequency is sufficiently low, the transfer inefficiency is determined not by the free charge transfer but by the surface state trapping.The magnitude of inefficiency for Cox 3.5 x 10 -8 Vs 5V Nss 10" cm -z eV -is about 4 10 -3 at room temperature for Vz 1.Although the result has been obtained with many assumptions, this value is in reasonable agreement with ex- perimentally measured inefficiency.
In digital applications of CCDs, one and zero can be represented by the presence and absence of signal charge in the energy well.However, one can also represent ZERO by small charge packet rather than the absence of it as long as the output circuit can distinguish it from ONE.The ZERO is called background or FAT ZERO.In the presence of FAT ZERO, all the energy wells in a CCD have signal charge and the surface states are not subjected to a long emission process.There- fore, the transfer inefficiency due to the surface states will be much smaller.

FEED FORWARD DUE TO BARRIER MODULATION IN CHARGE COUPLED DEVICES
Conventionally, the physics of the CCD has been studied by assuming that the signal charge has no influence on the potential distribution in the barrier region.
However, Brodersen et al. (1) and Krambeck et al. ( 2) have considered the effect of signal charge on the barrier potential to some extent and have described its effect on the free charge transfer resulting in charge transfer inefficiency (CTI).
All these have shown that there exists a retarding electric field due to the presence of signal charge, which reduces the collection of carriers by the signal packet, and hence results in CTI.
Let us consider the effect of charge induced retarding field, which results in modulation of the barrier potential, on the charges emitted from the interface states.It has been shown that phenomenon of barrier modulation can result in another source of signal degradation called "feed forward of charge" (3) and would also contribute to the CTI.

BASIC CONCEPTS OF BARRIER MODULATION
In a CCD, the charge packets are separated by the barriers, which are either inherent in the structure or are created by suitable clocking of gate electrodes (4).
The exact shape of barriers is a function of charges contained in the wells.To illustrate the point, let us consider three different situations for a 3-phase CCD shown in Fig. 3.The instant for which the surface potentials are shown is when two adjacent electrodes are ON and the barrier is provided by the third electrode.
The three situations are: 1) The wells on both sides of the barrier contain equal charges as shown in Fig. 3a.The barrier will be symmetrical about the midpoint.
2) The left well contains more charge than the right well as shown in Fig. 3b.
The barrier is no longer symmetrical and the location of the peak of the barrier would shift towards the left.This is because the surface potential on the left of the barrier is lower in magnitude than the surface potential on the right.
3) The right well contains more charge than the left well as shown in Fig. 3b.
The location of the peak of the barrier would shift towards the right.

Barrier
Left well R ight well Let us consider a carrier emitted by an interface state located in the barrier region.If the carrier is emitted from a region away from the peak barrier location, it would drift to the side well because of the large electric field present there.But if it is emitted from near the peak barrier location, where the electric field is small, its motion will be determined by the electric field as well as thermal diffusion.Due to thermal diffusion some of the carriers emitted from the right side of the barrier peak can join the left well and some of those emitted from the left side can join the right well.If the potential is symmetrical near the peak barrier and the emission rates on both sides of the barrier are equal, then we can expect that the number of those carriers emitted from the left side of the peak barrier location that will join the right well will be equal to the number of carriers emitted from the right side that will join the left well.So the net charges that will join each side well will be equal to those emitted from the same side of the peak barrier location.
The above analysis implies that both the wells in situation 1, Fig. 3a will collect equal charges.However, in situation 2 and 3, the asymmetry of the barrier will result in the collection of more emitted charges by the well, containing lesser charge as compared to situation 1.
To calculate the excess charge collection, the exact shape of barrier potential for the different situations will have to be computed.A comparison of the results will give the shift X (Fig. 3) in the location of the peak barrier potential.The amount of shift Xs would give an idea about the excess charge.
Let the peak barrier be at X X0 when the wells on each side of the barrier contain ZERO (FZ) charges.To a first order approximation, the electric field E(x) near X0 may be approximated by the first term in the Taylor series expansion.
where E'(x0) is the electric field gradient at x x0.Let the signal charge (qsig) plus FZ charge be in the left well while the other well contains only FZ charge.Let the electric field in the barrier region due to this be Es(x).Then to another first order approximation we assume" where Ce(X) is the electric field per unit signal charge.
Let the peak barrier location now be at x Xm.This is the location where the net electric field is zero.Assuming that the net electric field is the sum of the electric field given by equations ( 18) and (19 The above equation (21) gives a good quantitative picture of the barrier mod- ulation phenomenon and indicates that the shift is inversely proportional to the electric field gradient at the peak of the barrier, and is proportional to the signal charge.
Again from the Fig. 3 we can see that when the shift is towards left (Fig. 3b) it is easier for charge in the left well to spill over to the right well (considering it has a ONE) and this is called the feed forward.For the case of right shift we have a reverse case, i.e., the charge in the right well moves towards the left giving us feed backward.This is confirmed by the calculated percentage shift (X/Lb) of the peak barrier location as a function of signal charge in one of the wells, when the adjacent well carries FZ charge corresponding to 5% of full well capacity.The results show that the percentage shift is reduced for larger electrode length.The shift is as much as 20% for the barrier length of 5/m and signal charge of 80%.This implies that a ZERO which is following a ONE, will collect excess charge from this shift region, compared to the case when it is following a ZERO.Similarly, a ZERO that is followed by a ONE will collect more charge than the case when it is followed by a ZERO.The former effect will give rise to an effective feed backward and latter will result in feed forward.

CALCULATION OF THE FEED FORWARD CHARGE
Consider the 4-phase push operation of the CCD.The clock-waveforms are shown in Fig. 4. The surface potentials at various instance of time are shown in Fig. 5 in terms of the following parameters: Tt---is Tc/p, where T is the clock period and p is the number of phases.
K0is the FZ charge as a fraction of the full well charge.toffis the turn off time of any of the phase clocks.

Wwidth of channel
Let the surface potential beneath (h2 and (])4 in their OFF condition be less than that of ( and 3. 1) At t 0-the charge is stored under b2 and (3 (Fig. 5a) 2) At t 0 / (])4 turns on and (k2 starts to turn off.At t K0toff, FZ charge leaves b2 (Fig. 5b).
3) At t toff, b2 has fully turned off and the barrier peak is under TIME 0 .oss1Tt 4) At t Tt + t) goes on and (])3 starts to turn off.At t Tt + + K0toff, all the FZ charge leaves (3 and at t Tt + tory, ()3 has fully turned off (Fig. 50.5) At t 2Tt + b2 goes on and b4 starts to turn off (Fig. 5e).6) At t 2Tt / t off, b4 has fully turned off.
Let us consider the feed forward charge QFP per two transfers i.e. during t toff to 2Tt / tore.There are four distinct durations that can be considered" 1) t to, to Tx, when the peak barrier is under b. which is the right barrier electrode (Fig. 5c).Let the shift be Xsp.
2) t Tt to Tt / toll, when the peak barrier is under b2, and b2 is the left barrier electrode and tk3 is turning off (Fig. 5d).
3) t Tt + toe to 2Tt, when the peak barrier is under (])2 and it is the left barrier electrode (Fig. 5e).Let the shift be Xsp3.4) 2Ttt0 2Tt + toee, when the peak barrier is under b3 and it is the left barrier electrode.Let the shift be Xsp4.Let qp, qep2, qep3 and qep4 be the feed forward charges during the above mentioned 4 durations, respectively.
The number of charges emitted per N(t) NssKTln(antVthNc) per unit Area in time t.So the total charges emitted per unit area between times t and t2, when the free charge leaves the electrode at time to, can be derived as: N(t2' t' t)NssKT In (t 2-t(-t 0 ) t 0 (22) Using the above equation Let us assume Xsp2, Xsp3, Xsp4, which are shifts when the barrier peak is under the left barrier electrode, are all equal to XspL and Xspl, which is the shift when the barrier peak is under the right barrier electrode.Then taking k0toff " toff and Tt, we get from eqs. (23) to (26)   (27) CTI DUE TO BARRIER MODULATION Barrier modulation will not only result in feed forward of charge but also would result in CTI.When a 3-or 4-phase CCD is operated with push clock, normally the barrier is provided by two or three adjacent electrodes.There are four types of barriers that are usually encountered in a CCD.These are shown in Fig. 6a,b,c,d.We shall refer to them as case 1, 2, 3 and 4 respectively.Let (sL and (sr be the nominal surface potentials (magnitude) beneath the left and the right barrier electrodes respectively.In cases 1 and 2 (Fig. 6a and 6b), the barriers are asym- metrical about the inter electrode gap.In case 1, bsr < bsL and the peak barrier location is beneath the right barrier electrode.In case 2, br > (sL and the peak barrier location is beneath the left barrier electrode.In case 3 and 4 (Fig. 6c and 6d), the barriers are symmetrical and bsr bsL.In case 3, there is a small local barrier beneath the inter-electrode gap region, where as in case 4 there is a small local well beneath the gap region.Asymmetrical wells are formed when the OFF voltages of the phases have not been compensated for the threshold voltage difference of the electrodes.When the OFF voltages have been compensated for the threshold voltage difference, a symmetrical barrier with a small local barrier beneath the gap region (Fig. 6c) is usually formed for a p-channel device.However, in case of an n channel device with wide inter-electrode gaps, a local well can be formed (Fig. 6d).
Let us consider the barrier modulation for the four different cases mentioned above.Due to barrier modulation, the CTI will arise because of the shift in the peak barrier due to the presence of signal charge in the well on the right of the barrier (Fig. 6c).This is in contrast to the feed forward, which arises because of the shift in the peak barrier modulation due to signal charge in the well on the left of the barrier.

Case 1
The peak barrier location is under the right barrier electrode as shown in Fig. 7a.
Due to the presence of a signal charge (ONE CHARGE) in the well to the right of it, the barrier peak will shift towards the right as shown.Let the shift be x's as shown previously.where (toff Ktof) is the time that the electrode takes to turn off after ONE charge leaves the electrode.For the case toff < Tt this loss can be significant.When Ktoff " Tt and toll, we get qb X's WqNsKT In (Tt-f) The peak barrier location is under the left barrier electrode and is far off from the signal charge (Fig. 7b), and the electric field decreases very rapidly with distance.
Thus, the contribution to CTI would also be negligible.

Case 3
The peak barrier is under the inter-electrode gap (Fig. 7c) and the contribution to CTI due to barrier modulation in this case would be similar to the contribution to feed forward, which has been described earlier.

Case 4
This contribution would be similar to Case 1.Although there are two barrier peaks present, the shift in the peak barrier location under the right barrier would be effective in contributions to CTI; since this barrier peak is near the signed charge, the loss would be given by eq. ( 29).

SURFACE POTENTIAL FLUCTUATIONS
Surface potential fluctuations have been characterized in MOS capacitors by Ni- collian and Goetzberger [5] and JR Brews [6].These fluctuations arise mainly due to the random distribution of fixed and interface charges and they result in an electric field over and above the normally calculated value, which does not take into consideration these fluctuations In the patch work model proposed by Nicollian and Goetzberger [5], the surface potetnail is assumed to be constant under each patch of a characteristic Area A. The r.m.s, value of the surface potential fluctuation, try, is proportional to (Nox) /2, where Nox is the number of charges per cm at the interface [6].
The measured value of as has been found to lie between 40 to 67 mV for Nox in the range of 3   10 to 2 10 cm -2 [7].In the model proposed by Nicollian and Goetzberger, the surface potentials beneath various patches are also assumed to be uncorrelated and this would mean that the surface potential can change significantly over a distance of (Ac) /2.Nicollian and Goetzberger also found the values of Ac to be about 2.5 x 10 -1 cm2.Thus, (Ac) /2 1.5 x 10 -5 cm.Let a potential variation of 45 mV take place over this distance.This would mean that there would exist an electric field whose average magnitude value is about 3 x 103V/cm larger due to these fluctuations: this is much larger than the electric fields encountered near the barrier peak.The existence of these large electric fields due to the surface potential fluctuations would obviously affect the charge movement.These fluctuations would also result in small potential wells and barriers to be formed under the electrodes, and charge movement would mainly be determined by the diffusion charges over the small barriers: primarily it would be the average electric field profile obtained by ignoring these fluctuations, which would determine the sharing of the charges omitted from the barrier region between the two wells.So it would be reasonable to assume that the charges emitted from the left of the barrier peak (determined by the average electric field) would move towards the left well and those emitted from the right will join the right well.

CTI DUE TO SURFACE POTENTIAL FLUCTUATIONS
Due to the trapping of charges in the wells formed because of surface-potential fluctuations, CTI is increased.This possibility has been briefly mentioned by Taylor and Chaterjee [8].Let us consider this in detail.
Due to the formation of small wells under an electrode because of surface potential fluctuation (Fig. 8), the free charges would get trapped and they will have to cross small barriers to join the signal packet.This will slow down the charge transfer process.These fluctuations can be characterized by a simple first order model.

MODEL
Let the surface potential fluctuations be represented by small wells of constant depth tko.Consider a one-dimensional model where the width of the wells is equal to the width of the channel.The length of the well and the barriers are Lsw and Lb respectively (Fig. 9).Let qan and tn represent the charge concentration per cm and the barrier height for the n th well under an electrode, respectively.Since no electric field is assumed to be present in the barrier region, only diffusion current .Borrier el.ectrode  would flow.The current Jn per unit width between n th and (n + 1) th well would be [9,10].

D
Jn '-[qan exp(-l)n) qan+l exp(-)n+ 1)] ( where fl q/KT and D Diffusion coefficient of carriers. (31) Jn--bsbAqan 1+ Cox/ For the case qan/Cox " q/fl, which holds for the last pattern of the charge, we get from equation (34 This equation indicates that in the presence of surface potential fluctuations the effective diffusion coefficient, Deff, would reduce significantly when bd "> 1 The way this model has been described, the value of bd would be 2 tr where tr is the rms value of surface potential fluctuations.This is derived below" as is defined as lf0L trs (s(X) Os) dx (42 where Lf Any large length bs(X) Surface potential at x. bs(X) Average value of surface potential at x.
The dash-dot line in Fig. 9 represents the average value tks bd/2 below the barriers.The potential at barriers s tkd/s and at the bottom of the wells is + tkd/2.Using equation (42 For the reported values of as in the range of 40-67 mV, the effective diffusion coefficient Deft for the last portion of the charge to be transferred would be reduced by a factor of about 10-100 over the normally assumed value.This indicates that the charge transfer process would slow down considerably and can result in CTI.

AVALANCHE MULTIPLICATION IN CHARGE COUPLED DEVICE
Avalanche multiplication in semiconductor devices is a well known phenomena [11, 12].This occurs when carriers pass through an electric field of the order of 105 V/cm.Due to the high electric field, the carriers attain sufficient energy to generate hole-electron pairs.The high energy carriers are called hot carriers.The generated carriers add to the signal charge, and hence give rise to effective carrier multiplication.
In charge coupled devices, application of a voltage of the order of 10V between the-closely-spaced electrodes results in a maximum electric field of the order of 105 to 2 105 V/cm beneath the interelectrode gaps.This high electric field can result in a number of phenomena in CCD, such as carrier velocity saturation, [11][12][13], lower probability for a carrier to get trapped in an empty interface state and high emission probability for the trapped charges [11], reduced charge handling capacity [14], and avalanche multiplication (impact ionization) [11,12].
Hess & Sah [11,12] have pointed out the theoretical possibility of avalanche multiplication.Let us consider this in detail.

THEORETICAL POSSIBILITY OF AVALANCHE MULTIPLICATION IN CCDS
Consider a 2-phase CCD.In such a CCD, there is a barrier to give directionality to charge transfer as shown in Fig. 10.This barrier could be achieved by suitably clocking a 4-phase CCD [4].The presence of a barrier gives rise to a large electric field, which is typically concentrated within about 1/m around the inter-electrode gap [15].For a sufficiently larger barrier height (Dh (Fig. lc), a large electric field of the order of 10 V/cm may be present over a distance 'd' of 1/m, and this can cause generation of hole-electron pairs due to impact ionization when a carrier falls down this barrier and becomes hot.In an n-channel device, the generated electrons will add to the signal packet and the generated holes will tend to drift towards the bulk semiconductor and contribute to the substrate current.The generated electrons and the signal electrons can again acquire sufficient energy and generate more hole-electron pairs, thereby causing an effective multiplication of the signal charge.The generated holes will be subjected to two electric fields: the field along the surface will tend to move them towards the barrier (-x direction) and the field in the y direction will result in their drifting towards the bulk semi- conductor (see Fig. lc).If the electric field in the x direction is large compared to that in the y direction, the holes will tend to remain in the high electric field region for a longer duration and can also cause further ionization.However, we will neglect the effect of generated holes since the ionization rate of holes is typically less than that of electrons by a factor of 5 to 10.So we assume that the multiplication is due to electrons only.It has been observed experimentally that Avalanche multiplication results in an increase of charge at the output, and this has been measured.In an overlapping gate CCD, it has been observed to occur at 8 V, which is not very high.Because of the fact that avalanche multiplication has been observed to occur at a much lower voltage than the oxide breakdown voltage, the upper limit to the amplitude of clock voltages that can be applied to a CCD is likely to be determined by this avalanche multiplication mechanism rather than oxide breakdown criterion.For CCD structures that have wide gaps, the avalanche multiplication is expected to occur at higher amplitude levels because the peak value of electric field present in the interelectrode gap region is lower than that for an overlapping gate structure.Generally in a 3-or 4-phase CCD operated with push clocks, the rise and fall times of the clock pulses are not less than a few tens of a nanosecond.Under these conditions, the bulk of the free charge can quickly equilibrate, and no avalanche multiplication is expected in the initial stage of charge transfer.But the last fraction of free charge and charge emitted from the interface states can get multiplied due to a high electric field that they would encounter near the inter-electrode gaps when the transferring electrode has been turned off.
In 2-phase operation, the free charge can experience avalanche multiplication even for small h of the order of 4-5 V.
Consider Fig. 10 and 11.Let us now calculate the increase in the output charge due to avalanche multiplication.For the sake of simplicity in the analysis, we neglect the depletion layer charge.For a gate voltage Vg the surface potential Vs is given by qn VFI3 (44) s'--Vg Ce where qn magnitude of the minority carrier C Electrode capacitance of (])2 ( ()4 gates

VFB Flatband voltage
Let b Difference between the surface potential beneath ()4 and beneath (])3 (Refer to Fig. 11) and let Aq Ab0 when ()4 does not contain any charge.
, ,J ) q. n-i.1 (n/l)th Wet[ n+l FIGURE 11 Surface potential diagram for different levels of charges in a CCD well.
Let Vx Threshold voltage difference between t2 and th as well as between b4 and q3.Now when tk4 contains charge qn, qn I) (Vn2-Vn-VTa ) C-- In a CCD, the avalanche multiplication basically depends upon the profile of electric field beneath the interelectrode gap region.These are various clocking and device parameters that affect this electric field profile.The most important parameters are the clock voltages, charges contained in the well,and the oxide thickness [15].
However, to make the calculations simpler we assume that the electric field only depends upon the surface potential difference between the two adjacent electrodes.
Hence, the gain factor g will be a function of Ark.For input charge qn into the (n + 1) th well, the output charge qn+l after one transfer will be Qn+l qn(1 + g(A)) (46) This equation is valid only for small values of input charge qn, because for large values of q,, the Ab will itself vary during the charge transfer process and output charge may not be linearly related to the input charge.For an input charge q0 into the CCD, the output charge qN after N number of transfers would be qN q0(1 + g(A)N) (47) and the gain in the output charge qN will be qN qN--q0(1 + g(A4')N) 1 (48) It has been found that the gain factor is negligible for small tk and then increases rapidly.Let Abc Critical value below which g(Ab) is assumed to be zero.
Let us consider the charge transfer process when charge enters (4 from b2 across t3 electrode (Fig. 11).
Abo is the barrier height for no charge in b4.With charge entering q4, the surface potential difference A decreases, leading to a reduction in the gain factor g(Ath).
If sufficient charge enters b4, making Ab less than Aqc, no further avalanche multiplication will take place.This indicates that the avalanche multiplication is a highly nonlinear process.
If the amount of charge entering 4 is such that at the end of the transfer process, Ab becomes less than Atkc, then a constant amount of charge generation per transfer will take place for any given input charge.From eq. (46) we have dqn+l (1 + g(Ab) dqn (49) states, because the CTI decreases with increasing clock amplitude [16].In p-channel devices, since the hole ionization rates are much smaller, higher clock voltage amplitudes should be possible and it should be possible to achieve lower values of CTI (at least at low frequencies) for equal values of all other device and interface state parameters, compared to the case.In the CCD structures with wider gaps, the avalanche multiplication is expected to occur at higher clock voltages [12], because peak value of electric field present in the inter-electrode gap region is lower than in an overlapping gae structure.This implies that much lower values of CTI due to edge effect may be possible.
The other important consequences are: 1) Maximum signal handling capacity for the strucutres with wider gaps will be more than that of overlapping gate structures because of higher possible clock amplitudes.Similarly, for a p-channel device it will be higher than that of an n-channel device.
Maximum charge handling capacity of the devices would decrease at lower temperatures, since the ionization rate increases at lower temperatures [17].
Since avalanche multiplication is a highly non-linear mechanism (in CCDs), devices operated even under weak avalanche conditions can result in a significant amount of harmonic distortion.
4) The phenomenon of avalanche multiplication could be ultilized when small signal charges are to be estimated.The charge can be multiplied by pasing it through the CCD driven by clocks. 3)

COMPUTER ANALYSIS
A detailed analysis of the effect of the interface states, edge effect, the barrier modulation, and the variable transfer time of electrons on the CTI has been done through the computer program in Appendix A. The results show that the effect of interface states creates the highest amount of CTI, followed by the edge effect, then the CTI caused by the barrier modulation.The least amount of CTI among the four is caused by the variable transfer time effect.
The losses created by these have also been calculated and can be seen in Appendix B. The low frequency limit imposed by the dark current has also been calculated for different fractions of 'alpha' and the ratio of Qdark and Qsat.

FIGURE
FIGURE la Subdivision of clock period.

FIGURE 2
FIGURE 2 Emission of electrons from the surface states.(a) All the surface states are filled.(b) Surface states near conduction band have emitted electrons.

FIGURE 6
FIGURE 6 Four types of barriers.

FIGURE 8
FIGURE 8 Small wells formed due to surface potential fluctuations.

FIGURE 10
FIGURE 10 2b CCD with surface potential diagram.