DESIGN AND ANALYTICAL STUDY OF STRAYS-INSENSITIVE SWITCHED-CAPACITOR FILTERS

Use of analog circuit elements in active networks have become very common and the demand for their miniaturization is increasing day by day. Though several methods are available for the miniaturization of these elements through large scale integration on single chips, the performance is not very satisfactory in low-frequency applications, due to the presence of parasitic capacitance that is comparable to the capacitance of active elements. As a result, the desired response gets deviated and also noise is involved. In this paper, an attempt has been made to devise methods for the elimination or reduction of the influence of these parasitic capacitances on filter circuits.


INTRODUCTION
The use of electronic filters for selective frequency filteration has become a common application in various fields.For efficient use of these filters, it is desirable that a large number of filtering stages be fully integrated on a single IC so as to occupy as little silicon circuit area as possible.
In MOS integrated technology, it is relatively simple to achieve this objective due to the following advantages as compared to conventional techniques: (i) high integration density.(ii) high precision and stability.(iii) ideal characteristics of MOSFET switches.
A more promising approach in filter design is the use of charge transfer devices (CTDs) to implement analog-sampled data transversal filters [1].However, the performance is subjected to the following limitations: that, they are relatively inefficient in using the silicon area in implementing simple frequency response functions, the insertion losses are quite significant; and that they find it difficult to achieve the required level of noise performance with integrated MOS op-amps.
Another approach to filter design is the use of switched-capacitors (SC) circuits, which consists of op-amps and capacitors interconnected by an array of periodically operated switches.The properties offered by these circuits are low sensitivity, large dynamic range, and small physical dimensions.Furthermore, these circuits gained wide popularity due to rapid advances made in their fabrication using MOS technology.Due to these advantages, the switched-capacitor (SC) circuits are favored against the active digital and charge transfer device (CTD) filters on several occasions.

U. KUMAR
The only limitation faced by SC networks is due to the involvement of parasitic capacitances, as a result of which the actual system response deviates from the predicted one.The origin of these parasitics are mainly due to the presence of stray capacitances; finite-and frequency-dependent gain of op-amps; input voltage off sets; 'ON' resistance and junction capacitances between source, drain and substrate; effect of clock feedthrough from gate to source; and drain terminals of FETs.
The application of switched capacitors is manyfold.In many switched-capacitor realizations, a conventional analog network is taken as a basic circuit and each individual resistor is replaced by a switched-capacitor resistor.The value of resistance 'R' which is to be replaced by the switched capacitor of capacitance 'CR' is given by 1 R () f CR where f switching frequency (Fig. 1).Switched capacitors can also be used to sample a floating potential difference and provide a charge proportional to the sampled voltage.These also perform operations like additions, subtractions, and inversions and also provide delays.
A switched-capacitor network is essentially a sampled data network containing switched or unswitched capacitors and active elements such as op-amps and voltage buffers.The switching operation is carried out by the clock signal.
The conventional analog resistor (b) Switched capacitor resistor.

SWITCHED-CAPACITOR FILTERS 15
In this paper the limitations of these switched-capacitor circuits are highlighted, the origin of the parasitics are carefully studied, and the effects of these parasitics on SC performance are thoroughly reviewed under some of the non-ideal candi- tions.

ORIGIN OF VARIOUS PARASITICS AND THEIR IDENTIFICATION
Parasitics resulting from the fabrication process of SWITCHED CAPACITORS: In MOS technology, a capacitor would be fabricated as shown in Fig. 2. The nominal capacitance Cm is formed by two polysilicon layers separated by SiO2.
Owing to the technology of fabrication, there exists a parasitic capacitance Cp between the bottom plate of the capacitor Cm and the substrate as shown in the equivalent circuit of the Fig.The value of Cp is usually 5% to 20% of C m [2] and its operation may be non-linear.
Parasitics resulting from the SWITCHES MOS switches are realized from MOS transistors.In the ON state they behave like a resistor, and like an open circuit in the OFF state.Parasitics exist between the source and drain and the substrate, which are of the order of 0.5 PE (Fig. 3) Parasitics due to clock feed through Clock feedthrough is due to the capacitive coupling between gate and the channel.Due to non-linearities involved in the MOS capacitors the -ve fall time of clock feedthrough does not cancel out the +ve rise time of the clock feedthrough.Hence some parasitic capacitance is always involved in switched capacitors due to clock feedthrough.

Package parasitics
These result from lead inductances, pin capacitances, and mutual coupling between bonding leads.Therefore, the signal nodes that are electrically connected as package pins should always be either driven or at virtual ground.

EFFECTS OF VARIOUS PARASITICS ON THE FOLLOWING
Finite open loop gain of the op-amp (Fig. 4(a)" The open loop gain of the op-amp is given by A() AoWp +Wp (2)  If the op-amp is used to realize a unity gain buffer (Fig. 4(b)) its gain will be A/unity gain V o/V m AoWp/ / Wp (1 + Ao) (3) The characteristic equation of the above function has a pole at p -tOp (1 + Ao).
For typical values of fp -= 20 H,. and Ao 105, this pole has negligible effect on the unity gain buffer within the entire audio frequency range of operation.

Input Off set Voltage
Assuming that the input bias current of a MOS buffer is negligible, it is observed that inverting integrators are less affected by input off-set Voltage compared to non-inverting integrators.
'ON' Resistance of the Switch At very high sampling rates, the size of the switched capacitor becomes an important consideration.The maximum permitted switching rate will be determined by the need to ensure that the capacitor charges and discharges completely during the pulse duration of the clock.This requirement sets alimit on the maximum capacitance value such that T /ON" Cm < " is satisfied.
In practice, T/2 should be about 5 times larger than (on" Cm)" Hence C m U. KUMAR

Clock feedthrough
As a result of non-linearity of the capacitors, the charges fed at the -ve and +ve transition of the clock do not cancel.This can result in a net feedthrough error voltage that has the effects similar to that of a de offset voltage.In addition, the clock feedthrough also produces noise.

ERRORS DUE TO PARASITIC CAPACITANCE ON DIFFERENTIAL INTEGRATORS' PERFORMANCE
Switched-capacitor-based differential integrators are subjected to several important deviations from the ideal behavior (Fig. 5).For the integrating capacitor C2, the only parasitic capacitor that affects the circuit operation is Cpl.The charge placed on this capacitor when input sampling switches are 'ON' is transferred on to the integrating capacitor.This results in a transfer function from input to output described by where Vdm V V 2 and Vcm V + V2/2 Thus, the effect of parasitic capacitance is to degrade the common mode rejection ratio (CMMR), and to change slightly the differential mode gain constant.
However, for non-inverting integration, the integrator is not affected by the parasitics.The frequency response of the switched-capacitor integrator is shown in (Fig. 6).This response deviates from the continuous one in a very different way.
The inherent switching process during sampling introduces an excess phase shift at frequencies approaching the clock frequency.
vou --Cp1 ---Csub A straight forward analysis (over a complete clock cycle) of the switched- capacitor differential integrator gives a frequency response given by H(W) The first term in the brackets is the response of an ideal continuous integrator and the rest of the expression is the duration from that response caused by the sampling process.The resulting excess phase shift due to the delay term will distort the frequency response of the complete filter in a way that is similar to the effects of excess phase shift in op-amp in conventional active R-C filters.Typically, the distortion takes the form of Q--enhancement, in which the response of the filter shows some undesirable peaking.

Methodl
In this method, an attempt is made to split the parasitic capacitance into a series combination of two capacitances (Fig. 7).
One capacitance is formed between the polysilicon lower electrode and the P-well and the other between the p-well and the back gate of the substrate.. Thus, the loading effect of Cpw on node N2 is a minimum and Cws does not affect the floating node 'N2' at all.

U. KUMAR CASE STUDY
Often in filter design, the need arises for a differential integrator that integrates the difference between the analog voltages.Here, in this case study we consider the case of an integrator (Fig. 10).
The input/output relations for the circuit are given by ( If the same circuit is analyzed in switched-capacitor form, then the equations relating the input and output will be as per Vou FIGURE 10 (a) A conventional differential RC integrator (b) A switched capacitor differential integrator.
The expression (10) can be modified in view of (Fig. 10) to give the form of Vut V (vl v2) + Vl (11) and a straight forward analysis of the switched capacitor integrator gives the frequency response 1 C Cpl V ] H (W) 20 log 10 2j sin (toTer2) C2 C2 Vl V ' ----' exp (-jwTef2) dB (12) The response of this expression is plotted in Fig. 6 for different values of frequencies (200 to 4000 Hz) for two different conditions. Condition--1 Cpl 0, i.e., no parasitics involved.
The following parameters were used for the simulation of the case-study.
On comparison of the responses of the circuit in the presence of parasitics to that of the original circuit, we find that the gain of the integrator is distorted due to the presence of parasitics.Hence, we have to reduce the effects of parasitics for distortionless response using compensation techniques.

CONCLUSION
The origin of different type of parasitics in switched-capacitor filters and their effects on the performance of switched-capacitor filters have been discussed.Several ways of eliminating or reducing the effects of the parasitics in switched- capacitor filters are given.

FIGURE 3
FIGURE 3 Parasitic capacitances of MOS switches.
FIGURE 4 (a) An operational amplifier with finite open loop frequency dependent gain A(s) (b) Realization of unit-gain buffer by unit-gain feedback.

FIGURE 5 AFIGURE 6
FIGURE5A switched capacitor differential integrator showing the parasitic capacitances associated with switches and capacitors.
FIGURE 7 (a) Construction of a floating m.o.s, capacitor (b) Compensation scheme.