SOME CONSIDERATIONS ON TUNNELING LOSSES IN FIELD-EFFECT DEVICES FOR LOW-VOLTAGE MICROCONTROLLERS

The loss power density associated with the tunneling current in a typical MOS cell with a floating gate is evaluated for high electric-field strengths in the oxide layer. Furthermore, problems related to oxide thickness are discussed.


INTRODUCTION
The tunneling current in MOS cells for low-voltage microcontrollers based upon EEPROM plays a crucial role in understanding the physical electronics of those field-effect devices.The above current is very sensitive to the thickness of the oxide layer in a given MOS cell because the electric field in this layer depends on the above thickness and the current depends strongly on the electric-field strength [1][2][3][4].
On the other hand, it is important to recall that A1-SiO2-Si devices with floating gate will be considered.In effect, these devices are the crucial elements in low-voltage microcontrollers based on EEPROM.These devices have two gates: the control gate and the floating gate [1][2][3][4].When the drain voltage is reduced from 5V to 3 V, the corresponding charge pump output voltage also decreases [2,3]; consequently, the control gate voltage becomes smaller.This fact *Corresponding author.
implies a decreasing of the voltage drop across the tunnel oxide [2,3].
The diminished tunneling of carriers onto the floating gate originates a slow erase operation giving rise to EEPROM fallout [2,3].
In the following, we will consider n-channel devices and we will study the loss power density associated with the tunneling current for relatively high electric-field strengths in the oxide layer.At this point, we can claim that the oxide thickness plays a significant role; in fact, some problems related to this parameter will be discussed very briefly.

THEORETICAL FORMULATION
The magnitude of the tunneling current density in question obeys the following relationship [1 5]: where e is the electron charge, E is the magnitude of the electric-field strength in the oxide layer of the n-channel MOS considered, mo is the electron rest-mass, m is the tunneling electron effective mass, h is the reduced Planck constant and Eg is the barrier height of Si and SiO2 at cathode side.
If E is sufficiently high, the exponential in Eq. ( 1) approaches unity and we can conserve the preexponential term so that we can write: J , e3E2E-3/2/(16rr2h) since m 1.1 m0 (silicon).
On the other hand, the associated power density (W/m 3 ) is given by P JE so that by virtue of Eq. ( 2) we have: e3E3E-3/2 P 167r 2h (3) Since E Vox/tox (where Vox is the voltage drop across the tunnel oxide and tox is the oxide thickness), formula (3) is a good approximation because, in practice, tox must be small (typically tox 100,; see, for example, Ref. [6] ) so that E becomes high.Then, from Eq. ( 3) it follows: ,-3/2 e3Vox,..,g P ( 4) 167r2h t3ox that is to say, if tox is sufficiently small, tunneling losses per unit volume are inversely proportional to 3 OX" On the other hand, by taking into account that Vox decreases when the drain voltage is reduced from 5 V to 3 V (see the introduction of this paper), then E is not too high and, as a consequence, formula (3) is not applicable.Certainly, decreasing of Vox and a relatively small value of tox produce a moderate value of E; for a discussion on values of tox, see Refs.[2,6].At any rate, optimization of the tunnel oxide thickness constitutes a crucial problem.Variation in critical dimension on this thickness influences the so-called erase coupling ratio and program coupling ratio which determine the voltage induced onto the floating gate from the control gate and the drain, respectively [2]; these ratios are used to evaluate EEPROM cells [2].In particular, the erase coupling ratio, that is, the fraction of the control gate voltage induced onto the floating gate is [2]: Re--Cfc/C (5) since [2]" -Vcg (6)   where C is the total capacitance on the floating gate which is given by: c= + + + (7) where Cs is the capacitance of the floating gate to the source, Cfo is the capacitance of the floating gate to the.control gate, Cfs is the capacitance of the floating gate to the substrate, and Cd is the capacitance of the floating gate to the drain.On the other hand, Vfg is the floating gate voltage and Veg is the control gate voltage which is induced onto the floating gate during the erase operation.