MODELING OF SURFACE POTENTIAL AND THRESHOLD VOLTAGE OF LDD nMOSFET ’ S WITH LOCALIZED DEFECTS

We propose a model of the surface potential and the threshold voltage for submicron lightly-doped drain LDD nMOSFET’s in relation with the localized defects at the interface Si–SiO2 in the overlap n‾ LDD region. Calculating the surface potential in the intrinsic and the LDD regions by solving the 2-D Poisson's equation, the minimum surface potential and the threshold voltage model are derived. Simulation results show that the extension of the degraded zone induce a decrease of the surface potential and a modification on its profile, this leads to an increase of the threshold voltage. The threshold voltage variation can be used to characterize the ageing effect. The DIBL (Drain induced barrier lowering) and the substrate bias effects are also included in this model.


I. INTRODUCTION
Hot carrier injection in the oxide and at the Si-SiO2 interface constitutes a potential limit to device scaling.Indeed, the transistor miniaturization entails the presence of higher electric fields near the drain.This leads to an increase of the injection of the hot carriers in the oxide and at the interface.Therefore, localized defects near the drain are created [1][2][3].These defects generate a parasitic currents [4--6].The LDD technology is used in order to attenuate the hot carriers effect by reducing the maximum of the electric field which moves toward the LDD region.However, in the LDD nMOSFETs, hot carriers induce a damage in the LDD region, this contributes to the reduction of the free carrier mobility and the increase of the parasitic LDD resistance [7][8][9][10][11].Understanding the physics of hot- carrier effects in silicon MOSFETs plays an important role in determining device degradation mechanisms and thus the improvement of MOSFET design.One of the most important parameters for studying the ageing effect is the threshold voltage [12].Therefore, we   propose to model a surface potential and the threshold voltage which considers the localized interface defects in the overlap n-LDD region.
These defects are modeled by a spatial gaussian distribution.The threshold voltage is determined from the minimum surface potential.The surface potential is determined in the intrinsic and the LDD regions by the resolution of the 2-D Poisson's equation.Effects due to the DIBL (Drain induced barrier lowering) and to the threshold voltage are taken into account in this model.

II. MODELING OF THE SURFACE POTENTIAL
The surface potential model takes into account the spatial gaussian distribution of the acceptor defects localized at the interface Si-SiO2 in the overlap n-LDD region (Fig. 1).The potential (x, y) in a point (x, y) can be determined by the resolution 2-D Poisson's equation: 02(x' Y) 02b(x' Y) -q [No(y) Na (y) + p(x, y) n(x, y)] (1)  Ox 2 + Oy : -c ---N(y), Nz(y), n(x, y) and p(x, y) are respectively, the acceptor, the donor, the electron and the hole concentrations; es is the dielectric permittivity of the substrate and q is the elementary charge.
To get an analytical solution of the surface potential, the poten- tial distribution is approximated by the following polynomial form [12][13][14]: b(x, y) b0 + bly + b:y :z + b3y (2) where the Oi are only function of x.The surface potential is determined in the intrinsic region (0 < x < L) and then in the LDD region.Boundary Conditions allow to assure the continuity of the surface potential between these two regions.
In the intrinsic region donor and hole concentrations are ignored in a n-channel MOSFET device.The surface potential is computed un- der a depletion approximation, in this case concentration n(x, y) is neglected.
Boundary conditions on the interface and the depletion edges are given by: (3) where VGs, VBS and VFB are respectively, the gate, the substrate and flat band biases, s is the surface potential; Co is the oxide capacitance by unit area and Yd is the depletion depth.Substituting (2) into (1) and integrating from 0 to Yd with boundary conditions (3) we can get: [fO0 yd02 foYdOq2]fooYd es --y2 ay + --x2 dy q NAay (4) Using the Taylor series expansion at s=2f (f is the Fermi potential), Eq. ( 4) becomes: Ox: -peS Cs 2f + Vss + (Vas-VTo)lrlp / 12CoxTp V x VTo VFs + 2@ + q,V/2/+ Vss +1 v'2: + ys, / q s VA The resolution of the Eq. ( 7) leads to the following surface potential expression in the intrinsic region: A1 and A2 are calculated using the boundary conditions at the LDD- channel junction.
The AL value as well as the constants integration A1, A2, C1 and C2 are derived using the continuities of the surface potential and the electric field at the LDD-channel junction and the boundary conditions at the source and the drain, i.e. [15]: s (gchannl) (LLDD) (aCs(x)/a) X=Zehanncl (aCs(x)/ax) x=L+L (o) Vb + Vs (L + ZXL) Vb + Vo, (as(x)/dx) Ec X=LLDD (16) Vb and VDS are the substrate-LDD junction built-in potential and the drain bias.
Using (16) we can get: A1 sinh (kpL)[-s + G2(L)sinh (knAL)] The gate bias for which the minimum surface potential is equal to 2bf is defined as the threshold voltage.The minimum surface potential 3min is gotten by solving the equation dG(x)/dx=O in the intrinsic region.
bmin bS -+-v/2A 1A2 cosh (kpL) A A2 2f (21) Distance along the channel (Ixm) FIGURE 4 Variation of the surface potential for a stressed and virgin device under two substrate bias conditions: VsB 0 V and VsB 0.5 V.

Defect Impact on the Surface Potential
The localized defects at the interface Si-SiO2 in the overlap n-LDD region are modeled by a gaussian distribution for which the variation of the maximum and the standard deviation allow us to determine of the degraded zone impact on the surface potential.The substrate bias influence is also studied.The curves in Figure 2a show that the localized interface charge strongly changes the surface potential profile.Indeed, the increase of the maximum defect density entails a reduction of the free carrier mobility in the LDD region, this leads to an increase in parasitic LDD resistance which reduces the surface potential near the drain.Figure 2b shows that the surface potential is gradually lowered by increasing the  standard deviation of the defect density distribution.The minimum surface potential decreases as the degraded zone increases.The effect of the substrate bias Vss in presence of the localized defects on the surface potential is sketched on Figure 3.This figure shows that the impact of the defect density is weaker when Vss 0.5 V.It seems that the increase of the depletion charge according to Vss reduces the effect of defects (screen effect of the substrate bias).
Defect Impact on the Threshold Voltage As in the case of the surface potential the defects are localized at the interface Si-SiO9_ in the overlap n-LDD region.The curves in Figure 4 show the variation of the threshold voltage according to the 0.4 1 1 1 maximum defect density for two substrate biases (Vss=0V and Vss= 0.5 V).For Vs=O V it is apparent that the threshold voltage increases with the defect density amount, whereas this increase is negligible when Vss 0.5 V.This can be explained by the fact that the sub- strate bias reduce the effect of the defects on the minimum surface potential (Fig. 3).
The impact of the channel length on the threshold voltage in presence of the localized interface charge is represented in Figure 5.The maximum of the guassian distribution of the defect density is equal to 1012cm -2 and the standard deviation is 0,0056pm.Simu- lation results represented in Figure 5 indicate that the effect of the localized interface charges in the LDD region is more pronounced for short channels and their influence becomes negligible when the channel length is great than 0.5 ttm.

V. CONCLUSION
This modeling allows determination of surface potential and threshold voltage variations according to localized interface charges in the noverlap LDD region.The increase of the density and the extension of the damaged zone induce a significant change on the surface poten- tial profile near the drain and an increase of the threshold voltage.Simulation results in comparison with the experimental data carry the information about damage caused by the defects.This lead to under- stand the ageing effects in order to find technological solutions to minimize the performance degradation of the MOS devices.

FIGURE
FIGURE Illustration of a spatial gaussian distribution of the localized defects at the interface in the overlap n-LDD region.

FIGURE 5
FIGURE5 Threshold voltage variation versus maximum defect density for Vss=O V and Vss 0.5 V.
Variation of the surface potential for various maximums of defect density.