IMPACT OF THE STRESS ON THE SUBMICRON N-METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR CHARACTERISTICS

In this paper, we present a drain current model for stressed short-channel MOSFET’s. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.


I. INTRODUCTION
The degradation of the NMOS transistors caused by hot carrier in- jection in the oxide and at the Si-SiO2 interface constitutes a po- tential limit to device scaling.Indeed, the transistor miniaturization entails the presence of higher electric fields that provide enough en- ergy to the channel electrons which may generate electron-hole pairs through impact ionization.These electrons and holes contribute to the gate and substrate current [1-5] and they may create damage in the oxide or in the interface near the drain junction [6][7][8].Due to its strong impacts on device and circuit reliability, the hot-carrier effect becomes an important research topic for submicrometer and deep submicrometer MOSFET devices.Understanding the physical phenomenon of the degradation process is required in order to find technological solutions to minimize the aging effect and device performance degradation.
In this work we devote our effort to develop a drain current model in relation with the defect density generated by the hot-carrier-injection during stress time.This defect density is modeled by a spatio-temporal distribution.The modeling of this defect density was developed in our previous work [9] by investigating the threshold voltage evolution according to stress time.Simulation results allow us to deduce the impact of the stress time on the I-V characteristic and on the trans- conductance.

II. DRAIN CURRENT MODELING
To consider the source and drain resistances, we treat the device as an intrinsic MOSFET in series with two ones (Fig. l).The source drain voltage can be written as:

Gtae
VDS VD,S, + (Rs -[-RD)IDs The drain current expression in the linear region is given by: lz)s ,,WOCox[Vs Vro + zxvv-rV(y)] (2 where p., W, Cox and Vas, are respectively, the surface mobility, the channel width, the gate oxide capacitance per unit area and the gate bias.0 is the carrier velocity which is expressed by" where V(y) and Ey are the potential and the lateral electric field in the channel; 0sat is the carrier saturation velocity.The parameters involved in Eqs. ( 2) an (3) are defined as: x v + i-] Oy VFB VSB,s, and f are the flat-band voltage, the substrate bias, the dielectric permittivity and the Fermi potential, respectively./% is the low field channel mobility and 0 is the mobility degradation factor resulting from vertical electric field.Xdep is the depletion width.
A Vr is the threshold voltage reduction due to the lateral electric field.
In the linear region A Vr is small and can be regarded as a constant since the lateral electric field is weak.
The defect density created during stress time leads to an increase ofthe threshold voltage and a reduction of the carrier mobility, namely: Nit(y, ts) 0 and/3 are fitting constants.
Nit(y, ts) is the defect density created during stress, it is modeled [9] by: Nit(y, ts)= Nitmax(t) e x p ( ' -( y 2 t r ( t s ) 2 -y c ) 2 ' ) " where: / a (I)" Nitmax ts S;, Vt t t(ts) a0 + b log(ts) ( W is the channel width, los is the drain current.Se 10 -15 cm 2 is the average capture cross section, Vt-107 cm/s is the thermal velocity, the exponent n has been found to range between 0.5 and 0.75 [10,11].
In our simulation it is taken equal to 0.5.tr0 is regarded as an effective impact ionization length [12].

_ 20satin
The spatial average of the defect density Nit(y, t.) expressed as" where erf denotes the error function.
From Eq. (l l) we can write VD& as: where V, V2 and V3 are given by the following expressions: V tFn WCo Esat V3 IosL By substituting Eq. ( 14) in (l), the drain current in the linear region can be expressed as: where: When Vzs increases, the carrier velocity reach the saturation for high Vs values.The saturation channel voltage Vdsat is derived by letting Eq. ( 8) equal to the expression (10) The saturation current Ldsat is determined while replacing VDS with Vdsat in Eq. ( 10): The saturation extrinsic drain voltage Vdsat can be expressed as: Vdsat Vdsat q-(Rs + Rd)Idsat (20) In order to have a smooth transition between linear and saturation regions, an effective drain voltage was used [12]: A is a fitting parameter that is extracted from experimental data.
Replacing L by L-AL and Vos by VOSF in Eq. ( 16), provides the drain current.

III. SIMULATION RESULTS
The parameters of the transistor used in the simulation are given in Table I.  2 represents the variation of the ID.-VDS characteristic for two gate bias (3 V and 5 V) before and after stress.The curves of this figure show that the drain current decreases when increasing stress time, which is due to the mobility degradation.In saturation mode part, the interface states are in velocity saturation region and can be depleted, therefore the effect of these interface state becomes insig- 2O W---40tm ;::::::: . . . . . . . .V. =5V 1016C__.3 _...:i:%'.7 . . . . ."GS ".

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T.,,e, T,tre,r 1.10s 0 2 3 4 5 Drain voltage Vos (V) nificant.Moreover, after pinch-off, the channel current is governed by the inverted channel between the source and the drain pinch-off, so it becomes virtually independent of the region between the pinch-off point and drain junction.Since the defects are mostly located in this region near the drain, its influence upon the drain current becomes less in saturation.
Figure 3 shows the variation of the drain current drift versus stress time for different drain bias.The degradation of the drain current drift increases with stress time.Also notice that the degradation the delta decrease when the drain bias increase.
111.2.Impact on the Transconductance The curves of Figure 4 show that the stress acts on the transconduc- tance, which decreases with, the stress time.The degradation of the transconductance is due to the mobility reduction caused by the in- crease of the defect density during stress time.This transconductance degradation is reduced as the gate voltage increase.Indeed, when the  Gate bias Vs (V) FIGURE 4 Transconductance variation during stress time.
gate voltage increase, the carrier density in the inversion layer increase and the effects of coulomb scattering are reduced by the screening effect.Thus, the degradation of transconductance is less significant.

Exhibit
The evolution of the ratio, between the transconductance drift Agm and the transconductance initial value gmo (before stress), versus stress time is sketched on Figure 5.This figure show that the evolution of the Ag,,,/gmo is linear, in logarithmic scale, what is qualitatively agree with the results given in the literature [13][14][15].

IV. CONCLUSION
The modeling of the current drain in relation with interface defects created during stress time is very important.Since, it allows us to understand the aging phenomenon and the amount degradation of the performances of the devices.The simulations results show that the stress leads to the degradation of the I-V characteristic and the re- FIGURESchematic diagram and equivalent circuit of MOSFET.

FIGURE 2
FIGURE 2 Variation of the los-VDs characteristic versus stress time.

FIGURE 3
FIGURE 3 Evolution of the drain current drift with stress time for different drain bias.