Active and Passive Electronic ComponentsVolume 2012 (2012), Article ID 901076, 5 pagesdoi:10.1155/2012/901076

Research Article

Effects of Annealing Time on the Performance of OTFT on Glass with ZrO₂ as Gate Dielectric

W. M. Tang,1,2 M. G. Helander,¹ M. T. Greiner,¹ Z. H. Lu,1,3 and W. T. Ng²

¹Department of Materials Science and Engineering, University of Toronto, 184 College Street, Toronto, ON , Canada, M5S 3E4²Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, ON, Canada, M5S 3G4³Department of Physics, Yunnan University, 2 Cuihu Beilu, Yunnan, Kumming 650091, China

Received 15 July 2011; Accepted 6 October 2011

Academic Editor: Hsiao W. Zan

Copyright © 2012 W. M. Tang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Copper phthalocyanine-based organic thin-film transistors (OTFTs) with zirconium oxide (ZrO₂) as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N₂ at different durations (5, 15, 40, and 60 min) to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N₂ for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport.

1. Introduction

Owing to light weight, mechanical flexibility, and low-cost fabrication, organic thin-film transistors (OTFTs) have a wide range of applications such as sensors, flat-panel displays, and RFID tags [1–3]. The first OTFT based on organic semiconductor polythiophene was reported in 1986 [4]. Heavily doped silicon substrates are generally used for the fabrication of OTFT as they are highly conductive and can act as the gate of the devices. In addition, high-quality gate dielectric SiO₂ can be thermally grown directly on the Si substrate. However, for the next generation of OTFTs and oxide TFTs fabricated on glass or plastic substrates, a metal gate electrode is necessary. By fabricating OTFTs on flexible plastic substrates, there is a potential in the future for producing roll-up displays that can be integrated into a small device such as a pen. There are three major types of dielectric used in OTFTs: inorganic dielectric, polymeric dielectric, and self-assemble layer. For inorganic dielectric materials, silicon dioxide is commonly used as the gate insulator in OTFT. However, this kind of OTFT requires a relatively high voltage (about 100 V) for operation. In order to reduce the operating voltage and hence the power consumption, high-k material is often used as a gate dielectric in OTFTs. Several high-k dielectrics have been employed to fabricate OTFT, for example, HfO₂ [5], Al₂O₃ [6], TiO₂ [7], Ta₂O₅ [8], and BaTiO₃ [9]. The performance of organic transistors depends largely on the quality of the gate insulator, the insulator/organic interface, the morphology of the organic thin film, and the charge injection process. It is essential to develop a suitable and high-quality gate insulator with appropriate morphology to achieve a smooth insulator/organic interface. The as-deposited high-k films are usually loosely packed and contain impurities and defects such as oxygen vacancies, oxygen interstitials, and/or oxygen deficiency [10]. These defects and impurities will cause transient charge trapping in the high-k dielectric and leakage current [11]. Various surface passivation methods have been developed in order to achieve high-quality high-k OTFTs, such as annealing in ultraviolet (UV) ozone and nitridation gases, surface treatment with octadecyltrichlorosilane (OTS), polymethylmethacrylate (PMMA), polyvinyl acetate and ion-beam irradiation, and using stack insulator structure. In this study, one of the most promising high-k dielectric for widespread application, zirconium oxide (ZrO₂), is used as the gate dielectric. ZrO₂ is a stable metal oxide with a high dielectric constant (~15–25) [12] and a large band gap (5.8 eV). It has been reported that ZrO₂ has the lowest leakage current [13]. Moreover, it is a promising material for the fabrication of large-area flexible displays because the ZrO₂ films can be transparent and have good adhesion with plastic substrates [14]. The effects of ZrO₂ annealing treatment time in nitrogen ambient on the electrical properties of CuPc-based organic thin film transistors are investigated. The electrical and physical characteristics of the devices are presented.

2. Experimental Details

Corning 2947 glass substrates (25 × 25 mm²) were used in this study as they are mechanical stable, low cost, and compatible with large area applications such as plasma televisions. The substrates were cleaned with a standard regiment of Alconox, acetone, methanol, and deionized water followed by UV ozone treatment for 15 min. The substrates were then loaded into a sputtering chamber with a base pressure of 2.5 × 10⁻⁶ Torr. A 150 nm thick Al gate was then deposited at room temperature with a deposition rate of 0.4 Å/sec. A 40 nm thick ZrO₂ was then deposited by sputtering from a zirconium target (99.95% purity) with an RF power of 130 W in a mixed Ar/O₂ ambient (Ar to O₂ ratio = 4 : 1). The chamber pressure during deposition was 5.67 mTorr. The samples then underwent annealing on a hotplate at 350°C in N₂ for different durations (0 min, 5 min, 15 min, 40 min, and 60 min). A layer of 40 nm p-type semiconductor, copper phthalocyanine (CuPc) was then deposited by vacuum evaporation through a patterned shadow mask at room temperature. CuPc is a stable and promising p-type organic semiconductor with the major charge carriers as holes. It can be easily obtained in large quantity and high purity and hence particularly attractive for low-cost applications in dye processing, chemical sensors, and optical data storage [15, 16]. The source and drain gold pads, 50 nm thick, were then deposited on top of the organic layer by thermal evaporation through a stainless steel mask with a channel length of 36 μm and a channel width of 961 μm. The cross-section of the OTFT structure is as shown in Figure 1. The current-voltage (-) characteristics were measured by an HP 4155A semiconductor parameter analyzer. All the measurements were taken by a probe station at room temperature in the ambient atmosphere. An atomic force microscopy (Veeco Dimension 3100) in tapping mode was employed to analyze the surface morphology, grain size, and rms roughness of the high-k ZrO₂ and CuPc films.

Figure 1: Schematic diagram of a CuPc transistor.

3. Results and Discussion

Figure 2 shows the output characteristics of the OTFTs with ZrO₂ film annealed for 0 min and 60 min. Typical - curves were obtained when a negative was applied to the devices. At a gate voltage of −3 V and a drain voltage of −4.5 V, the device with ZrO₂ film annealed for 0 min has a drain current of 77 nA, while the one annealed for 60 min has a larger drain current of 107 nA. The operating principle of OTFT is similar to that of traditional p-type MOSFET. The current flowed between the source and drain electrodes is modulated by the gate voltage . The carrier mobility of the devices in the saturation regime can be calculated using the following equation: where is the unit capacitance of the insulator and is the carrier mobility. Figure 3 shows the transfer characteristics of versus at a fixed of −2.5 V for the devices. The subthreshold slope, , is a very important parameter for OTFTs as it can be used to evaluate the switching characteristics of the OTFTs. is defined as evaluated at the steepest slope of the plot. From , the maximum density of the surface states at the organic semiconductor/dielectric interface can be estimated as where is the electronic charge, the Boltzmann constant, and the temperature in Kelvin.

(a)

(b)

Figure 2: Output characteristic curves of OTFTs with ZrO₂ gate dielectric annealed in N₂ for (a) 0 min and (b) 60 min.

Figure 3: Transfer characteristic curves of OTFTs with ZrO₂ gate dielectric annealed for various durations.

The important parameters of the devices extracted from the transistor characteristics are summarized in Table 1. It is found that the performances of the OTFTs including mobility, subthreshold slope, surface states density, and off-state current improve with annealing duration. This should be due to the fact that the OTFT annealed for longer duration can have a denser ZrO₂ film and a thicker interfacial layer [17, 18] with lower interface-trap density to suppress the leakage associated with high-k materials. In addition, longer annealing can remove more deep traps, oxide charges, and unsaturated bonds in the ZrO₂ dielectric and thus lead to a significant reduction of , and . It has been reported that dielectric roughness can affect the performance of OTFT [19, 20]. Figure 4 shows the AFM images of the ZrO₂ films with different annealing times. It is found that extending the annealing time from 0 min to 60 min can reduce the gate-dielectric surface roughness (by 9% as measured using AFM). This can contribute to the reduction of trap states, interface defects, and surface scattering on charge carriers leading to higher mobility and smaller subthreshold slope. A smoother insulator surface is also more favorable for the growth of better quality organic film resulting in larger grains CuPc film grown on the surface of ZrO₂ (~9% larger). This reduces the grain boundaries in the conduction channel for higher mobility of the device [21, 22].

Table 1: Device parameters of the OTFTs.

0 min
5 min
15 min
40 min
60 min

(×10−3 cm²/Vs)
1.19
1.21
1.23
1.31
1.43

(V/decade)
1.53
1.45
1.11
1.03
0.8

(nA)
2.59
1.73
1.39
0.76
0.73

(×10¹³ cm⁻²)
6.89
6.51
4.92
4.54
3.47

(a)

(b)

(c)

Figure 4: AFM images (scan area of 2 μm × 2 μm) of ZrO₂ surface with different annealing treatment times: (a) 0 min, (b) 15 min, and (c) 60 min.

4. Conclusions

In summary, CuPc-based OTFT on glass substrate with high-k ZrO₂ as gate insulator has been fabricated and studied. The effects of annealing time on the electrical properties of the devices are investigated. The study has demonstrated that ZrO₂ is a promising gate dielectric material for obtaining low operating voltage and low power consumption. Experimental results show that the OTFTs with ZrO₂ gate-dielectric annealed for 60 min have 20% higher mobility, 50% smaller subthreshold slope, 72% lower off-state current and 50% smaller maximum density of surface states than the one annealed for 0 min. The possible reasons are that longer annealing time can enhance the densification of the ZrO₂ film, the dielectric properties of the ZrO₂ film, and the quality of the CuPc/ZrO₂ interface, resulting in less carrier scattering and better grain growth.

Acknowledgment

The authors would like to acknowledge funding for this research from the Natural Sciences and Engineering Research Council (NSERC) of Canada, and Science and Technology Promotion Project of Yunnan Province (Grant nos. 2009CI130 and 2007A0017z).

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