MCML D-Latch Using Triple-Tail Cells : Analysis and Design

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML Dlatch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption.The proposed low-voltageMCMLD-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18μm CMOS technology parameters.


Introduction
The advances in semiconductor technology have led to the integration of high performance digital and analog circuits on the same silicon substrate.The traditional CMOS logic style does not provide an analog friendly environment due to the large switching noise [1][2][3].Many alternate logic styles have been suggested in [3][4][5][6] and the reference mentioned therein.MOS current mode logic (MCML) style is the most promising one due to the lower switching noise in comparison to traditional CMOS logic style [6][7][8][9].Also, it exhibits better power delay than the traditional CMOS logic style at high frequencies [6][7][8][9][10][11][12][13][14][15].Therefore, MCML style is appropriate for designing high performance digital circuits wherein a D-latch is widely used as a building block in different applications such as prescalars, frequency dividers, and sequential logic circuits [16][17][18][19][20].
The D-latch topology given in [16][17][18][19][20] is referred to as traditional D-latch and is based on the series-gating approach (i.e., stacked source-coupled transistor pairs) [9] which puts a limit on the minimum power supply.The power supply may, however, be lowered by reducing the number of stacked transistor pair levels with triple-tail cell concept [21][22][23].In this paper, a new low-voltage MCML D-latch is proposed.The static parameters for the proposed D-latch are analytically modeled and applied to develop a design approach.From the knowledge of the transistor sizes, the delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption.The proposed lowvoltage multiplexer is analyzed for high-speed and powerefficient design cases.A comparison in performance of the proposed D-latch with the traditional one is carried out for all the cases.
The paper first briefs the operation of the traditional MCML D-latch in Section 2. Thereafter, a new low-voltage MCML topology for the D-latch is proposed, and analytical formulations for different static parameters and delay are put forward in Section 3. The analysis of the proposed D-latch for the different design cases is presented, and its performance is compared with the traditional one in Section 4. Extensive SPICE simulations are carried out to validate the proposed theory.Section 5 concludes the paper.

Traditional MCML D-Latch
A traditional MCML D-latch with differential inputs  and CLK is shown in Figure 1 [24].It consists of two levels of source-coupled transistor pairs to implement the logic function and a constant current source  TR1 to generate bias current  SS .The differential input CLK drives the lower level transistor pair  TR2 - TR3 that alternatively activates the upper level transistor pairs  TR4 - TR5 and  TR6 - TR7 .When differential input CLK is high,  TR3 is OFF and the bias current  SS flows through  TR2 and is steered either to  TR4 or  TR5 according to the differential input  to ensure that the D-latch operates in the transparent state.Conversely, when the differential input CLK is low, the bias current  SS flows through  TR3 and is steered to one of the two transistors, that is, either  TR6 or  TR7 according to the previous output value such that the output does not respond to the changes in the input; thus, D-latch remains in the hold state.The bias current  SS is converted to the differential output voltage (  −   ) through the PMOS transistors  TR8 and  TR9 [24].The load capacitance   includes the effect of fanout and the interconnect capacitances.
The minimum supply voltage,  DD MIN TR , for the traditional D-latch is defined as the lowest voltage at which all the transistors in the two levels and the current source operate in the saturation region [25] and is computed as where  T TR is the threshold voltage of the transistors  TR4,5,6,7 ,  T TR1 is the threshold voltage of  TR1 , and  BIAS is the biasing voltage of  TR1 .The minimum supply voltage,  DD MIN LV , for the proposed D-latch is computed by the method outlined in [25] as

Proposed Low-Voltage MCML D-Latch
where  T LV is the threshold voltage of transistor  LV3,4,5,6 ,  T LV1 is the threshold voltage of  LV1 , and  BIAS is the biasing voltage of  LV1 .

Static Model.
The static model is derived by modeling the load transistors  LV9 ,  LV10 by an equivalent linear resistance,   [26].Using the standard BSIM3v3 model, the linear resistance,   is computed as where  DSW is the empirical model parameter,   the channel width of the load transistor, and the parameter  int is the intrinsic resistance of the PMOS transistor in the linear region and is given as where  ox is the oxide capacitance per unit area.The parameters  eff, , V , ,   , and   are the effective hole mobility, the threshold voltage, and the effective channel length of the load transistor, respectively.It may be noted that if equal aspect ratio of all transistors in the triple-tail cells is considered, then the transistors  LV7 and  LV8 will not be able to completely switch OFF the transistor pair  LV3 - LV4 and  LV5 - LV6 .Hence, for proper operation, the aspect ratio of transistors  LV7 ,  LV8 is made greater than the other transistors' aspect ratio by a factor .As an example if the value of differential input  is chosen such that the transistors  LV3 ,  LV5 are ON while the transistors  LV4 ,  LV6 are OFF, then a high differential CLK voltage turns ON the transistor  LV8 .But since the transistors  LV5 and  LV8 have the same gatesource voltages, the currents flowing through  LV5 ( ,5 ) and  LV8 ( ,8 ) can be written as The current through  LV5 can be minimized by increasing factor .This input condition produces minimum output voltage  OL as L/H = low/high differential input voltage,  1 =  SS /2,  2 = ( SS /2)(/(1 + )), and where  ,3 ,  ,4 ,  ,5 , and  ,6 are the currents through transistors  LV3 ,  LV4 ,  LV5 , and  LV6 , respectively.The differential output voltages for various input combinations are enlisted in Table 1.It can be observed from Table 1 that there are two values of maximum output voltage ( OH ) and minimum output voltage ( OL ) for different input and output combinations.Consequently, the voltage swing,  SWING1 , when the input and output are the same can be expressed as where  OH1 ,  OL1 are maximum output voltage and minimum output voltage, respectively, for the same input/output.The voltage swing,  SWING2 , when the input and output are different can be expressed as where  OH2 ,  OL2 are maximum output voltage and minimum output voltage, respectively, for different input/output.As  SWING2 <  SWING1 ,  SWING2 has been considered as the worst case voltage swing: The small-signal voltage gain ( V ) and noise margin (NM) for the proposed D-latch are computed by the method outlined in [26] as where  eff, ,  , ,   , and   are the effective electron mobility, the transconductance, the effective channel width, and length of transistors  LV3,4,5,6 , respectively.

Transistor Sizing.
In this section, an approach to size the transistors of the proposed low-voltage D-latch on the basis of static model is developed.For a specified value of NM, factor , and  V (≥1.4 for MCML [8]), the voltage swing of the proposed D-latch is calculated using (10) as It may be noted that  SWING should be lower than the maximum value of 2  so as to ensure that transistors  LV3,4,5,6 operate in saturation region.The voltage swing obtained from (11) requires sizing of the load transistor with equivalent resistance   (= ((1+)/)( SWING / SS )).To this end, the equivalent resistance,   MIN , for the minimum sized PMOS transistor is first determined, and then the bias current  HIGH for the required voltage swing is determined as If the bias current is higher than  HIGH , then   should be less than   MIN , and this is achieved by setting   to its minimum value, that is,  MIN and   which is calculated by solving (3) and ( 4) as Similarly, if the bias current is lower than  HIGH , then   should be greater than   MIN , and this is achieved by setting   to its minimum value, that is,  MIN and   which is calculated by solving (3) and (4) as The small-signal voltage gain ( V ) (9) has been used to size transistors  LV3,4,5,6 .Assuming minimum channel length for the said transistors, the width is computed as Sometimes (15) results in a value of   smaller than the minimum channel width.This happens when the bias current is lower than the current of the minimum sized NMOS transistor,  LOW , given as Therefore, in such cases,   is also set to  MIN .For proper switching, the width of transistors  LV7,8 is made  times the width of transistors  LV3,4,5,6 .
The accuracy of the static model for the proposed Dlatch is validated through SPICE simulations by using TSMC 0.18 m CMOS process parameters and with a power supply of 1.1 V.The proposed D-latch was designed and simulated for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4,  = 5, and the bias current ranging from 10 A to 100 A.The designs were simulated, and the error in simulated and theoretical values for voltage swing, small-signal voltage gain, and noise margin using ( 8), (9), and (10), respectively, are calculated and are plotted in Figure 3.It may be noted that maximum error in voltage swing, small-signal voltage gain, and noise margin are 10%, 8%, and 14%, respectively.The impact of parameter variation on proposed lowvoltage and traditional MCML D-latch performance is studied at different design corners.The findings for various operating conditions are given in Table 2.It is found that the voltage swing, small-signal voltage gain, and noise margin of the proposed low-voltage D-latch varies by a factor of 1.8, 1.4, and 2.1, respectively, between the best and the worst cases.For the traditional MCML D-latch, the voltage swing, smallsignal voltage gain, and noise margin vary by a factor of 1.7, 1.2, and 1.7, respectively, between the best and the worst cases.Thus, the proposed low-voltage D-latch shows slightly higher variations than those of the traditional MCML D-latch for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].

Delay Model.
In this section, a delay model of the proposed D-latch is formulated in terms of bias current and the voltage swing.For a low-to-high transition on CLK input that causes output to switch by activating (deactivating) the transistor pair  LV3 - LV4 ( LV5 - LV6 ), the circuit reduces to a simple MCML inverter.The equivalent linear half circuit is shown in Figure 4 where  gd ,  db represent the gate-drain capacitance and the drain-bulk junction capacitance of the th transistor.For NMOS transistors operating in saturation region,  gd is equal to the overlap capacitance  gdo    between the gate and the drain [26].For the transistor operating in linear region,  gd is evaluated as the sum of the overlap capacitance and the intrinsic contribution associated with its channel charge [26].The junction capacitance  db for the transistors is computed as explained in [27].The input capacitance  input represents the input capacitance of the source-coupled pair ( LV5 - LV6 ) [9].
The delay of the proposed D-latch can be expressed as with  db3 =  db5 ,  gd3 =  gd5 and,   = ((1 + )/) ( SWING / SS ); (17) can be rewritten as The capacitances may be expressed in terms of the bias current and the voltage swing as where   is the capacitance between the terminals  and  and   ,   , and   are the associated coefficients.Using ( 14) and ( 15), various capacitances in (18) for  SS ranging from  LOW to  HIGH may be expressed as where  gdo is the drain-gate overlap capacitance per unit transistor width.Consider the following: where   ,  sw are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter, respectively.The coefficients   ,  sw are the voltage equivalence factor for the junction and the sidewall capacitances [27].Parameter  d is extrapolated from design rules [9].Consider the following: where  bulk,max is a parameter defined in BSIM3v3 model [24].Consider the following: where   ,  sw are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter respectively.The coefficients   ,  sw are the voltage equivalence factor for the junction and the sidewall capacitances of the PMOS transistor, respectively [27].
Parameter  d is extrapolated from design rules [9].The coefficients   ,   , and   of all the capacitances in ( 18) are summarized in Table 3.Using ( 20)-( 24), ( 18) can be written as where The accuracy of the delay model for the proposed Dlatch is validated through SPICE simulations by using TSMC 0.18 m CMOS process parameters and with a power supply of 1.1 V.The proposed D-latch was designed for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4, the bias current ranging from 10 A to 100 A,  = 5, and load capacitance of 0 fF, 10 fF, 100 fF, and 1 pF.It is found that there is a close agreement between the simulated and the predicted delay for all the operating conditions.The simulated and the predicted delay in particular for NM = 130 mV and V = 4 and with different load capacitances are plotted in Figure 5.
The impact of parameter variation on proposed lowvoltage and traditional MCML D-latches delay is studied at different design corners.The findings for various operating conditions are given in Table 4.It is found that the propagation delay of the proposed low-voltage D-latch varies by a factor of 1.8 between the best and the worst cases.For the traditional MCML D-latch, the delay varies by a factor of 1.7 between the best and the worst cases.Thus, the proposed low-voltage D-latch shows slightly higher variation than the traditional MCML D-latch in delay for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].

Design Cases
In the previous section, the proposed D-latch has been modeled, and different parameters are expressed as a function of bias current and voltage swing.In practice, the voltage swing is set on the basis of the specified noise margin while the bias current is chosen according to power-delay considerations.Therefore, the proposed low-voltage D-latch for high-speed and power-efficient design cases is discussed.

High-Speed Design.
A high-speed design requires bias current that results in minimum delay.The delay (25) decreases with the increasing  SS and tends to an asymptotic minimum value of 0.69 ((1 + )/)(/ SWING ) for  SS → ∞.A substantial improvement in delay with increasing bias current is achieved if condition is satisfied.However, high value of bias current results in large transistor sizes.Therefore, the bias current should be set to such a value after which the improvement in speed is not significant.If equality sign in ( 27) is considered, then the delay is close to its minimum value, and the use of high bias current is avoided.Therefore, this assumption leads to a bias current ( SS HS ) and delay ( PD MIN ) as The proposed high-speed D-latch, designed with a power supply of 1.1 V, noise margin of 130 mV, small-signal gain of 4,  = 5, and load capacitance of 100 fF, gives  SS HS as 254 A.A delay of 265 ps and 255 ps is obtained from (29) and simulations, respectively.On the contrary, a traditional highspeed D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a delay of 598 ps.This indicates that the proposed D-latch can achieve a much higher speed than the traditional one.A PDP value of 38.5 fJ has been obtained for the proposed Dlatch.On the other hand, a traditional power-efficient D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a PDP value of 24 fJ.The result signifies that the proposed D-latch results in higher PDP values than the traditional one.

Conclusions
A new low-voltage MCML D-latch based on the triple-tail cell concept is proposed.Its static parameters are analytically modeled and are used to develop a design approach for the proposed low-voltage MCML D-latch.The delay is formulated as a function of the bias current and the voltage swing and is traded off with power consumption for high-speed and power-efficient design cases.It is found that the proposed low-voltage D-latch is better than those of the traditional MCML D-latch for the high-speed design case.

Figure 3 :
Figure 3: Errors in the static parameters (a) voltage swing, (b) small-signal voltage gain, and (c) noise margin.

Figure 4 :
Figure 4: Linear half circuit (with low-to-high transition on CLK).
The proposed low-voltage D-latch with differential inputs  and CLK is shown in Figure2.It consists of two triple-tail cells ( LV3 ,  LV4 ,  LV7 ) and ( LV5 ,  LV6 ,  LV8 ) biased by separate current sources of  SS /2 value.The transistors  LV7 and  LV8 are driven by the differential CLK input and are connected between the supply terminal and the common source terminal of transistor pairs  LV3 - LV4 and  LV5 - LV6 , respectively.A high differential CLK voltage turns ON the transistor  LV8 , and deactivates the transistor pair  LV5 - LV6 .At the same time, the transistor  LV7 turns OFF so that the transistor pair  LV3 - LV4 generates the output according to the differential input .Thus, the D-latch works in the transparent state.Similarly, the transistor pair  LV5 - LV6 gets activated for low differential CLK voltage and preserves the previous output.Therefore the D-latch operates in the hold state for low value of the differential CLK input.

Table 1 :
Differential output voltages of the proposed D-latch for various input combinations. −

Table 2 :
Effect of process variation on static parameters of the proposed and the traditional D-latch.

Table 4 :
(25)ct of process variation on the delay of the proposed and the traditional D-latch.V = 4,  SWING = 0.4 V,   = 100 fF, and  SS = 100 A.The delay model can also be used for  SS value outside the range [ LOW ,  HIGH ].This is because for  SS >  HIGH , the capacitance coefficients of PMOS transistor in(25)differ as explained in Section 3.2.But since for high values of  SS , the capacitive contribution of PMOS transistor is negligible, therefore(25)can predict the delay.Similarly, for  SS <  LOW , the capacitance coefficients of NMOS transistor in(25)differ.But since for low values of  SS , the delay majorly depends on the capacitances of PMOS transistor, so expression (25) can estimate the delay of the proposed D-latch.
Design.A power-efficient design requires a bias current that results in minimum power-delay product (PDP).The power is calculated as the product of  DD and  SS .So, the PDP of the proposed D-latch may be expressed as PDP = 0.69  DD  SWING SWING +  +   ) .