Active and Passive Electronic Components
Volume 2016 (2016), Article ID 3741250, 10 pages
http://dx.doi.org/10.1155/2016/3741250

Research Article

Analysis of Random Variation in Subthreshold FGMOSFET

Rawid Banchuin

Department of Computer Engineering, Siam University, 235 Petchakasem Road, Bangkok 10163, Thailand

Received 21 April 2016; Accepted 26 June 2016

Academic Editor: Jinlong Liu

Copyright © 2016 Rawid Banchuin. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

The analysis of random variation in the performance of Floating Gate Metal Oxide Semiconductor Field Effect Transistor (FGMOSFET) which is an often cited semiconductor based electronic device, operated in the subthreshold region defined in terms of its drain current (), has been proposed in this research. is of interest because it is directly measurable and can be the basis for determining the others. All related manufacturing process induced device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using such result, the strategies for minimizing variation in can be found and the analysis of variation in the circuit level parameter of any subthreshold FGMOSFET based circuit can be performed. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit.

1. Introduction

The FGMOSFET in subthreshold region has been found to be an extensively utilized semiconductor based electronic device for low voltage/low power circuits [1–16]. The concept of variability aware design has been applied to such low voltage/low power circuits for handling the effects of the manufacturing process induced device level random variations [6, 10–16]. The examples of these variations are the variation in channel width () and channel length () and so forth. These device level variations affect the circuit level performances of FGMOSFET such as , transconductance (), and drain to source resistance (). Similar to the ordinary Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the subthreshold FGMOSFET is more susceptible to these variations than that in the above-threshold region and has been found to be the key circuit level performance as it is directly measurable and can be the basis for determining the others according to their relationships.

According to the importance of , various analyses of random variation in of the ordinary MOSFET caused by manufacturing process induced device level random variations have been performed in the analytical manner where the subthreshold region operated MOSFET has also been concerned [17–23]. For FGMOSFET, on the other hand, the previous studies have been mostly focused on variations in the circuit level performances of certain FGMOSFET based circuits where subthreshold FGMOSFET based circuits have also been considered [6, 10–12, 15, 23–29]. Unfortunately, the analysis results of these previous researches are applicable only to their dedicated circuits. Moreover, the variability analysis of a single subthreshold FGMOSFET, which is more versatile as it is applicable to any subthreshold FGMOSFET based circuits, has never been performed in any previous work.

Hence, the analysis of random variation in () of subthreshold FGMOSFET caused by manufacturing process induced device level random variations has been proposed in this research. All related device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The obtained analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using the obtained result, the strategies for minimizing can be found and the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit which is an interesting low voltage/low power semiconductor application. In the next section, the overview of FGMOSFET will be addressed followed by the proposed analysis in Section 3. The verification of the analysis result and discussions will be, respectively, given in Sections 4 and 5. Finally, the conclusion will be drawn in Section 6.

2. The Overview of FGMOSFET

FGMOSFET is a special type of MOSFET with an additional gate, namely, floating gate isolated within the oxide. A cross-sectional view of an N-type FGMOSFET with inputs where can be shown as in Figure 1 where the symbol and equivalent circuit are shown in Figure 2. Such equivalent circuit is composed of a MOSFET, input capacitances , overlap capacitance between floating gate and drain (), overlap capacitance between floating gate and source (), and parasitic capacitance between floating gate and substrate ().

Figure 1: A cross-sectional view of N-type, inputs FGMOSFET.

(a)

(b)

Figure 2: The symbol (a) and equivalent circuit model (b) of an N-type, inputs FGMOSFET.

Let and let any th input capacitance be denoted by ; the floating gate voltage, , can be given by

where is the input voltage at any th input gate, is the drain voltage, is the source voltage, and is the bulk voltage. Moreover, stands for the charge stored on the floating gate. Finally, denotes the total capacitance of the floating gate which can be defined as

Let , , , and denote the coupling factor of any th input gate, drain, source, and bulk and be defined as , , , and = , respectively; can be alternatively given as in (3). From either (1) or (3), it can be seen that depends on , , , and :

where denotes charge stored on the floating gate per and is equal to .

3. The Proposed Analysis

By using as given by (3), of the subthreshold region operated FGMOSFET can be given without assuming that for covering the low voltage/low power operating condition which may have very low that invalidates this assumption, as

where , , , and stand for subthreshold specific current which depends on various physical parameters, for example, gate oxide capacitance () and threshold voltage (), subthreshold parameter, drain to source voltage, and thermal voltage, respectively.

Since the variations in (), (), (), (), (), (), (), (), and (), which are related to manufacturing process of the FGMOSFET, contribute of our interest, can be given in terms of its contributors as

where variations in the physical parameters of , for example, those in () and (), have been taken into account by . By using (4), derivatives in (5) can be given by

From (5)–(6), it can be seen that is very mathematically cumbersome. So, it is worthy to look for the alternative manners of analysis, for example, the per-unit based analysis which performs the analysis in terms of the per-unit value of (). By using (4)–(6), can be given as follows:

where ,  ,  ,  ,  ,  /, ,  /, and are the per-unit values of ,  ,  ,  ,  ,  ,  ,  , and , respectively.

Since it has been found that is much more compact than , the per-unit based analysis is preferable and has been chosen for this research. It has also been found that and contribute in the similar directions which are opposite to that of . Finally, the directions of contributions to of , , , , and depend on , , , and whereas that of is solely dependent on the polarity of . As is a random variable similar to its contributors, that is, , , , , , , , , and , it is convenient to analyze its statistical behavior by using its standard deviation as its mean is equal to zero similar to those of the contributors. By taking the statistical correlations of the contributors into account, the standard deviation of () has been found to be given by

where denotes the variance of and . Moreover, denotes the correlation coefficient of and which displays the degree of their statistical correlation; for example, denotes the correlation coefficient of and and displays the degree of their statistical correlation. It can be seen from (8) that the 1st up to the 9th terms of have been solely contributed by each of ’s where the others have been contributed by the statistical correlations based terms. Moreover, by keeping in mind that , , , ,   , , , and are zero mean random variables, can be obtained by using (9) where stands for the expectation operator:

4. Verification of the Analysis Result

The proposed analysis result has been verified at the nanometer level based on the 65 nm level CMOS process technology, two-input FGMOSFET of both N-type and P-type, and SPICE BSIM4 [30] with all necessary SPICE parameters provided by PTM. Since two-input FGMOSFET has been assumed, we let ; that is, and . It should be noted that both and can be arbitrary constants as our device is not in the triode region which is the only region of FGMOSFET that the coupling factors are functions of [31]. So, we let in order to balance the influence of both FGMOSFET inputs. We also let  nm and  nm and also assume that and is extremely small as has been done in many previous works on subthreshold FGMOSFET, for example, [1–3, 6–8, 11, 15]. For making the influences of all device level variations be unbiased, all of such variations have been assumed to be statistically equivalent by letting them be normally distributed with zero means and 1% standard deviations. As a result, such as employs a normal product distribution [32] as the products of the manufacturing process induced device level random variations, for example, , , and , are the product of two normally distributed random variables. Moreover, all ’s have been assumed to be given by 0.5 which is a reasonable estimation [33]. So, each device level variation must be expressed in terms of a weighted sum of its correlated and uncorrelated components which are both normally distributed [33] and have equal weights given by .

In order to perform the verification, the formulated has been compared to its SPICE BSIM4 based reference () obtained by using the Monte-Carlo SPICE simulation with 1000 runs. The SPICE BSIM4 based modelling of FGMOSFET with two inputs can be done by using the two-input version of the equivalent circuit of FGMOSFET in Figure 2 where the core MOSFET has been modelled by using the SPICE BSIM4 and the simulation methodology proposed in [34] has been adopted for solving the convergence problem of the simulator.

As the resulting verification, and have been comparatively plotted against the magnitude of the voltage of the 1st and 2nd input of FGMOSFET denoted by and , respectively. The minimum values of both and are volts and the maximum values have been chosen so that the both N-type and P-type FGMOSFETs operate in the subthreshold region. The comparative plots of and against (where ) of N-type and P-type subthreshold FGMOSFET can be shown in Figure 3 where the similar plots against (where ) are shown in Figure 4.

Figure 3: N-type and P-type subthreshold FGMOSFET based comparative plots against where .

Figure 4: N-type and P-type subthreshold FGMOSFET based comparative plots against where .

From Figures 3 and 4 where and have been, respectively, shown in blue lines and red dots for N-type subthreshold FGMOSFET (green lines and black dots for P-type device), highly strong agreements between and can be observed. Moreover, the average errors of from determined by using the data sets of Figure 3 have been found to be and for N-type and P-type subthreshold FGMOSFET based comparison. On the other hand, such errors determined by using the data sets of Figure 4 have been found to be and for the N-type and P-type device based comparison, respectively. This means that the analysis result is very accurate for both N-type and P-type subthreshold FGMOSFET. If desired, can fit obtained by using the data from more advanced technology node, for example, 45 nm, 32 nm, and 28 nm. For doing so, the optimum parameters of subthreshold MOSFET’s such as , , , and , extracted from the measured of the advanced technology node under consideration by using the optimization algorithm [35], must be adopted.

From Figures 3 and 4, it can be seen that of the subthreshold FGMOSFET of both N-type and P-type grow larger when either or are lowered. This implies that the subthreshold FGMOSFET under very low voltage/low power operating condition is subjected to very large . It can also be seen that both ’s with respect to and of the P-type subthreshold FGMOSFET are lower than those of the N-type device. This means that the P-type device is more robust to the manufacturing process induced device level random variations than its N-type counterpart and has been found to be more preferable. Finally, even though the aforementioned average errors of the P-type device are larger than those of the N-type counterpart, it does not mean that our analysis result is more suitable to the less robust device. This is because the differences in these average errors which are very small as they are less than 0.3% are caused by the differences between the extraction errors of the subthreshold MOSFET’s drain current analytical model parameters from the 65 nm level CMOS technology based drain current data of the N-type and P-type MOSFET.

5. Discussions

Since the subthreshold FGMOSFET under very low voltage/low power operating condition is subjected to very large as stated above, omitting such condition in the designing of those circuits with crucial variability related issues has been found to be a simple strategy to avoid large . However, this strategy is not recommended according to the necessity of such condition for obtaining the low voltage/low power circuit. As a result, the operating condition regardless of strategies for minimizing must be determined. Fortunately, these strategies can be obtained by using our formulated given by (7). From this equation, it can be seen that

Obviously, (10)–(18), respectively, determine the contributions of , , , , , , , , and to . So, minimizing them yields the minimization of . It can be seen that , , and are constant, so, they cannot be minimized by any means. On the other hand, is proportional to , , , , , and are inversely proportional to , and , , , and are proportional to , , and , that is, proportional to , , and . Thus, it can be seen that can be minimized by minimizing , , , and and maximizing . In order to do so, can be minimized by several means such as using UV shining [13] and using a dummy stacked contact [36]. On the other hand, the effects of , , and can be minimized by ensuring that . Moreover, can be maximized by minimizing the oxide capacitance per-unit area between the floating gate and the bulk.

Apart from yielding the above strategies, our is also applicable to the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit in which the formulated given by (8) has been found to be beneficial as well. For performing such analysis, we let the circuit level performance of the subthreshold FGMOSFET based circuit of our interest be ; thus, the random variation in () can be given by

where , , and denote number of FGMOSFETs within the circuit which contribute , , and of any th FGMOSFET which can be determined by using (7), respectively. It can be seen from (19) that can be determined after every has been found.

According to the definition of above, it is a zero mean random variable and so does . As a result, it is convenient to analyze the statistical behavior of by using its standard deviation, that is, . By taking the statistical correlations between each random variation in into account, can be given by (20), where denotes the correlation coefficient of and which are the random variations in and , that is, of any th FGMOSFET where , respectively. Since and are, respectively, of th and th FGMOSFET, they can be determined by using (8). After finding all ’s and ’s, can be obtained:

As a practical example, let be the output current () of the subthreshold FGMOSFET based OTA [11] whose core circuit has been depicted in Figure 5 where () and denote the voltage at the positive (negative) input of the OTA and the supply voltage, respectively. For this OTA, and which have two inputs serve as an input differential pair and the averaging circuit has been included for improving the linearity. According to [11], can be given in terms of of and , that is, and as

Figure 5: The core circuit of the subthreshold FGMOSFET based OTA proposed in [11].

Since the bodies of these FGMOSFETS are grounded and their sources are tied together as shown in Figure 5, we have and . Thus, we can let both and be given by . As a result, and can be, respectively, given by

where ,  ,   , and stand for , , , and of . These coupling factors can be given by

where , , , , and stand for , , , , and of , respectively.

So, the random variation in () can be given by using (19) with as

where both and can be determined by using (7) as they are of and . For determining , we let , , , , , = , , and in (7). For determining on the other hand, we let , , , , , , , and .

Moreover, the standard deviation of () can be obtained by using (20) with as follows:

where and can be determined by using (8) as they are of and . Similar to determining and , we let , , , , , , , and = 0 for determining and let , , , , , , , and for determining . Finally, we can plot against and as shown in Figure 6 where has been expressed in a per-unit basis with respect to the nominal and the magnitude of has been assumed to be 0.5 which implies a reasonable medium degree of correlation between and . From Figure 6, it can be seen that is increased with respect to and . It can also be seen that even small amounts and can induce considerably large . As an example, and , that is, and of 9% and 8% of the nominal ID1 and ID2, respectively, yield which is equivalent to as large as 26% of the nominal . So, it can be seen that the adverse effect of to the performance of subthreshold FGMOSFET based circuits is significant.

Figure 6: The 3D plot of the subthreshold FGMOSFET based OTA versus and .

6. Conclusion

In this research, the analysis of of subthreshold FGMOSFET, which is an often cited semiconductor based electronic device, has been performed. All related device level random variations, that is, , , , , and which cover variations in the physical parameters of , for example, and , , , , and and their statistical correlations, have been taken into account. Moreover, the low voltage/low power operating condition has also been concerned. The obtained result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy where the average error of each verification scenario has been, respectively, found to be 1.6245% (1.8904%) and 1.8244% (1.9518%) for N-type (P-type) subthreshold FGMOSFET.

Based on the proposed analysis result, it has been found that the subthreshold FGMOSFET under low voltage/low power operating condition is subjected to large and the P-type subthreshold FGMOSFET has been found to be a more preferable device as it is more robust to the manufacturing process induced device level random variations than its N-type counterpart. It has also been found that can be minimized by minimizing , , , and , maximizing , and avoiding the extremely low voltage/low power operating condition. The design technics for obtaining minimum , , , and and maximum have been suggested. Moreover, the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done based on the proposed result as illustrated above in which the subthreshold FGMOSFET based OTA has been focused on. So, the result of this research has been found to be beneficial to the variability aware analysis and design of subthreshold FGMOSFET based circuit which is an interesting semiconductor application.

Competing Interests

The author declares that there are no competing interests regarding the publication of this paper.

Acknowledgments

The author would like to acknowledge Mahidol University, Thailand, for the online database service.

References

E. Farshidi, “A systematic design procedure for log-domain filters based on nonlinear transconductance,” in Proceedings of the 2nd International Conference on Signals, Circuits and Systems (SCS '08), pp. 1–5, Monastir, Tunisia, November 2008.

F. Keleş and T. Yildirim, “Low voltage low power neuron circuit design based on subthreshold FGMOS transistor,” Sigma Journal of Engineering and Natural Sciences, vol. 29, pp. 170–177, 2011.

S. Thanapitak, “An 1-V wide-linear-range weak inversion operational transconductance amplifier for low power applications,” in Proceedings of the 21st International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS '13), pp. 497–500, Naha, Japan, November 2013.

J. Alfredsson, S. Aunet, and B. Oelmann, “Basic speed and power properties of digital floating-gate circuits operating in subthreshold,” in Proceedings of the International Conference on Very Large Scale Integration (IFIP VLSI-SOC '05), pp. 229–232, 2005.

E. Rodríguez-Villegas, A. Yúfera, and A. Rueda, “A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 256–259, 2004.

E. Rodriguez-Villegas, A. Yúfera, and A. Rueda, “A 1.25-V micropower -C filter based on FGMOS transistors operating in weak inversion,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 100–111, 2004.

F. Keleş and T. Yildirim, “Low voltage low power neuron circuit design based on subthreshold FGMOS transistors and XOR implementation,” in Proceedings of the 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD '10), pp. 1–5, Gammarth, Tunisia, October 2010.

A. El Mourabit, G.-N. Lu, and P. Pittet, “A low-frequency, sub 1.5-V micropower -C filter based on subthreshold MIFG MOS transistors,” in Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC '05), pp. 331–334, IEEE, Grenoble, France, September 2005.

J. Alfredsson and B. Oelmann, “Capacitance selection for digital floating-gate circuits operating in subthreshold,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '06), pp. 4341–4344, Kos Island, Greece, May 2006.

Y. Zhai and P. A. Abshire, “Adaptive log domain filters for system identification using floating gate transistors,” Analog Integrated Circuits and Signal Processing, vol. 56, no. 1-2, pp. 23–36, 2008.

A. El Mourabit, P. Pittet, and G.-N. Lu, “A wide-linear range subthreshold OTA based on FGMOS transistor,” in Proceedings of the 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS '04), pp. 17–20, IEEE, Tel Aviv, Israel, December 2004.

J. de la Cruz Alejo and L. N. O. Moreno, “Mismatch compensation in current mirrors with FGMOS transistor,” in Proceedings of the 7th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE 2010), pp. 599–603, Tuxtla Gutierrez, Mexico, September 2010.

A. J. Lopez-Martin, J. Ramírez-Angulo, R. G. Carvajal, and L. Acosta, “CMOS transconductors with continuous tuning using FGMOS balanced output current scaling,” IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1313–1323, 2008.

M.-C. J. Antonio, G.-C. Lizeth, and G.-C. Felipe, “Floating-Gate MOSFET parallel analog network for assignment problems,” in Proceedings of the 7th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE '10), pp. 556–559, Tuxtla Gutierrez, Mexico, September 2010.

A. E. Mourabit, P. Pittet, and G.-N. Lu, “A low voltage, highly linear CMOS OTA,” in Proceedings of the 16th International Conference on Microelectronics (ICM '04), pp. 700–703, IEEE, Tunis, Tunisia, December 2004.

G. Lizeth, T. Asai, and M. Motomura, “Application of nonlinear systems for designing low-power logic gates based on stochastic resonance,” Nonlinear Theory and Its Applications, IEICE, vol. 5, no. 4, pp. 445–455, 2014.

P. R. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1212–1224, 2005.

H. Masuda, T. Kida, and S.-I. Ohkawa, “Comprehensive matching characterization of analog CMOS circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 92, no. 4, pp. 966–975, 2009.

W. Lü and L. Sun, “Modeling of current mismatch induced by random dopant fluctuation in nano-MOSFETs,” Journal of Semiconductors, vol. 32, no. 8, Article ID 084003, 5 pages, 2011.

K. Hasegawa, M. Aoki, T. Yamawaki, and S. Tanaka, “Modeling transistor variation using α-power formula and its application to sensitivity analysis on harmonic distortion in differential amplifier,” Analog Integrated Circuits and Signal Processing, vol. 72, no. 3, pp. 605–613, 2012.

L. Vancaillie, F. Silveira, B. Linares-Barranco, T. Serrano-Gotarredona, and D. Flandre, “MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design,” in Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC '03), pp. 671–674, IEEE, Estoril, Portugal, September 2003.

K. Papathanasiou, “A designer's approach to device mismatch: theory, modeling, simulation techniques, scripting, applications and examples,” Analog Integrated Circuits and Signal Processing, vol. 48, no. 2, pp. 95–106, 2006.

S. Vlassis and S. Siskos, “Current-mode non-linear building blocks based on floating-gate transistors,” in Proceedings of the IEEE Internaitonal Symposium on Circuits and Systems, vol. 2, pp. 521–524, Geneva, Switzerland, May 2000.

C. Y. Kwok and H. R. Mehrvarz, “Low voltage and mismatch analysis of quadruple source coupled multi-input floating-gate MOSFET multiplier with offset trimming,” Analog Integrated Circuits and Signal Processing, vol. 26, no. 2, pp. 141–156, 2001.

S. Vlassis and S. Siskos, “Differential-voltage attenuator based on floating-gate MOS transistors and its applications,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 11, pp. 1372–1378, 2001.

S. Vlassis and S. Siskos, “Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 329–341, 2004.

V. S. Babu, A. Sekhar, R. Salini Devi, and M. R. Baiju, “Floating gate MOSFET based operational transconductance amplifier and study of mismatch,” in Proceedings of the 4th IEEE Conference on Industrial Electronics and Applications (ICIEA '09), pp. 127–132, IEEE, Xi'an, China, May 2009.

V. Suresh Babu, R. S. Devi, A. Sekhar, and M. R. Baiju, “FGMOSFET circuit for neuron activation function and its derivative,” in Proceedings of the 4th IEEE Conference on Industrial Electronics and Applications (ICIEA '09), pp. 739–744, IEEE, Xi'an, China, May 2009.

J. Alfredsson and S. Aunet, “Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations,” in Proceedings of the IEEE/IFIP VLSI System on Chip Conference, Rhodes Island, Greece, October 2008.

BSIM4 Manual, http://www-device.eecs.berkeley.edu/

S. K. Saha, “Non-linear coupling voltage of split-gate flash memory cells with additional top coupling gate,” IET Circuits, Devices & Systems, vol. 6, no. 3, pp. 204–210, 2012.

E. W. Weisstein, Normal Product Distribution, Math World-A Wolfram Web Resource, Oxfordshire, UK, 2016.

K. Khu, “Statistical modeling for Monte Carlo simulation using Hspice,” in Proceedings of the Synopsys Users Group Conference, pp. 1–10, San Jose, Calif, USA, 2006.

J. Ramfrez-Angulo, G. Gonzalez-Altamirano, and S. C. Choi, “Modeling multiple-input floating-gate transistors for analog signal processing,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '97), vol. 3, pp. 2020–2023, Hong Kong, June 1997.

P. E. Allen and D. R. Holdberg, CMOS Analog Circuit Design, The Oxford Series in Electrical and Computer Engineering, Oxford University Press, Oxford, UK, 2011.

E. O. Rodríguez-Villegas and H. Barnes, “Solution to trapped charge in FGMOS transistors,” Electronics Letters, vol. 39, no. 19, pp. 1416–1417, 2003.