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The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores. This is achieved by reducing the admittance matrix

At present, there is an ever-greater integration in electronic circuits resulting from grouping in the same card the complex chips with different natures [

The current and voltage of the power source are generally cumbersome. Indeed, they often cannot be directly connected to the transistors presented within the integrated circuits. Thus, the currents will have cross interconnections, the power plans, and the bondings wires before supplying the transistors. All these elements have resistance, pure inductance, and possibly a capacitance. The currents, crossing these elements, will create voltage fluctuations on arrival. This phenomenon is called simultaneous switching noise (SSN). The SSN is due to mutual inductive coupling and interconnections of power delivery networks (PDNs). So, to analyze the SSN, it is necessary to model the behavior of these inductive coupling and interconnections at high frequencies.

In relation to the topic, several papers have discussed the issue of modeling PDNs. Therefore, there are different modeling methods, such as a finite difference time domain (FDTD) method [

One of the most important criteria in the design of PDNs is to ensure safe energy to the circuits when a sudden power occurs. Indeed, the elimination of SSN in multilayer PCB is a critical task in the phase of the design to assure signal integrity. Several methods have been used to reduce the harmful effects of noise transmission, such as integrated capacitors, which are used at high frequencies because of their low inductance [

In [

After the introduction, the second section presents the analysis of the approximation with a rational function. The third deals with a method of vector fitting. The fourth consists in the applications that analyze the effect of the presence of two cores. Finally, conclusions are drawn in the last part.

In general, the power distribution network (PDN) contains many networks of capacitors with several types and different values which allow obtaining the target impedance on the required frequency range of a PCB ground and power plans. So, the design of the PDN interconnections should carry its impedance

Example of PDN impedance versus frequency.

The main objective in the design of the power distribution network is to provide the sufficient current for each transistor of the integrated circuit by ensuring that the power supply noise does not exceed the specified margin. Then, the target impedance

The SSN waveform cannot be calculated directly with

The impedance rational approximation in the frequency domain can be written [

In (

By multiplying (

We note that

Equation (

The calculation of the poles and the residues of the impedance rational approximation in the frequency domain can be achieved by the principle of vector fitting in two steps based on the starting poles. The first step involves the identification of the poles based on (

Equation (

The vector fitting examined the problem of (

The second phase of vector fitting consists of calculating the residues of

The rational approximation with the vector fitting in frequency domain should respect several criteria such as passivity, causality, and stability. The passivity is satisfied when the eigenvalues of Re

With

The first part of (

After having respected these three criteria,

By performing the inverse Laplace transformation, the impedance in the time domain has the following form:

It is clear that the impedance function in the time domain can be easily obtained from the rational approximation in the frequency domain.

Once the impedance function in the time domain is determined from (

For digital signals at GHz, the pulse width of switching current is in the order of 0.1 ns, and the resonance period exceeds 1 ns for typical PDNs [

We assume that the switching current is a triangular periodic signal as indicated in Figure

Switching current waveform.

In real circuit system, the PDN is a multiport system as represented in Figure

Example of PDN with multiport.

So, the SSN of the

Multiple power supply voltages are often used in modern high performance ICs, like microprocessors, to decrease power consumption without affecting circuit speed. To maintain the power distribution network impedance below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy as illustrated in Figure

Cross section diagram of PDN.

In this section, a study of a system with two integrated circuits or cores in the same chip is presented. It comprised two equivalent circuits, one without the ground parasitic circuit return (Figure

Lumped circuit of the PDN with dual supply voltages and two cores without circuit return.

A lumped circuit model of a PDN as depicted in Figure

As already mentioned in the introduction, the model of a PCB can be extracted using different methods, such as FDTD and transmission matrix method.

The PDN is composed of several networks of decoupling capacitor, because no single decoupling capacitor network will provide a low enough inductance. Therefore, the real solution to the high-frequency decoupling problem lies in the use of multiple decoupling capacitors. The number of these capacitors and their type, values, and placement with respect to the IC are important in determining their effectiveness. Many approaches have been proposed such as the use of multiples capacitors all of the same value, the use of multiple capacitors of two different values, and the use of multiple capacitors of many different values, usually spaced a decade apart.

As already said in Section

The values of all resistive, capacitive, and inductive elements of the circuit have been taken from the paper [

The circuit rational function parameters are calculated by the principle of vector fitting. But before this calculation, it is necessary to compute the values of this function in specific range of frequency. Obtaining these values is performed by the reduction method in which all elements of the matrix

The circuit of Figure

So, the circuit admittance matrix

The

The

The matrix

Inserting (

The matrix

After obtaining the reduced admittance matrix, the impedance matrix seen from terminals 1 and 2 is calculated by its inverse. Thus, the noise of the two ports is given by

Figure

SSN analysis methodology.

To make a comparison between the programmed theoretical calculation (VFM + reduction matrix

SSN waveform of the PDN near the first core;

SSN waveform of the PDN near the second core;

The comparison between the results given by our method and PSpice shows first that the vector fitting is very powerful in the calculation of the poles and residues of the rational function that approximates SSN, which is illustrated by the coincidence of the two curves. The results, also, show that the presence of a second active integrated circuit increases the rate of the SSN to core 1, that is shown in Figure

Presently, by changing the value of coupling capacitance chip

SSN waveform of the PDN near the second core;

Lumped circuit of the PDN with dual supply voltages and two cores and with return circuit.

From the results of this section we can conclude that the presence of several integrated circuits in the same chip can increase the fluctuations of the simultaneous switching noise due to the existence of coupling between these circuits.

This second application is for studying and calculating the simultaneous switching noise of the same PDN circuit (Figure

The frequency domain noise of the PDN for

The study was performed again through the study of the effect of the current of the second core and the values of the coupling capacitors between the two cores.

The presence or the absence of the current of the second core has no effect on the SSN at core 1, whereas at the second core while current

SSN waveform of the PDN near the second core;

To study the effect of the coupling capacitance between the PDNs, we keep

For the electrical coupling presented by the capacitance

SSN waveform of the PDN near the second core;

From these results, we can conclude that the addition of ground parasitic circuit influences the form of the SSN precisely at the second core and the fluctuations become more important. We can also conclude that the larger the coupling is beside the two cores, the more important the noise is.

In this paper, a study is made to analyze the simultaneous switching noise in power distribution network with dual supply and two cores. Unlike Ding and Li [

The authors declare that there are no conflicts of interest regarding the publication of this paper.