A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior

In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. (e total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. (e turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.


Introduction
Due to the 60 mV/dec physical limit in subthreshold swing (SS) of conventional MOSFETs at room temperature, it is unrealizable to reduce power consumption by infinitely reducing the supply voltage, which would seriously degrade the circuit performance [1,2]. e tunneling field-effect transistor (TFET) with band-to-band tunneling (BTBT) transport mechanism can achieve steep SS far below 60 mV/ dec [3][4][5][6][7][8]. TFETs are considered as one of the best candidates for the next generation of low-power devices because their manufacturing process is compatible with modern CMOS and FinEFT technology. However, TFETs also face some problems such as low turn-on current and ambipolar behavior [9][10][11][12].
Multigate transistors with strong channel control ability have higher turn-on current than the single-gate ones. It can also effectively suppress short channel effects and reduce leakage current, which has attracted researchers' wide interest. However, most of the current multigate TFETs have only a single input terminal [13][14][15][16]. Previous studies have shown that the double-input TFET has better signal processing ability than the single-input one. For example, the TFET with two symmetric gates can accept two input signals and produce a corresponding output. us, it can implement a Boolean logic function in a single transistor [17][18][19].
In this paper, a new type of TFET with three-input terminals (Ti-TFET) is proposed. e "Majority-Not" logic function can be realized compactly by using Ti-TFET. e invented T-shaped channel (T-channel) enhances the gate control ability on channel potential of any two gates, thus increasing its turn-on current. Taking N-type Ti-TFET as example, the influence of the coupling effect on the potential, energy band, and current density distribution is analyzed.
e results show an interesting feature that a single Ti-TFET exhibits the three-input "Majority-Not" switch behavior and a reconfigurable logic function between NAND and NOR. Device characteristics such as turn-on current, leakage current, and the ratio of turn-on/turn-off current (I on /I off ) are optimized by choosing the appropriate work function and body thickness. e main objective of this paper is to demonstrate a novel TFET technique by taking silicon-based TFET as an example to expand the logic function in a single transistor. In order to obtain an acceptable turn-on current, we select the supply voltage of 1V in this paper. e paper is composed of five sections. Section 2 describes the simulation approaches and main physical models used to model the proposed device in the TCAD environment. Section 3 describes the simulation results, and then the device optimization methods are described in Section 4. e conclusion and summary are included in Section 5.

Device Structure and Simulation Approach
In this section, taking N-type Ti-TFET as an example, the structure and parameters of the device are introduced [20], and then the TCAD simulation models used in this paper are presented. Finally, the fabrication process flow of the Ti-TFET device is explained. e 3D structure of the N-type Ti-TFET is shown in Figure 1(a). e cross section along the center of the Y-Z plane of the device is shown in Figure 1 e special T-shaped channel can be divided into a horizontal channel and a vertical channel. e horizontal channel can be divided into two subchannels: Channel 1 and Channel 2. For convenience, we call the vertical channel, Channel 3. e region in red is the high-k dielectric layer HfO 2 . ree independent-biasing gates, Gate 1, Gate 2, and Gate 3, are deposited and patterned on the surface of the oxide layer. e spacer is used to isolate the gates from the source and drain. e optimized parameters of the Ti-TFET are shown in Table 1.
e doping concentration of heavy P ++ doped source, heavy N ++ doped drain, and the light N-doped channel are 1 × 10 20 cm −3 , 1 × 10 18 cm −3 , and 1 × 10 14 cm −3 , respectively, which ensures the abrupt doping of the sourceto-channel and small leakage tunneling current. e body thickness T Si of the T-shaped channel is set as 5 nm, which ensures that the coupling strength of all the gates on channel potential is large enough. e source length L S , channel length L G , and drain length L D are all selected as 30 nm. e thickness of the High-k dielectric layer is set as 3 nm for appropriate gate capacitance [21]. In order to obtain the required threshold voltage, we use TiN x as the gate material with controllable nitrogen concentration to realize the adjustable work function Φ [22]. e fabrication process flow for a Ti-TFET is detailed in Figure 2. We started from an initial Si wafer, with epitaxial silicon film thinned above 60 nm, and then Gate 1 was deposited and patterned on the oxide layer. After sacrificial oxide layer deposition, molecular bonding on handling oxidized wafer was achieved.
e T-shaped channel was formed by selective etching and chemical mechanical polishing (CMP). Later, Gate 2 and Gate 3 were deposited and patterned on the right and left sides of the T-channel, respectively. Finally, the initial substrate and buried oxide (BOX) were removed chemically.
In this paper, the electronic performance of the proposed device is verified and optimized in the 3D simulation environment with SILVACO TCAD. e Kane BTBT model considering the position-dependent band gap and the magnitude of the electric field is used to describe the carrier transport mechanism. is model is widely used in nanowire and other 3D TFETs [23,24], and its theoretical analysis is in good agreement with the experiments. Along with that Shockley-Read-Hall Recombination models, Band Gap Narrowing Effects, Fermi-Dirac Statistics, and Doping-Dependent Mobility Model are also employed for more accurate simulation results. Since the minimum bulk silicon thickness of the device is 5 nm, quantum confinement effects are considered to calculate the potential, the carrier concentrations, and the discrete subband spectrum of both conduction and valence bands.

The Device Performances
In this section, the current density distribution, current characteristics, and energy band distribution are analyzed. In order to obtain an acceptable turn-on current, we select the supply voltage of 1 V in the simulation.

Current Density Distribution in the Different Switching
States.
e BTBT mainly occurs on the interface between the source and channel. We intercept the contour plots of the current density on this interface, as shown in Figure 3. e greater the current density in the channel, the larger the total current flowing through the channel. ere are three subchannels in the T-shaped channel, and each subchannel has two current paths near the channel surface. erefore, there are six current paths in the entire T-shaped channel.
When V GS1 � V GS2 � V GS3 � 1 V, the current density distribution on the interface between source and channel is shown in Figure 3(a). In this switching state, the coupling effect between all the gates on the three subchannels is the strongest, and maximum drain current flows through both surfaces of all the three subchannels.
When V GS1 � 1 V, V GS2 � 0 V, and V GS3 � 1 V, the coupling effect between Gate 2 and Gate 1 (or Gate 3) is weakened, resulting in the decrease of the control ability on the Channel 1 and Channel 3, so that the currents flowing through Channel 1 and Channel 3 are reduced, as shown in Figure 3(b). In this switching state, since the coupling effect of Gate 1 and Gate 3 on Channel 2 is still strong, a relatively large current still flows through both surfaces of Channel 2.
When V GS1 � 0 V, V GS2 � 1 V, and V GS3 � 1 V, the current density distribution is shown in Figure 3(c). In this switching state, the coupling effect between Gate 1 and Gate 2 (or Gate 3) is weakened, and the control ability on Channel 1 and Channel 2 decreases, but a relatively large current still flows through both surfaces of Channel 3.
When V GS1 � V GS2 � 0 V and V GS3 � 1 V, the current density distribution is shown in Figure 3(d). e channel coupling effect between all three gates is simultaneously reduced. From Figure 3(d), almost no current flows through Channel 1, but Gate 3 is still biased at 1 V, and few carriers flow through the right surface of Channel 3 and the lower surface of Channel 2.
From the above analysis of current density distribution, it can be seen that each gate of the Ti-TFET controls two subchannels. When only one gate is biased at 1 V, this gate has weak control on corresponding subchannels, and thus the corresponding drain current is small. When the bias voltages of the two gates are 1 V, the T-channel structure can generate a strong coupling on the corresponding subchannel, resulting in an exponential increase in drain current. erefore, the proposed T-channel structure allows the device to show the "Majority-Not" switching behavior.

Device Characteristics of Ti-TFETs.
e drain current of the device depends on the gate-to-source voltage (V GS1 , V GS2 , and V GS3 ). In order to analyze the DC characteristics of the Ti-TFETdevice comprehensively, we carry out DC sweep analysis for a gate voltage with the fixed biasing voltage of 1 V or 0 V for the other two gates. Considering the symmetry between Gate 2 and Gate 3, the DC sweep analysis of the Ti-TFET is performed only for Gate 1 and Gate 3. e simulation results of the transfer characteristics (I D -V GS1 and I D -   Figure 4(a) indicates that the DC scan analysis for the gate-to-source voltage V GS1 is performed with V GS2 � 1 V and V GS3 � 0 V, while the mode M 10X shown in Figure 4(b) indicates that the DC scan analysis for the In the modes M X11 and M 11X , the drain current of the device ranges from 1.45 μA to 4.28 μA, and thus the device is turned at all the times of the modes M X11 and M 11X , as shown in the two yellow lines in Figure 4. In modes M 00X and M X00 , the drain current of the device is always less than 1 nA, and thus the device is always turned off, as shown by the two blue curves in Figure 4. In the other four modes, M X01 , M X10 , M 01X , and M 10X , the device changes from turnoff state to turn-on state when the gate-source voltage increases from 0 V to 1 V. When all the three gates are shorted, the transfer characteristics of the N-type Ti-TFET are shown in Figure 4(c). As we can see, the proposed device with shorted gates behaves similar to a conventional N-type TFET with a high threshold voltage.
e Ti-TFET exhibits the minimum subthreshold swing SS (40.78 mV/dec) due to the strong gate coupling, and it has good off-state leakage. Table 2 lists the drain current of the device in eight switching states. Here, logic "1" and logic "0" indicate that the gate-source voltage is 1 V and 0 V, respectively. e drain current of the device is normalized accordingly and listed in the rightmost column of Table 2. From Table 2, the maximum turn-off current of the device is 8.21 × 10 −4 μA, while the minimum turn-on current reaches 1.41 μA. e Ti-TFET exhibits a worst-case switching ratio I on /I off of 1767.

Energy Band Distribution of the Channel Surfaces.
As we can see from Table 2, the strong coupling between all the gates would increase the turn-on current of the device. In order to understand the mechanism of current multiplication caused by the coupling effect, we analyze the energy band distribution of the channel surface in different biasing conditions. Figure 5 shows the energy band diagram and BTBT rate of the Ti-TFET along the top and bottom cut lines (shown in Figure 1 Figure 5 is an enlarged view of the energy band distribution. As shown in Figure 1(a), the top cut line is located at 0.5 nm directly below the HfO 2 layer under Gate 1 along the x-direction. e bottom cut line is in the same plane as the top cut line and located at 0.5 nm above the HfO 2 layer. W1 and W2 are the minimum tunneling widths with the fixed V GS1 � 1 V and V GS1 � 0 V, respectively.
For the energy band distribution on the surface of Channel 2, only V GS1 and V GS3 need to be considered. e four dashed curves in Figure 5(a) represent the conduction and valence energy band along the top cut line and bottom cut line, where V GS1 � 0 V. We found that the energy value of the conduction band in the source region is still lower than that of the valence band in the channel region along the top cut line, and thus BTBT hardly ever occurs in the top region of Channel 2, and BTBT rate is approximately equal to zero.
As we can see from Figure 5(a), the enlarged view along the bottom cut line, the energy value of the conduction band decreases obviously along the bottom cut line, and the tunneling window is opened. erefore, the BTBT occurs in the bottom region of Channel 2 in this biasing condition, the tunneling window is small, and the tunneling distance W2 is relatively large. e BTBT rate increases in the bottom region of Channel 2, but the value is still small so that the tunneling current is relatively small. e energy band distribution curve along the top and bottom cut lines is shown as the solid lines shown in Figure 5(b) with the fixed V GS1 � 1 V and V GS3 � 1 V. From Figure 5(b), as V GS1 becomes 1 V, the coupling on the potential of Channel 2 is enhanced. In the top region of the channel near Gate 1, the curvature of the energy band at the interface between the source and channel increases obviously, and thus BTBT occurs accordingly. Due to the influence of V GS1 , the tunneling width W1 becomes smaller  than W2 and the tunneling window is also larger. erefore, the BTBT rate near the bottom region of the Channel 2 is greatly increased, which leads to a substantial increase in BTBT current in two paths, and thus the device is turned on.

Optimization
In this section, taking the turn-on current I on and switching current ratio I on /I off as the optimization objective, the body thickness T Si and work function Φ, which have the greatest impact on the device performance, are optimized. e turn-on current I on and the switching current ratio I on /I off for different body thickness T Si and work functions Φ are shown in Figure 6(a), and Figure 6(b) is 2D contour plots for better observation. IRDS2020 points out that the turn-on current of a transistor should be at least 1 μA even for lowpower applications. Hence, the switching current ratio should also be more than three orders of magnitude. From Figure 6(b), in order to obtain a large switching current ratio and acceptable turn-on current, T Si could be selected from 5.0 nm to 5.5 nm and Φ from 4.05 eV to 4.10 eV. Figure 7 shows the sensitivities of the transfer characteristics I D -V GS3 to the body thickness variations, where V GS1 � 1 V and V GS2 � 0 V. In Figure 7, I 101 is the turn-on current I on of the device, while I 100 is turn-off current I off . It can be seen that the I off of the device shows a continuous decrease trend as T Si decreases from 9 nm to 5 nm, while an opposite trend can be observed for I on .

Body ickness T Si .
erefore, the reduction in T Si is the most effective method to reduce the leakage current and increase the switching current ratio. It is important to notice that these trends of I on and I on /I off for different work functions are almost the same, as shown in Figure 6. is phenomenon could be well explained by using the energy band distribution and BTBT rate shown in Figure 8, where T Si � 5 nm and T Si � 9 nm. From Figure 8, the device with thin T Si would have small tunneling width and thus obtain the large BTBT rate. erefore, we might draw the conclusion that I on of the device increases with the decrease of the body thickness and thus the better performance.

Work Function Φ.
e relationship between the current characteristics and work function Φ is shown in Figure 9(a), where V GS1 � 1 V, V GS2 � 0 V. It can be seen both turn-on current and turn-off current of the device decrease as the work function is increased. e curve in black in Figure 9(b) represents the turn-on current I on of the device with different work functions. We find that I on shows an exponentially increased trend with the decrease of Φ. e curve in red shown in Figure 9(b) shows the switching current ratio I on /I off as a function of Φ. We find that the ratio of I on /I off decreases rapidly as Φ varies from 4.2 eV to 4.3 eV. From Figure 9(b), we also find that I on /I off decreases rapidly as Φ decreases from 4.1 eV to 3.8 eV.
is phenomenon could be well explained by using the energy band distribution and BTBT rate with different work functions (Φ varies from 3.8 eV to 4.2 eV) in the turn-off state, as shown in Figure 10. When Φ > 4.2 eV, the conduction band energy of the channel region was still higher Active and Passive Electronic Components 5 than the valence band energy of the source region. us, the BTBT does not occur, so that device is not yet turned on, and the turn-off current (I 100 ) of the device is very small. erefore, when Φ > 4.2 eV, I on /I off decreases rapidly because of rapidly decreased I on .
When Φ decreases to 4.1 eV, the tunneling window is turned on nearly, and BTBT rate begins to occur also, as shown in Figure 10, so that the turn-off current I 100 increases quickly, but the BTBT rate is not large enough. As Φ continues to decrease, the tunneling window is fully open, so that the leakage current I 100 increases rapidly. erefore, when Φ decreases from 4.1 eV to 3.8 eV, I on /I off decreases rapidly because of rapidly increased I off rather than I on .
From the above analysis, we can see that the device with Φ � 4.1 eV is at a near turn-on state when V GS1 � 1 V, V GS2 � V GS3 � 0 V. In this case, once a small biasing voltage is applied to Gate 3 or Gate 2, the tunneling current would increase rapidly, so that the proposed Ti-TEFT would be Table 2: e turn-on and turn-off currents of the N-type Ti-TFET device.    turned on when two or more input terminals are biased with high level.

Logic Cells
e "Majority-Not" circuit is a fundamental logic cell that can be widely used to implement efficiently complex logic circuits. e truth table of the three-input "Majority-Not" is shown in Figure 11(a). e traditional "Majority-Not" cell using static complementary CMOS logic is shown in Figure 11(b). Another realization of the "Majority-Not" cell using a reconfigurable logic function with NAND and NOR along with a MUX is shown in Figure 11(c). Since a single N-type Ti-TFET exhibits the three-input "Majority-Not" switching behavior, only one N-type and one P-type Ti-TFET can be used to compactly implement the "Majority-Not" logic cells, as shown in Figure 11(d). Compared with the two traditional 10-T "Majority-Not" logic cells, the "Majority-Not" logic cell using Ti-TFETs can effectively reduce the number of transistors and stack height.
e power consumption and power delay product of the static complementary Majority-Not cell using 7 nm FinFETs [25], 20 nm AlGaSb/InAs single-gate TFETs [26] Ti-TFETs are compared in Table 3. e power consumption and power delay product of the Majority-Not logic gate based on Ti-TFETs are smaller than FinFET devices and single-gate TFETs with an acceptable delay penalty.
e power consumption of each transistor is about 6 nW for the 7 nm FinFET, 4.9 nW for the single-       erefore, reduced power is due to both TFET operation and the multigate transistor architecture.

Conclusion
is paper has proposed a new type of TFET with tri-input terminals, and the objective of this paper is to demonstrate a technique to expand the logic function in a single transistor and reduce transistor count in circuits. e proposed Ti-TFET has been optimized by selecting the channel structure, body thickness, and work function. We also highlight the fabrication guidelines for Ti-TFETs. e special T-channel structure enhances the channel coupling of any two gates, and thus drain current can exponentially increase. Since the Ti-TFET exhibits the three-input Majority-like switching behavior, the proposed devices can provide a new perspective for further application of different types of TFETs to realize the compact logic circuits.

Data Availability
e data used to support the findings of this study are available from the corresponding author upon request.

Disclosure
An earlier version of this paper was presented at the 20th IEEE Conference on Nanotechnology with 4 pages [20]. Now, the authors significantly expand the previous conference version to contain substantial new technical material, and the content has also expanded by more than 70%.

Conflicts of Interest
e authors declare that there are no conflicts of interest regarding the publication of this paper.