Analysis and Design of High-Energy-Efficiency Amplifiers for Delta-Sigma Modulators

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Introduction
With the outbreak of the Internet of things (IoT) sensing application market, analog-to-digital converters (ADCs) are the current research hotspot, especially high-energyefciency ADCs with high precision and high dynamic input swing.Diferent from bias low-power applications of SAR ADC [1] and towards the high-speed application of fash ADC [2], delta-sigma ADC is an excellent choice for energyefcient ADCs because of its inherent high energy efciency within the common bandwidth of the IoT.
Te delta-sigma modulators are the main part of the delta-sigma ADCs.Amplifers belong to the design core of the integrator in delta-sigma modulators, and their performance dominates the performance of the whole deltasigma modulator.Terefore, high-energy-efciency amplifers have been a research hotspot in recent years.An inverter amplifer was proposed in [3] to achieve current reuse and large output swing.However, the gain was generally limited to about 30 dB and sensitive to the process, voltage, and temperature (PVT).In [4], a cascode inverter was proposed to achieve gain greater than 50 dB at the expense of swing, and it was still sensitive to PVT.A current-starved amplifer that adds a fxed current bias to combat PVT robustness but at the expense of swing was proposed in [5].A dynamic bias amplifer which requires a complex common-mode (CM) feedback circuit was proposed in [6], increasing the design complexity and power consumption.A foating-inverter amplifer (FIA) and its application were proposed in [7,8], which represents the highest energy efciency level of the current amplifer design and has relatively good PVT robustness, but its gain was generally limited to about 30 dB.In [9], a cascode FIA was proposed to obtain a moderate gain by sacrifcing a certain swing.A cascaded FIA was proposed in [10] to obtain a moderate gain and large output swing at the expense of power consumption.In some high precision and high-dynamic-range delta-sigma modulator applications, a medium gain may still not be sufcient.In addition, some gain-insensitive techniques have been proposed, such as correlated level shifting (CLS) [11,12], averaging correlated level shifting (ACLS) [13], dynamic body-biasing (DBB)-assisted CLS [14], and a CLS technique with ping-pong operation [15]; they have been widely used in recent years but at the expense of area and clock circuit power consumption.In this study, the existing FIA techniques were analyzed and summarized in detail and a high-gain FIA scheme was proposed, which has a better tradeof between power consumption and stability.
Section 2 introduces the working principle of an FIA.In Section 3, in-depth analysis compares several structures with simulation verifcation.Section 4 introduces the high-gain FIA proposed in this study, and the simulation results and conclusions are given in Section 5.

Floating-Inverter Amplifier (FIA)
With the increasing demand for high-energy-efciency amplifers, researchers have made progress in the structural innovation of amplifers year by year.Te structure of the FIA was frst proposed in [7], as shown in Figure 1.Its working process is divided into two stages: reset and amplifcation.In the reset stage, the energy storage capacitor (C RES ) is charged, while in the amplifcation stage, the amplifer is powered by the C RES .In implementing current reuse at the same time, g m /I d increases as the overdrive voltage decreases in the amplifcation stage.Because of its high energy efciency, it is widely used in some low-power applications.
Because of the particularity of the FIA's working principle, the C RES will discharge continuously in the amplifcation stage, indicating that the power supply voltage of the amplifer keeps decreasing over time.Finally, the FIA will stop working when the voltage on the capacitor (V RES ) is less than the sum of the MOSFET threshold voltages (V THN + V THP ) between the power and ground paths.At this time, the current of the amplifer is close to zero.Tis feature of the FIA is referred to as the self-quenched mechanism in [7].Tis mechanism provides the amplifer extremely strong stability, and its open-loop gain has very low sensitivity to dynamic errors such as clock jitter.Compared with traditional closed-loop static amplifers, the FIA does not need an additional CM compensation circuit because the FIA is powered by an C RES .According to Kirchhof's current law, the input and output currents of the C RES must be equal, so there is no need for a complex CM feedback circuit [10].

Analysis and Simulation of Traditional FIA
and Improved Amplifiers Based on the FIA where where T s is a working period of FIA and G m,0,si is the transconductance of the MOSFET working in the strong inversion at the beginning of the amplifcation phase [7].If the C RES is large enough, τ 0,si ≫ T s /2, then the amplifer will behave as if it were powered by an ideal voltage source, where the average small signal transconductance G m,avg,si ≈ 2G m,0,si .However, the C RES in the actual circuit cannot be infnite, so with the continuous discharge of the C RES , MOSFETs will work in the weak inversion for a period of time before switching of, and the expression of the FIA average transconductance is as follows: which is assumed that the FIA working time in the strong inversion area is much longer than that in the weak inversion area [7].Te above analysis applies to simple FIA and cascode FIA, where the small signal transconductance of FIA architecture as an amplifer is not a constant.Diferent from traditional amplifers, due to the characteristics of FIAs' C RES power supply, the working current of FIA will continue to decrease with the discharge of C RES , resulting in an increase in the output impedance of MOSFETs and a decrease in the pole frequency of FIA.As a result, the simulation results of the gain over frequency and phase over frequency of FIA cannot well refect the performance of FIA.In this paper, the variation trend of unity-gain bandwidth (UGB) and phase margin (PM) over time is adopted to represent the working state of these FIA-based amplifer structures.Te simulation results of the low-gain and large-swing FIA are shown in Figures 2 and 3. 2 Active and Passive Electronic Components According to [9], the input-referred in-band noise of the structure is v 2 n,i ≈ kT/C in .At the same time, the unity-feedback structure mentioned in [9] was used, as shown in Figure 4.At a sampling frequency of 128 kHz and a bandwidth of 0.5 kHz, transient noise was added to obtain the normalized equivalent input noise, as shown in Figure 5, and the sigma value was about −93.40 dB.For the sake of simplicity, the later noise analysis was performed under this condition.

Medium-Gain and
Small-Swing FIA.Te closed-loop direct current (DC) gain of the integrator using a simple FIA can only reach about 30 dB in general, which is not suitable for high-precision delta-sigma modulator applications.Terefore, an improved FIA with a higher gain has been reported, whose structure was proposed in [9].Te circuit structure is shown in Figure 6.Because of the high output impedance of the cascode structure, a higher gain A V � (G m R o ) 2 is achieved, which can generally reach more than 60 dB, but it requires additional bias voltage or MOSFETs with diferent size ratios.At the same time, because of the cascode structure, the output swing is limited, making the structure only suitable for some applications with a medium gain and low output swing.Because the high output impedance of the cascode structure yields a high gain and the UGB of the unipolar system is mainly related to the current, the change in the pole frequency caused by the discharge of the same size, the C RES has little efect on the PM.From the simulation results in Figures 7 and 8, the UGB of the proposed structure is similar to that of the structure in Figure 1, while the PM slightly changes.According to [9], the input-referred in-band noise of this structure is similar to that of the structure in Figure 1.Te transient noise simulation results of this structure are shown in Figure 9, and the sigma value is about −93.34 dB.Te simulation proves that the input-referred in-band noises of the two structures are basically similar under the same energy storage capacitance.

Cascaded Medium-Gain and Large-Swing FIA.
Although the cascode FIA has a medium gain, it sacrifces part of the output swing.To solve the contradiction between the single-stage FIA gain and output swing, a cascaded structure of the simple FIA was proposed in [10], as shown in Figure 10.Sufcient output swing can be guaranteed for the amplifer when cascaded gain of a two-stage simple FIA is achieved.
Its working process can be divided into reset and amplifcation stages.First, in the reset stage (V1 � 1 and V2 � 0), the input and output voltages of the amplifer are reset to the CM voltage V CM .At the same time, the C RES starts precharging and quickly charges to the power supply voltage to prepare for the dynamic amplifcation of the next phase.With diameters of V1 � 0 and V2 � 1 in the amplifcation stage, the upper and lower plates of the C RES are connected to the power supply track of the amplifer so that the amplifer can be started to work.Because the output CM voltage will be reset back to the CM voltage at the beginning of each cycle and the enabled switch timing of the two stages of the amplifer is the same, the closed-loop amplifcation function is realized.Te structure consumes more power and area to achieve a medium gain.
Te equivalent noise model of the two-stage amplifer based on the FIA is shown in Figure 11.According to the analysis in [10], the equivalent input-referred in-band noise expression of this structure is Because the C RES of the second stage is designed to be smaller than that of the frst stage, the noise factor will gradually decrease as the working current of the second stage decreases faster, so the amplifcation efect of the noise factor G m2 R O1 on the input-referred in-band noise of the frst stage will also gradually decrease.Active and Passive Electronic Components According to (2), compared with the single-stage FIA input noise analyzed earlier, the cascaded FIA input-referred in-band noise generated by the frst-stage amplifer is amplifed by the noise factor G m2 R O1 , so the noise performance will be decreased.
As shown in Figure 12, the sigma value of the structure is about −87.06 dB.Compared with the simulation results earlier, the noise performance of the two-stage FIA will decrease signifcantly, which is consistent with the theoretical analysis.

Cascaded High-Gain and High-Input-Range FIA.
Although the two structures shown in Figures 6 and 10 achieve a closed-loop DC gain of greater than about 60 dB, it is still not enough to meet the design requirements of some applications with high precision and high dynamic range.To achieve a greater gain, an improved two-stage amplifer based on the FIA was proposed in [16], as shown in Figure 13.Te frst stage adopts the cascode FIA, and the second stage still uses a simple FIA, which achieves a high gain and still has a large output swing, but the structure is analyzed according to (2).Te high output impedance of the frst stage provided by the cascode structure will increase the noise factor G m2 R O1 .As a result, the noise performance of the structure is greatly sacrifced.At the same time, due to the large output load capacitance and the high output impedance of the frst stage, it is necessary to add an additional compensation capacitor at the output of the frst stage for the stable operation of the circuit.Tis structure does not have the condition of a single variable, so this study does not conduct in-depth analysis and simulation of this structure.

Two-Stage High-Gain FIA
For cascade integrators with a feedforward structure commonly used in delta-sigma ADCs, due to the input feedforward path and the dynamic range scaling of the integrator outputs [9], the structure does not require a high integrator output swing but a high amplifer gain in applications with high precision and high dynamic range.On the basis of this application scenario, in this study, a novel two-stage amplifer based on the FIA structure was proposed, as shown in Figure 14.Te cascode structure was used in the second stage, which has a larger output impedance and makes the amplifer have a high gain.Te operating principle is the same as that of the two-stage closed-loop amplifer shown in Figure 1.
Te unity-gain integrator (C S � C F ) was constructed with a switching capacitor, as shown in Figure 15.Simulation tests of the DC gain and output range were conducted when the power supply voltage was 1.2 V. Te DC gain simulation results of the integrators with diferent structures at varying output voltage under the same energy storage capacitance are shown in Figure 16.Te simulation results are consistent with the DC gain and output range of the three structures in the above analysis.A simple FIA and a twostage FIA are appropriate for large-input-swing applications.Te proposed FIA + cascode FIA is the most appropriate when the demand for a high gain and high dynamic range is high, and the output swing of the integrator is not high.
Te new amplifer proposed in this paper has the same working principle as several structures mentioned above, and the relationship between its small signal transconductance and energy storage capacitance is still complex with the derivation mentioned above, so it will not be Figure 13: Two-stage high-gain FIA structure with a compensation capacitor.Active and Passive Electronic Components repeated here.Since the two-stage amplifer is enabled at the same time, a negative feedback circuit can be introduced to form a closed-loop amplifer and realize the function of closed-loop amplifcation.Te signal change process of the closed-loop amplifer is shown in Figure 17.
For a two-stage dynamic amplifer, stability must be considered.In a traditional two-pole system, to obtain a sufcient PM, the frequency of the nondominant pole is often designed to be more than twice that of the UGB, increasing power consumption.Te two-stage dynamic Figure 16: DC gain varying with output voltage (inverter: the structure in Figure 1, cascode: the structure in Figure 6, inverter and inverter: the structure in Figure 10, and inverter and cascode: the structure in Figure 14).amplifer proposed in this study is also a two-pole system.Te two poles are the output nodes of the frst and second stages of the operational amplifer, but the amplifer designed in this study can work stably without an additional compensation capacitance.
According to the analysis of the pole frequency of the two-stage FIA in [10], the pole frequency is f � 1/R o C o , where C o is the output load capacitance and R o is the output impedance; the output impedance of a MOSFET is r o � zV ds /zI ds � 1/g ds .According to the equivalent output impedance analysis diagram of the frst and second stages shown in Figure 18, the output impedance of the frst stage is expressed as R O,1 � 1/(g ds,p + g ds,n ), while that of the second stage is expressed as follows: where g m,p2 and g m,n2 are the equivalent transconductance of common-gate PMOS and NMOS, respectively.At the same time, because of the large output load capacitance of the second stage, the second-stage output pole must be the dominant pole.Diferent from traditional amplifers, because the C RES of the FIA will discharge in the amplifcation stage, the current in the amplifer will decrease with time, resulting in increasing output impedance, which will lead to the change in pole frequency.Terefore, the C RES of the second-stage FIA was designed to be smaller than that of the frst-stage FIA (C RES1 � 33 pF and C RES2 � 6 pF), making the discharge rate of the second-stage amplifer higher, and the frequency variation of the dominant pole was greater than that of the nondominant pole, thus increasing the PM; thus, the amplifer can work stably without the need of an additional compensation circuit.
From Figures 19 and 20, the UGB of the amplifer starts from 900 MHz, indicating that the C RES provides a great working current to the amplifer at the beginning of the amplifcation stage.Later, as the C RES continues to discharge over time, the current keeps decreasing, so the UGB gradually decreases.As the C RES of the frst stage is larger than that of the second stage, the frequency of the dominant pole decreases faster than that of the nondominant pole.Te initial PM is 33 °and the fnal PM is close to 87 °, showing that the output waveform of the closed-loop amplifer will oscillate at the beginning of the amplifcation stage but will stabilize over time.
According to the above analysis, diferent from the structure in Figure 13, the design structure proposed in this study does not need to introduce a compensation capacitance to stabilize the system due to its advantages in structural design, making the design simpler.
Te simulation results of the input-referred in-band noise are shown in Figure 21.Te sigma value is about −87.29 dB.As the input noise analysis of the cascaded-type FIA and single-stage FIA mentioned earlier shows, the input-referred in-band noise of the structure is similar to that of the structure in Figure 10, indicating that the structure does not need to sacrifce the noise performance of the amplifer when it achieves a high gain, which is also proven by the simulation results.According to the above analysis and actual simulation, the noise performance of the single-stage FIA is better than that of the two-stage FIA.For delta-sigma ADC, we usually only focus on the noise energy in its low frequency passband.Terefore, in order to suppress the ficker noise of the amplifer at low frequency and further improve the noise performance of the integrator [17], the half the sampling frequency chopper switching circuit is introduced to test the circuit as shown in Figure 22.By adding the chopper switching circuit, the ficker noise at the low frequency is moved out of the frequency passband that we care about, thus reducing the in-band noise energy that we care about.
Te noise of the proposed two-stage dynamic amplifer was tested, and the normal distribution of the input-referred in-band noise was obtained after adding the chopper circuit.
Te noise analysis and simulation results obtained after adding chopper switches to diferent structures when the C RES s are the same are shown in Figures 23-26.Te sigma value of the noise after adding the single-stage FIA chopper increases by about 8 dB, and that of the input noise after adding the structure chopper in Figure 10 increases by about 6 dB.
In the cascaded high-gain FIA circuit proposed in this study, one sigma of the input-referred in-band noise after adding the chopper was about −100.26 dB, which increased to about 12 dB.Because of the structural characteristics of the cascaded high-gain FIA proposed in this study, the size of the input MOSFETs of the frst-stage amplifer in the actual design is smaller than that of the second-stage amplifer, as shown in Figure 10.
Terefore, the transconductance of the second-stage amplifer designed in this study will be smaller than that Active and Passive Electronic Components   Active and Passive Electronic Components Active and Passive Electronic Components of the second-stage amplifer of the circuit in Figure 10.According to (2), the noise amplifcation factor of the structure proposed in this study will be smaller than that of the circuit in Figure 10, so the chopper efect is better than that of the circuit in Figure 10.

Conclusion
FIA is an excellent representative of high-energy-efciency amplifers in recent years, and ADC innovative designs based on this structure are constantly emerging.However, there is still no relatively perfect basic analysis and research on FIA and its improved structure.
In this paper, the existing FIA structure and its improved amplifer are analyzed and simulated in detail from the aspects of gain, swing, stability, and noise.Te results are shown in Table 1.Te conclusions are as follows: single-stage FIA is more suitable for low-noise applications, while for high-precision applications with a high input dynamic range, two-stage FIA has obvious advantages of high gain.
It can be seen that the SC integrator using the new amplifer proposed in this paper has a greater closed-loop Table 1: FIA structure and performance comparison between the improved amplifers.

Data Availability
Te data used to support the fndings of this study are available from the corresponding author upon request.

Figure 3 :
Figure 3: Time varying PM of the simple FIA structure.

Figure 5 :Figure 6 :
Figure 5: Histogram of the normal distribution of the input noise of the FIA (Number: number of simulations, Mean: mean value, Std: standard deviation, Median: median value, Var: variance, and Mean: mean value).

Figure 9 :
Figure 9: Histogram of the normal distribution of the input noise of the cascode FIA.

Figure 17 :
Figure 17: Equivalent single-ended AC model with negative feedback.

Figure 20 :Figure 21 :
Figure 20: Time varying PM of the proposed two-stage FIA structure.

Figure 25 :
Figure 25: Input noise of the circuit in Figure 10 with a chopper.
Figure 2: Time varying UBG of the simple FIA structure.
Figure 7: Time varying UBG of the cascode FIA structure.
Figure 19: Time varying UBG of the proposed two-stage FIA structure.
DC gain and excellent noise performance and is suitable for the design of delta-sigma ADC with high precision and high input dynamic range.Te SC integrator based on the amplifer is designed and verifed by the SMIC 180 nm CMOS process under a power supply voltage of 1.2 V.