Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell

. Tis work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. Te performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully diferential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). Te proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. Te built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and V DD collapse. Te impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and V DD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. Te impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. Te deviation of HSNM for 15 ° C to 55 ° C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. Te proposed SRAM cell is designed at a 22nm CMOS technology node and verifed in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.


Introduction
An SRAM cell is typically designed using nanoscale transistors to achieve a high integration density. As a result, SRAM's stability and write capabilities continuously deteriorate, and achieving a suitable yield with planar bulk metal-oxide semiconductors in 22-nm technology and beyond is extremely difcult [1].
Te construction of a conventional 6T SRAM cell is quite simple. But the read and write stability of 6T SRAM has decreased due to increased threshold voltage fuctuations brought on by global and local process changes in modern CMOS processes. Te major feld of research for creating cutting-edge memory applications on chip SOC has long been energy-efcient and fast-accessing memory cell architectural design. Particularly, in military and aerospace applications, accurate memory operations are expected to be performed across a variety of temperature and resource limitations. Low power consumption and quick memory access are the two most important requirements for such applications [2]. Fast read and write operations are indeed critical factors in designing memory, and in this aspect, write assist circuits should be included in memory architecture. But it leads to area overhead. Te area overhead is reduced by proper cell design with an in-built assist circuit to improve the access speed. Te proposed BSRWA 10T SRAM cell is designed by taking reference from a shared-pass-gate 11T [3], low standby power 10T (LP10T) [4], energy-efcient single-ended 10T (SE10T) [5] SRAM cells. Te second criteria of designing the cell are the handling capability of half-select write failure issues. Half-select write failure issue occurs when a neighboring memory cell is unintentionally programmed along with the target cell. Tis can result in errors and data corruption, especially in highdensity memory arrays. Te proposed BSRWA 10T SRAM cell is proposed with proper design with a bit of interleaving structure to mitigate this issue.
ST-based inverter-structured SRAM cell is strong in terms of holding the data. Te high HSNM cell structure of ST SRAM faces an issue with write ability. Write margin of SRAM cell needs to be improved along with HSNM and RSNM improvement. Te performance improvement by the proposed SRAM is explained clearly using all circuit parameters such as read static noise margin, hold static noise margin, write margin, write trip current, write tip voltage, and data retention voltage. Te data retention voltage parameter was extracted through HSNM plots.
Tis paper is organized as follows. Te proposed built-in self-read and write assist 10T (BSRWA 10T) SRAM cell design and comparison with previous SRAM cell's operation are observed in Section 2. Write performance analysis of proposed BSRWA 10T, improvement of WM, write accessing speed, and thermal stability using MC simulations are observed in Section 3.

Proposed Built-In Self-Read and Write Assist 10T (BSRWA 10T) SRAM Cell Design and Comparison with Previous SRAM Cell's Operation
Tis section is organized as follows: read operation of BSRWA and stability analysis, which is compared by previous SRAM cells as shown in Section 2.1 [6,7], hold operation of BSRWA and hold stability analysis, which is compared by previous SRAM cells as shown in Section 2.2 [8,9], about write operation and write ability of proposed SRAM cell comparison with previous cells as shown in Section 2.3 [10,11].

Proposed BSRWA 10T SRAM Cell's Read Mode of
Operation. In advanced technology nodes, data retention of the memory cell is a crucial functional constraint during read access. Lowering the supply voltage in the advanced technology nodes makes the memory cell less stable. Here, read SNM (RSNM) as a design metric is considered for stability analysis of memory cell operated in read mode. Read stability analysis for conventional, FD 10T-ST [12], SSDF 9T-ST, and proposed BSRWA 10T SRAM cells is performed. SRAM cells with high read stability can withstand the read disturbance. So read stability through "RSNM" is calculated by the SNM test model. SNM test model is created by updating the cell with two to four memory nodes (D, Db to D, Db, Db, Ddb) by breaking the feedback loop. Ten, DC voltage transfer curves are plotted by keeping noise sources. Figure 1(a) illustrates the read operation of the conventional memory cell, precharged BIT, and BITB lines able to disturb the core memory cell (D, Db) during an active WL signal. Te read disturbance (∆v) is analyzed with the adjustment of cell ratio and observed as "∆v ′ " is brought to minimum through maximizing cell ratio. So pull-down transistor (MPDL) with maximum size may protect the cell from read disturbance, but it has a penalty as a write failure [13] and consuming area. Figure 1(b) illustrates the read operation of the FD 10T-ST SRAM cell [12]; here, cell confguration focuses on stabilizing the inverter pair to withstand the read disturbance [12]. ST inverters have 2 levels of switching thresholds, and feedback transistors (MFBL, MFBR) attached to increase the switching threshold range for each inverter, which can improve the cell read stability. But "∆v ′ " can make MFBL conducts to a stacked node, which will reduce the conducting capacity of the stacked pull-down transistor. So chances of cell getting disturbed are more, which is strongly justifed by the simulation shown in Figure 1(b). It is observed from VTC that they are not touching level-"0" when node-Db is maintained at a high level. Figure 1(c) illustrates the read operation of the SSDF 9T-ST SRAM cell [14], and when the word line is active, precharged bit lines can disturb the core cell by accessing the transistor (MAXL). Te strength of read disturbance (∆v) should not cross the level of the trip voltage; otherwise, read failure is caused. SSDF 9T-ST SRAM cell confguration has one stacked conventional inverter and another ST inverter with a high switching threshold connected in a regenerative loop. Figure 1(c) illustrates the RSNM histogram for the proposed memory cell and corresponding butterfy curves (VTC of cross-coupled inverters). It is observed that node-D is strongly pulled to ground with transfer curves touches level-"0" when node-Db is maintained at a high level. So read failure is minimum in this proposed cell, which is also justifed through the simulation result of the RSNM histogram shown in Figure 1(c). Te Schmitt-Trigger (ST) inverter has enhanced the read stability of the FD 10T-ST [12] and SSDF 9T-ST SRAM cells. Te proposed BSRWA 10T SRAM cell has better read stability when compared to the conventional, FD 10T-ST, SSDF 9T-ST. Tis is due to the following reasons. Figure 1(d) illustrates the read operation of the proposed BSRWA 10T SRAM cell. WL is active, and the BIT line is precharged to "V DD " as per the test bench setup for a read operation from the core memory cell. Te precharged bit line does not disturb the node-SD through MAXR, M NR1 when it holds "1." But in the case of node-SDb holds "0," the strength of "∆v" depends on "ON" resistance of M NR1 . "∆v" may disturb the memory cell in the conventional structure, but build-in self-read assist in the proposed memory cell has strong pull-down mechanism through M NR2 when M NR1 ofers high "on" resistance in the worst case. So node-D is strongly pulled down to logic level-0 which strongly holds the SD node also at logic level-0 through the feedback network. Node-D (at level-0) holds the node SDb at logic level-1. So pull-up network becomes very weak (M PRS is of) to boost the node-SD; simultaneously, node-Db also makes the pull-down strong. So the read disturbance is reduced by read assist cell architecture.
Histogram  HSNM under super threshold (V DD � 0.6 V) and nearthreshold (V DD � 0.4 V) is observed as supply voltage reduces hold stability is reduced. Tis feature of varying HSNM with supply operating voltage is used for the fast write operation. Tis concept is explained in Section 3.

Proposed BSRWA 10T SRAM Cell's Write Mode of
Operation. Write operation is performed for conventional, FD 10-ST, SSDF 9T-STmemory cells. Memory nodes of each memory cell are updated with write data during the write operation. Ultradynamic voltage scaling (U-DVS), negative bit line (NBL) [15], and write assist combining negative BL and V DD collapse [16] circuits are designed to improve the write performance. Write operation for SSDF 9T-ST SRAM cell using write assist combining negative BL and V DD collapse is shown in Figure 4. Te control signals are Colgen, Boost1, and Boost2 are generated at the architecture level throughout row and column by row and a column address decoder. Supply scaling and negative bit line mechanisms are introduced during the write operation. Transistors (P1, P2, N1, N2, N3) are turned "on" and "of" by control signals in the assist circuit to provide a scaled supply voltage (V COL ) to reduce the stability, and simultaneously, the assist circuit is also provided negative bit line voltage to increase the driving strength of accessing transistor Te write performance of the previous SSDF 9T-ST SRAM cell is improved by the assist circuit as shown in Figure 4 [17]. But generating controlling signals (colgen, boost1, boost2) by the external circuit is becoming complex. Te proposed BSRWA 10T SRAM cell, by virtue of its integrated self-write assist feature, can enhance write performance on its own. Tus, the overhead of the external write assist circuit and control signals is optimized. Figure 5(a) illustrates the write-"0" operation of the proposed BSRWA 10T SRAM cell.
Enabling WL, WWL, and WBLB with logic-"1" and BL with logic-"0" are the initial conditions for performing the write-"0" operation. Active WBLB tries to bring the node-Db to a high level, which turns of the M PR . So node-D discharges freely and strongly pulled down through M NR2 without having any disturbance from the charging path. Strongly pulled-down node-D turns M PL1 on and generates strong logic-1 at node-SDb. Te strong logic-1 at SDb turns of the M PRS , so node-SD discharges freely and is strongly pulled down through M NR1 without any disturbance from the charging path. So memory node (D) and stacked memory node (SD) are written with logic-0. Similarly, enabling WL, WWL, and BL with logic-"1" and WBLB with logic-"0" are the initial conditions for performing the write-"1" operation. Active low WBLB tries to bring the node-Db to the low level, which turns on the MPR and turns of the M NR1 . So node-D charges freely and strongly pulled up through MPR without having any disturbance from discharging path through M NR1 and M NR2 . Node-D at logic-"1" turns M NL1 on and generates strong logic-0 at node-SDb. Te strong logic-0 at SDb turns on the MPRS, so node-SD is also pulled down through MPRS. So memory node (D) and stacked memory node (SD) are written with logic-1. Figure 5(b) illustrates the write-"1" operation of the proposed BSRWA 10T SRAM cell. Enabling WL, WWL, and BL with logic-1 and WBL with logic-"0" are the initial conditions for performing the write-"1" operation.
V SS is pulled to the high level, which turns of the M PRS . Active word line makes M AXR turn on, which allows node-D charge from BL. When node-D is charged, M PL2 gets turned of which allows the node-Db discharges to WBL through M AXL . So node-Db with logic-0 turns on the M PR which can boost the node-SD. Boosted node-SD discharges node-SDb using M PL1 , M NL1 inverter.
Pull-down path for write-0 in SSDF 9T-ST SRAM cell Pull-down path for write-0 in proposed SRAM cell Due to the stacking of multiple transistors (M PDSL and M PDL ), the pull-down path is not strong towards the ground. So write bit voltage change is not strongly refected across node-D in the SSDF-9T SRAM cell [14]. Tis problem is avoided in the proposed SRAM cell with a single transistor clamped at bias ground level in a pull-down path. So write bit voltage change is strongly refected in the proposed SRAM cell.
Te transient response of the proposed BSRWA 10T SRAM cell during a write operation is shown in Figure 6.
Tere is a successful write operation along with write failure cases depending on the adjustment of oxide thickness of M PL2 , M NL2. Smaller oxide thickness (T OX ) gives a higher oxide capacitor (C OX ) and a higher gate capacitance (C G ), so control of the gate on a channel is more in this case for thinbox-SOI as shown in Figure 7. So node-Db responds immediately to node-D changes [18].  Active and Passive Electronic Components Figure 6 illustrates the successful write-"1" operation with node-D, node-Db updated with logic-"1," logic-"0," respectively. But some write failure cases and maximum delays are observed for increasing the value of T OX (T OX > 1.7 nm).
Te Gaussian distribution function of threshold voltage variation is considered as a sample for MC simulation (σ Vth shift ). Occurrence plots are extracted with respective environmental and device parameters [19].

. Results and Discussion
In this section, the performance of the proposed BSRWA 10T SRAM cell is analyzed using the following parameters. Te proposed BSRWA 10T SRAM cell results are compared with previous SRAM cells with assist circuits. Tis section concludes that the proposed SRAM cell's performance is better than previous SRAM cells through the following simulation results. Tis section also concludes that the improved performance in conventional SRAM cells by assist circuits can be dominated by the performance of the proposed BSRWA 10T SRAM cell.

Write Performance Analysis Using WM Parameter.
Write margin (WM) is a parameter to measure the ability and performance of the write operation. Write operation of previous SRAM cells and proposed SRAM cell is observed in previous sections. In this section, the performance of the write operation and comparison results with previous SRAM cells is observed.
Write-ability performance analysis of memory cell through the "WM" parameter and occurrence of WM for proposed BSRWA SRAM cell with reference to previous SRAM cell (SSDF SRAM cell) is observed in Figure 8. Te histogram plot of MC simulation for SSDF SRAM cell, SSDF SRAM cell with UDVS assist circuit [20,21], SSDF SRAM cell with NBL assist circuit [15], and the proposed BSRWA SRAM cell is observed in Figure 8. Te improvement of WM for SSDF SRAM cell [14] is 15.7% (WM � 0.38 V to 0.44 V) by UDVS assist circuit [20,21] and 26.1% (WM � 0.38 V to 0.484 V) by the NBL assist circuit [15]. But the proposed BSRWA SRAM cell has an improvement of WM performance is 34.2% (WM � 0.38 V to 0.510 V) due to built-in self-write assist confguration. Te write performance of the proposed SRAM cell is dominating the previous SRAM cells with the assist circuit's performance also.

Write Performance Analysis Using Write Trip Current (WTI) and
Branch Current Analysis to Measure WTI through I NC . In this section, write trip voltage (WTV) and write trip current (WTI) are the parameters used to measure the ability and performance of the write operation [7]. To explore the individual transistor's efect on trip current, all the branch currents around the internal node-D can be measured in response to the voltage sweep. Te pull-up branch, forced voltage source, and accessing transistor branch supply the current towards node-D; simultaneously, the pull-down branch draws the current from node-D to the ground. Te direction of these branch currents changes based on the data stored in the SRAM cell. WTV and WTV are measured using N-curves [22], which are nothing but I-V characteristics of forced voltage source at memory node (Db � 0) for conventional, Write performance is improved by reducing the level of WTV. "WTV" is nothing but the minimum voltage required to fip the cell with write data.
Te response of forced node current (I NC ) for multiple voltage sweep parameters and multiple cell structures is shown in Figure 9. Te primary sweep parameter is forced node voltage, and the secondary sweep parameter is V BLB . Te trip current level is calculated for diferent sweep voltage levels of V BLB . When WTI is observed, "0" is the indication of data write. So write behavior of SRAM cells is observed based on WTI occurrence plots as shown in Figure 10. WTI depends on V BLB . WTI occurrence plots are shifted right and reach to level-0 at WTV [23]. Figure 11 illustrates that the WTI occurrence plots of conventional, FD 10-ST, SSDF 9T-ST, and proposed BSRWA 10T SRAM cells at V BLB is V DD. WTI is measured from the above occurrence plots and observed as the level of WTI is near "0" in the proposed BSRWA 10T SRAM when compared to previous SRAM cells as shown in Table 1. Write-ability of a bit cell indicates how easy or difcult it is to write to the cell. Write-trip-point defnes the maximum bitline voltage V BIT − MAX needed to fip the cell content. Te higher the bit-line voltage, the lower the write-trip-point, and the easier it is to write to the cell.

Termal-Stability Analysis Using HSNM and Data Retention Voltage (DRV) during Hold Mode of Operation.
In this section, thermal stability analysis is performed using the HSNM parameter. Te justifcation of thermal stability for the proposed SRAM cell is as follows. Node-Db is connected to the ground through M NR1 in the pulldown path. During the read and hold mode of operation, the deviation of electrical voltage strength at node-DB due to M NR1 gets compensated by the change of electrical voltage strength at node-D due to a similar transistor M NR2 . Te electrical properties of M NR1 and M NR2 are the same, so both transistors respond similarly to temperature change. So thermal stability of the proposed BSRWA 10T SRAM cell compared to previous SRAM cells is high, due to the compensation structure. Te efect of temperature change from 15°C to 55°C on stability is observed with SNM occurrence histogram plots using Monte Carlo simulation as shown in Figure 12 [25]. Te improvement of hold stability by the proposed BSRWA 10T SRAM compared with previous SRAM cells is observed in Table 2.
During the hold mode of operation, cell stability depends on the supply voltage. Cell stability is reduced by scaling the supply voltage. Data retention voltage is defned as the minimum operating voltage required by the cell for holding data. Te proposed BSRWA 10T SRAM cell is simulated under diferent operating voltages and corresponding VTC, and HSNM occurrence plots are captured in Figure 13.

Write Delay Analysis.
In this section, the performance of the proposed SRAM cell during the write operation and comparison results with previous SRAM cells are observed. Write-ability performance analysis of memory cells is through the "write delay" parameter [10].    Te write delay of the SRAM cell refers to the time taken to write new data into the cell after the write enable signal has been applied. Te write delay depends on the size of the cell; i.e., area capacitance decides the delay. Te write operation of BSRWA 10T SRAM cell through transient response (transient waveform) is shown in Figure 14. Te occurrence of the delay parameter for the proposed BSRWA SRAM cell with reference to the previous SRAM cell (SSDF SRAM cell) is shown in Figure 15, and measured values are observed in Table 2.

Write
Half-Selected Cell Stability. Te paragraph describes a proposed SRAM cell, called BSRWA 10T, that eliminates the problem of write-half-select disturb in a bitinterleaving structure. Te paragraph explains how the proposed SRAM cell works in four diferent situations during a write operation, including selected, hold, column half-selected, and row half-selected cells as shown in Figure 16.
For the column half-selected cell, the storage nodes are decoupled from BL, so memory node-D, SD gets not disturbed. For the row half-selected cell, corresponding WL, WBLB, and BL are tied to VDD. If the row half-selected cell stores "1," both D and SD remain at "1," and the stored data can be latched safely with any disturbance because node-D and BL are at the same level. If the row half-selected cell stores "0," SD gets charged to "1" through M AXR by BL. But node-D pulled down to ground level through M NR2 , so node-D holds "0," which holds the M PRS in of state through an inverter (M PL1 and M NL1 ). So node-SD is isolated from the core memory node (D). Terefore, the stored data in the row half-select cell can also be latched safely. Te proposed BSRWA SRAM cell operates with a bit-interleaving structure free of write-half-select disturb. Half-selected cell stability is also improved by SPG11T SRAM cell [3]. But the cell is controlled with extra control inputs such as RWL and VSS and also connected with extra transistors to generate SLB. So extra circuitry requires to generate extra control signals, which leads to more dynamic power dissipation. Te proposed BSRWA SRAM cell operates with a bit-interleaving structure free of write-half-select disturb. Half-selected cell stability is also improved by SPG11T SRAM cell [3]. But the cell is controlled with extra control inputs such as RWL and VSS and also connected with extra transistors to generate SLB. So extra circuitry requires to generate extra control signals, which leads to more dynamic power dissipation.
3.6. Cell Area. Figure 17(b) shows the layout of the proposed BSRWA 10T SRAM cell which is compared with previous SRAM cells. Table 3

Conclusion
Tis proposed work concludes that the performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully diferential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). Te proposed SRAM cell dominates SSDF 9T-ST SRAM cell in terms of write ability, even SSDF 9T-ST SRAM cell is assisted with assist circuits such as NBL [15], UDVS [20,21], write assist combining negative BL and V DD collapse. Te read stability improvement of the proposed BSRWA 10T SRAM cell is 212%, 67%, and 33% from conventional SRAM cell, FD 10T SRAM cell, and SSDF 9T SRAM cells, respectively. Te impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for HSNM parameter. Te deviation of HSNM for 15 O C to 55 O C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. Te impact of assist circuits on the write performance of memory cells is observed using Monte Carlo simulation for the write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit [20,21] and write assist combining negative BL and V DD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. Write delay of SSDF 9T-ST SRAM is reduced by 7.3%, 12.4%, and 18.3% by adding NBL [15], UDVS [20,21], and write assist combining negative BL and V DD collapse. But delay is minimized by 19.7% using the proposed BSRWA SRAM cell without any assist circuit. Te proposed SRAM cell is designed at a 22 nm CMOS technology node and verifed in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmoscope wave viewer.

Data Availability
Te data supporting the current study are available from the corresponding author upon request.

Conflicts of Interest
Te authors declare that they have no conficts of interest.