An Ameliorated Small-Signal Model Parameter Extraction Method for GaN HEMTs up to 110 GHz with Short-Test Structure

An improved method of extracting small-signal equivalent circuit model parameters for gallium nitride high electron mobility transistors (GaN HEMTs) is presented. Tis paper intends to present a method to extract the parasitic inductance and resistance of transistors based on the short-test structure without the open-circuit test structure. Te parasitic capacitance of transistors is extracted by the method based on the size scalable model. Compared with the traditional COLD-FET method, the extraction procedure is simpler and more convenient. After removing the infuence of parasitic elements, the intrinsic parameters of the model can be extracted by the S -parameters measured at diferent bias points. Te experimental results show that the simulation results have good agreement with the measured results in the range of 0.5 ∼ 110GHz.


Introduction
GaN high electron mobility transistors have been widely applied in high power and high frequency applications due to their high breakdown voltage and high electron saturation rate [1].In order to better reduce the cost and shorten the design time in the process of integrated circuit design, it is essential to establish an accurate small-signal circuit model that can work in the RF and microwave frequency band [2][3][4][5].Moreover, the accuracy of the S-parameter of the device under test is of great signifcance to the small-signal model, and it is necessary to obtain the accurate S-parameter of the device under test.When conducting S-parameter measurements of the microwave device directly on a wafer, the parasitic efect of metal lines and PAD cannot be ignored.Terefore, considering the parasitic efect of test structure can better improve the accuracy of the model.
It is very obvious that once the parameters of the parasitic elements are determined, the intrinsic elements can be directly obtained after de-embedding the efect of the parasitic elements.Up to now, there have been various methods to extract parasitic elements based on scattering parameter measurement.In the traditional method [6], the pad capacitance can be extracted by using the open-test structure [7].However, this method requires a special test structure for each device size on the wafer, and the inhomogeneity on the wafer must be ignored.In this paper, the equivalent circuit parameters of the test structure are determined [8].Four GaN HEMTs with diferent sizes but identical test structures were used to extract the parasitic capacitance.Trough the above method, the open-test structures can be ignored and the extraction of parasitic parameters is simplifed.In this paper, the scalable small-signal model for GaN HEMTs devices has been developed.An improved extrinsic elements extraction procedure has been proposed.Te main contribution of this paper is that the scalable rules for the small-signal model up to 110 GHz are given in detail.Compared with traditional methods [9][10][11], the proposed method has presented an update of the classical small-signal parameter extraction method, which is very valuable for the industry.Because the use of this method implies that open structures are not necessary.Advantages are clear in terms of area saving, characterization, and data analysis time.
Te organization of this paper is as follows.In Section 2, the small-signal equivalent circuit model used in this paper is introduced.In Section 3, the improved method of extracting parasitic and intrinsic parameters is introduced, and the parameters of the device are extracted by the test structure.In Section 4, the simulation results are compared with the measurement results.

Small-Signal Equivalent Circuit Model of GaN HEMT
Five diferent GaN HEMTs are adopted in this study; they are TZ0210, TZ0420, TZ0630, TZ0840, and TZ0860.All of them were manufactured by UMS using GH15-10 process with 150 nm gate length.Te gate width of TZ0210 is 10 μm and the number of fngers is 2; the gate width of TZ0420 is 20 μm and the number of fngers is 4; the gate width of TZ0630 is 30 μm and the number of fngers is 6; the gate width of TZ0840 is 40 μm and the number of fngers is 8; the gate width of TZ0860 is 60 μm and the number of fngers 8. Te above devices are based on GaN-on-SiC process.
Te two-port S-parameter has been measured in the frequency range from 500 MHz to 110 GHz.Te de-embedding method based on short-test structure has been performed to remove the parasitic component of the PADs and interconnect lines.
Figure 1 shows the equivalent circuit of the GaN HEMT.Te model consists of two parts: the parasitic elements independent of bias voltage and the intrinsic elements dependent on bias voltage.C pg and C pd represent the PAD capacitance of the gate and drain between the signal PAD and the ground, respectively.C pgd represents the coupling capacitance between the gate and drain PADs.L g , L s , and L d represent the inductance of the gate, source, and drain interconnecting lines, respectively.R g , R s , and R d represent the resistance of the gate, source, and drain interconnecting line, respectively.C gs , C gd , and C ds are the gate-source, gate drain, and source drain intrinsic capacitance, respectively.R i is the intrinsic channel resistance, g m is the transconductance, g ds is the drain output conductance, and τ is the time delay.R pg and R pd , respectively, represent substrate losses of input PAD and output PAD.

Parameter Extraction and Results and Discussion
Te resistance and inductance values of the interconnecting lines and the capacitance values of PADs can be determined by testing the S-parameters of the HEMT device's short-test structure.Te value of the intrinsic element can be calculated after removing the infuence of the parasitic element.

Extraction Methods of Parasitic Element.
When the active device works in the cutof region, it presents capacitive passive network characteristics, so the PAD capacitance can be extracted by using the S-parameter and admittance parameter of low frequency (0∼10 GHz) measured under the cutof condition.However, a common premise of these methods is the assumption that the gate-source and drain-source capacitance of all symmetric FETs is equal in the COLD-FET bias case, so the application range of this method is limited.Tis paper presents a parasitic capacitance extraction method based on the proportional model, which can efectively overcome the above disadvantages.Te formula of the traditional COLD-FET method to extract parasitic is as follows: ( Te results of parasitic capacitance are shown in Figure 2.
It can be seen from the extraction results in the fgure that the values of the parasitic capacitances based on the COLD-FET method are large.Te main reason is the infuence of the feed lines and transitions between the PADs and feed lines.Tis problem has been taken into account by the method based on the size scalable model and neglected by the COLD-FET method [12].
Te method based on the size scalable model steps is as follows.Firstly, the S-parameter of diferent gate width devices under the cutof condition is measured.Secondly, the S-parameter is converted into the Y-parameter (admittance parameter).Finally, the values of the parasitic capacitances are obtained from the imaginary part of the Yparameter (admittance parameter) [13].
Te admittance matrix of Y-parameter is represented as follows: Te formula of the equal scalable model method is as follows: Trough the measured S-parameter and Y-parameter of fve diferent devices under the cutof condition, the mean value of the low frequency (0.5∼10 GHz) range was taken as the fnal value.
Te relationship between parasitic capacitance and gate width is shown in Figure 3.
In the ftting function of the relation between the gate width (the GaN PHEMTs with 2 × 10 µm, 4 × 20 µm, 6 × 30 µm, 8 × 40 µm, and 8 × 60 µm) and the imaginary part of the Y parameter (admittance parameter) in the Figure 3, which shows the relationship between the imaginary parts of the Y-parameters, (i, j = 1, 2) and the gate width of the HEMTs.Since the value of Cpgd is so small that it is almost negligible, the intercept value can be considered to be the value of Cpd and Cpg.
Comparing the results of the two methods, it is obvious that the capacitance value obtained by the proposed method is closer to the fnal optimization result than that obtained by the traditional method.
Te values of the substrate resistances can be extracted by the following formulas: Substrate efects start to be dominant above 50 GHz.Considering the frequency range of this work, which achieves 110 GHz, the substrate resistance value can be extracted using the real part of Y-parameter under high frequency (60∼70 GHz) conditions.Te results of substrate resistances are shown in Figure 4.

Extraction Methods of Parasitic Inductance and
Resistance.Te values of the parasitic inductance and the parasitic resistance can be obtained by the following formula: where Y short is the admittance matrix obtained from conversion of the measured S-parameters of the short-test structure (as shown in Figure 5); Y short1 is the admittance parameter of the dashed box part of Figure 5 equivalent circuit; Y PAD is the admittance matrix obtained from conversion of the measured S-parameters of Figure 6.
where Z short1 is the impedance parameter matrix obtained from the conversion of Y short1 .Ten, we can get the expressions of R s , R g , R d , L s , L g , and L d as follows: Finally, the values of the obtained parasitic elements are taken as the initial value for iterative optimization.Te optimization results are shown in Table 1.

Extraction Methods of Intrinsic Element.
When the operating frequency is relatively low, the efect of the parasitic resistance and the parasitic inductance of the interconnect is almost negligible.However, when the working frequency increases, especially when the working frequency enters the millimeter band, the parasitic inductance of interconnect on the device cannot be ignored, so when the working frequency is high, it must de-embed, and the specifc de-embedding process is as follows:

Active and Passive Electronic Components
Step 1: the S-parameter S DUT of the device under different bias conditions is obtained by using the on-chip test system.
Step 2: strip the parallel parasitic parameters according to the following equation: Formula ( 9) represents the stripping of parasitic parameters from admittance parameters of the device under test, and formula (5) represents the stripping of parallel parasitic parameters from impedance parameters of the short-test structure.Y HEMT1 represents the admittance parameter of the transistor under test after de-embedding.4 Active and Passive Electronic Components Step 3: convert Y HEMT1 and Y short1 into corresponding impedance parameters Z HEMT1 and Z short1 and then subtract them to obtain impedance parameter Z HEMT of the device under test after removing the infuence of parasitic parameters: Step 4: the YHEMT parameter of the transistor can be obtained by converting ZHEMT into impedance parameter.
Step 5: the intrinsic parameters of the device under test were calculated according to the following formulas:

Measurement and Discussion
Te S-parameter measurements for model extraction and verifcation were made up from 0.5 GHz to 110 GHz using an Agilent E8361A network analyzer, with DC bias being supplied by an Agilent E5270A.All measurements were carried out on wafer using Cascade Microtech's Air-Coplanar Probes M150, with all instruments under IC CAP software control.Te wafer probes were calibrated using line-refect-match (LRM) calibration technology.
Te parasitic capacitances extraction method proposed in this paper has been proved on wafer up to 110 GHz using GaN HEMTs with 0.15 µm gate length.In this paper, the GaN HEMTs with 2 × 10 µm, 4 × 20 µm, 6 × 30 µm, 8 × 40 µm, and 8 × 60 µm gate width (number of gate fngers × unit gate width) and a comparison of the novel method with the conventional method are given.
Te measured pinch-of cold-FET S-parameters for three diferent size HEMTs are frstly transformed to Y-parameters, and then the imaginary parts of Y-parameters can be extracted at low frequencies.Te bias condition is V gs � − 5 V and V ds � 0 V.Under this bias condition, the whole network is in a cutof state.Te corresponding intrinsic capacitances under pinch-of bias condition are summarized in Table 2.
Te values of substrate resistances can be extracted under bias of V gs � 0 V and V ds � 0 V.Under this bias condition, the HEMT is already in saturation region.Te extraction results of substrate resistances values are R pd � 45.54 Ω and R pg � 20.83 Ω, respectively.Te equivalent circuit was constructed in the Keysight ADS software; a set of bias in the saturation region (V g � 0 V and V d � 8 V) and the cutof region (V g � −5 V and V d � 4 V), respectively, is for verifcation.Te obtained parasitic parameters and intrinsic parameters were substituted into the model as initial values for iterative optimization.Te fnal results are shown in Tables 3-5.

Experimental Verification
Figures 7-9 show the comparison of the refection and transmission co-efcients of simulations and measurements of the devices under the diferent bias in the frequency range of 0.5-110 GHz.It is observed from the fgure that relatively good agreement between measured and simulated data can be achieved.Good agreement has been obtained between the modeled and measured S-parameters to verify the improved parameter extraction approach in this article.

Conclusions
In this paper, an improved method is used to extract the parasitic resistances of the gate, source, and drain when extracting the parameters of the small-signal equivalent circuit model of the GaN HEMTs.Te proposed method without the open-test structure is compared with the traditional COLD-FET capacitance extraction method.Te accuracy and efectiveness of the method based on the size scalable model in the extraction of parasitic inductances are proved.Te simulated S-parameters are in good agreement with the measured S-parameters in the frequency range up to 110 GHz.

Figure 1 :
Figure 1: Te equivalent circuit model of the GaN HEMT.

Figure 5 :Figure 6 :
Figure 5: Te equivalent circuit of the short-test structure.

Table 1 :
Results of parasitic parameter extraction.

Table 2 :
Extracted results for intrinsic capacitances under pinch-of bias condition.

Table 3 :
Results of intrinsic parameter extraction, bias:V g � − 5 V and V d � 4 V.

Table 4 :
Results of intrinsic parameter extraction, bias:V g � 0 V and V d � 8 V.

Table 5 :
Results of intrinsic parameter extraction, bias:V g � − 5 V and V d � 0 V.