Degradation Analysis of Chaotic Systems and their Digital Implementation in Embedded Systems

Digital implementation of chaotic systems (CSs) has attracted increasing attention from researchers due to several applications in engineering, e.g., in areas as cryptography and autonomous mobile robots, where the properties of chaotic systems are strongly related. e CSs in the continuous version (CV) need to be discretized where chaotic degradation must be analyzed to guarantee preservation of chaos. In this paper, we present a degradation analysis of ve three-dimensional CSs and the necessary conditions to implement the discretized versions (DVs) of Lorenz, Rössler, Chen, Liu and Chen, and Méndez-Arellano-Cruz-Mart́ınez (MACM) CSs. Analytical and numerical analyses of chaos degradation are conducted by using the time series method; the maximum discrete step size and the Lyapunov Exponents (LEs) are computed by using the Euler, Heun, and fourth-order Runge–Kutta (RK4) numerical algorithms (NAs).We conducted comparative studies of performance based on time complexity of the ve proposed CSs in their DVs by using four embedded systems (ESs) based on three families ofMicrochipmicrocontrollers 8bit PIC16F, 16-bit dsPIC33FJ, and 32-bit PIC32MZ (of low-cost electronic implementation) and a Field Programmable Gate Array (FPGA). Based on the results, the intervals at control parameters to guarantee chaos are proposed, which improves the performance characteristics of the ve proposed CSs in their DVs based on digital applications.

Recently, the literature reports degradation studies of 3D CSs in their DVs by using the NA of Euler; a robustness diagram for control parameters guarantee chaos is presented, and its digital implementation is conducted in a microcontroller PIC32 [29].
e methods equivalent used to conduct arithmetic and logical calculations inside of a microprocessor-or its equivalent microcontroller as main core of an ES-are based on numerical standards.Microchip Technology Inc. is the manufacturer of PIC, dsPIC, and PIC32 microcontrollers; their numerical results are based by the IEEE-754 Compliant Floating Point Routines [45].On the other hand, Altera-Intel is an FPGA manufacturer, and their numerical results of simulations are represented in IEEE-754 (2008) [46,47].
e NAs are simulated by using Matlab, and its results are similar in comparison with the compilers used by Microchip microcontrollers and software for design used by Altera-Intel FPGA because both are based on IEEE-754 [35,46,47].
e FPGA has powerful simulation tools to reproduce chaotic dynamics of CSs in their DVs by using digital signal processing (DSP) modules as a complementary tool for Matlab/Simulink software, e.g., Altera Simulink/DSP Builder and Xilinx System Generator BlockSet [48,49].
In this paper, we present a degradation analysis of the five 3D CSs in their DVs to determine the performance of implementation in four versions of an ES, the time complexity, and the intervals of control parameters to guarantee chaos are obtained.e results of this paper can be of great interest for digital applications of chaos in engineering.To our knowledge, the literature does not report comparative studies of digital degradation of five 3D CSs in their DVs by using the NAs of Euler, Heun, and RK4, where its performance is conducted in microcontrollers of 8, 16, and 32 bits, and FPGA.
e paper is organized as follows: In Section 2, the normalized version of five three-dimensional CSs are presented, numerical analyses calculating the Lyapunov exponents are conducted to verify the chaotic behavior using the Euler, Heun, and RK4 NAs where a Root-Mean-Square Error (RMSE) analysis is conducted to compare their continuous and DVs.Section 3 presents the digital implementation on ES with 8-bit PIC16F, 16-bit dsPIC33, 32-bit PIC32MZ microcontrollers, and the Altera FPGA Cyclone IV GX, where the performance and the robustness digital diagram to guarantee the chaos is proposed.Finally, conclusions of this work are reported in Section 4.

Degradation Analysis
In this section, we describe the normalized equations of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs to obtain their DVs by using the NAs of E, H, and RK4. e time series method is used to obtain the degradation limits by calculating the LEs of the five 3D CSs in their continuous and DVs [50,51].We analyzed the accuracy of the trajectories of state variable x of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs by calculating the RMSE.All the numerical results and methods described in this section are conducted by using Matlab [35].

Normalized 3D CSs.
is subsection briefly describes the normalized version of the Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs, and the difference between them is given by the complexity of their dynamics, the representation of their nonlinear functions, and parameters.
First, we consider the Lorenz system, which is a wellknown example of a CS.Lorenz's three-variable model provides a practical test case with qualitatively realistic properties [18]; it is represented by the nonlinear state equations described as where x, y, and z are the state variables and the standard parameter values for Lorenz's chaotic attractor are σ � 10, r � 28, and b � 8/3.We also consider the Rössler system introduced by Rössler in 1976 [19], which is described by where x, y, and z are the state variables, the Rössler system presents chaotic behavior for the following parameter values: a � 0.2, b � 0.2, and c � 5.7.Similarly, the Chen system is introduced as a dual system of the Lorenz system in 1999 [23] and is described by where x, y, and z are the state variables and the Chen system presents chaotic behavior for the following parameter values: a � 35, b � 3, and c � 28.Moreover, the Liu and Chen system was introduced in 2002, and its description is given by [24] where x, y, and z are the state variables, this nonlinear system presents a chaotic behavior when the following condition ab + ac + bc ≠ 0 is met.It can create a complex 2-scrolls attractor from the following parameter values: and b � − 3.4.Recently, the MACM CS was proposed in 2017 [29], which is described by where x, y, and z are the state variables and the MACM system presents chaotic behavior for the following parameter values: a � b � 2, c � 0.5, and d � 4.
e literature reports the validation of chaos calculating the limits of the LEs by using the time series method by Wolf and Briggs [50,51], and the LEs and fractal dimension, commonly known as Kaplan-Yorke dimension D KY , of the five 3D CSs (1)-( 5) in their CVs are computed by using the proposed time series method.Table 2 shows the LEs and the fractal dimension results of CSs ( 1)-( 5) in their CVs.

Numerical Algorithms.
NAs of Euler, Heun, and RK4 are used to obtain the DV of the CSs (1)-( 5), the step size as referred to as τ, and n is the iteration number that represents the time in DV. e nonlineal functions f, g, and h of the five 3D CSs of Lorenz, Rössler, Chen, Liu and Chen, and MACM in their DVs describe the states x, y, and z, respectively.
Euler algorithm presents just one step, and it is easy to implement because it requires less arithmetic operations [35].e Euler NA is described by e Heun is the second NA implemented [35]; this method is known as trapezoidal in two steps where the first step predicts and the second step corrects.e NA of Heun is described as follows: where e third NA is the RK4; this algorithm is one of the most widely used methods for solving differential equations [35].e NA of RK4 is given by where k 1 , k 2 , k 3 , and k 4 are referred to as coefficients of the first equation, similarly, the parameters l 1 , l 2 , l 3 , and l 4 are referred to as coefficients of the second equation, and the parameters m 1 , m 2 , m 3 , and m 4 are referred to as coefficients of the third equation.e coefficients described in system (9) are given by Finally, the coefficients described in (10)-( 13) are placed in (9); they as whole represent the NA of RK4 ( 9)-(13).

Degradation Analysis of the 3D CSs in eir DVs.
In this subsection, the maximum step size is referred to as τ max , and it is computed by using the time series method considering one positive LE as the condition to guarantee chaos in the DV of the five 3D CSs [50,51].LEs to obtain the chaotic degradation of the five CSs in their DVs are computed by using the NAs of Euler (6), only the τ max were reported in [29]; in this study, the LEs and D KY are added, and their results are presented in Table 3.In addition, we computed LEs, τ max , and D KY of the five CSs in their DVs by using the NAs of Heun (7) and (8) and RK4 ( 9)- (13), and their results are presented in Tables 4 and 5, respectively.e results obtained in  show that MACM CS presents the higher τ max , and Chen and Liu and Chen CSs Complexity present the smallest τ max in comparison with Lorenz.In the case of Rössler system, we recommend to use τ max � 0.005 because, for higher values, the dynamical chaotic behavior is lost and dynamic behavior of limit cycle for step sizes within the intervals 0.006 ≤ τ ≤ 0.091 is shown; for higher values of τ � 0.091, the LEs cannot be computed using the time series method with the NA (6).Rössler system supports an interval small of τ max , because the chaotic dynamics diverges.Nevertheless, Rössler system presents a high interval in comparison Lorenz system by using the NAs of Heun (7) and (8) and RK4 (9)- (13), and their results are described in Tables 4 and 5.
Figure 1 illustrates the comparison of τ max obtained with the results of the NAs described in Tables 3-5.NA of RK4 presents higher τ max in comparison of the NAs of Euler, and Heun.e DV of MACM system presents a higher τ max than the DV of the CSs of Lorenz, Rössler, Chen, and Liu and Chen systems.

Performance of Chaotic
Behavior.We use RMSE to compare the performance and accuracy of the trajectory of state x of the CSs (1)-( 5) in their CVs respect to their DVs by using the NAs of Euler (6), Heun ( 7) and ( 8), and RK4 ( 9)-( 13).e RMSE is defined as follows: where the state variable x e(n) is referred to as the estimator value of the CV of CSs ( 1)-( 5), the state variable x (n) is referred to as the predicted estimated value of DV of CSs ( 1)-( 5), and n is referred to as the total number samples.e Ordinary Differential Equation (ODE) function number 45 (ODE45) of MATLAB is considered to reproduce the CV of the CSs (1)-( 5), although strictly it is also a discretized representation, this algorithm is based on an explicit Runge-Kutta
e error calculation is compared with respect to state variable x (n) of the five 3D CSs in their DVs, and their trajectory errors are referred to as follow: e 1 represents the difference between ODE45 and Euler algorithm ( 6), e 2 represents the difference between ODE45 and Heun algorithm (7) and (8), and e 3 represents the difference between ODE45 and RK4 algorithm ( 9)- (13).
Figure 2 shows the comparison of the evolution of the state variable x (n) of the Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their continuous version using ODE45 and DVs using the NAs of ( 6)- (13).Figure 3 shows the trajectory errors e 1 -e 3 of the trajectories of set of CSs shown in Figure 2. Figure 2(b) shows that the trajectories of the Rössler system (2) have no changes; they are practically the same trajectories for the DVs with respect to the continuous version (2), and Figure 3(b) shows that the Rössler system has minimal errors for e 1 − e 3 .Considering the numerical results of the trajectories of state x of the set of five 3D CSs shown in Figures 2 and 3, the RMSE comparison is obtained by using (14), and its result is shown in Figure 4. Chen and Liu and Chen systems show high RMSE, and to a lesser extent in the Lorenz system, followed by this value, the MACM system exhibits a low RMSE value, but the Rössler system exhibits the lowest RMSE (see Figure 4).

Digital Implementation
In this section, we present the necessary conditions to implement the NAs of the five 3D CSs in their DVs considering the described studies in Section 2. e digital implementation is carried out in an ES which main core is represented in four different hardware versions: 8-bit PIC16F, 16-bit dsPIC33, and 32-bit PIC32MZ microcontrollers, and one Cyclone IV GX FPGA.Table 6 shows the hardware description of the four versions of the ES.
Microcontrollers U1-U3, FPGA U4, and DACs U5-U7 are configured according to the performance recommended by their manufacturers-the SPI protocol was configured in the master mode from specification of U1-U4 by using 12 bits of resolution.e DAC U5, U6, and U7 represent the state variables x (t) , y (t) , and z (t) , respectively, and its software configuration is given from U1-U4. Figure 5 shows the hardware description for the four versions of ES.Version 1 (V1) represents the hardware implementation by using U1, Version 2 (V2) represents the hardware implementation by using U2, Version 3 (V3) represents the hardware implementation by using U3, and Version 4 (V4) represents the hardware implementation by using U4.
e compilers of the manufacturer Mikroelektronika are used to program U1-U3 [54].e FPGA U4 is programmed by using the set tools of Quartus II to design the hardware, and Eclipse compiler is used to design the software.erefore, the numerical results conducted in the proposed four versions V1-V4 of the ES are similar because Matlab and the C compilers to program U1-U3 and U4 have the IEEE-754 standard [35,[44][45][46].
In order to conduct the simulations of the NA, we used the Proteus Virtual System Modeling (VSM) Software, in special, the VSM for Microchip version that contains the device libraries of some families of 8-bit PIC and 16-bit Complexity dsPIC33 microcontrollers, and the schematic capture tool was used to simulate the complete V1 and V2 ESs [55].e numerical results of V1-V4 proposed and their equivalences between simulation and implementation are carried out by using the methods described in [29,37,38].e total quantity of iterations Q T is referred to as the maximum number of n iterations generated in 1 second, and it is represented in time units (tu), and the CSs (2)-( 6) are represented in three dimensions, i.e., we are considering N � 3 dimensions, and the Q T representation is given by Complexity using the main core of U1, U2, U3, or U4; the total-graphic time t Tg is the time that the three DACs U5-U7 need to represent the state variables x (t) , y (t) , and z (t) , and the time required for each DAC (U5-U7) is referred by t Tdac(1-3) , respectively.e measurement of the iterations f Tg and the time T Td are obtained experimentally when the program of NA used is executed in the 4 versions of the ES.Only t c depends on the size of the NA used.e size of t Tg depends of the configuration of SPI protocol used in U1-U4.
e equation ( 15) is a reference to determine the performance of the proposed ES in their four versions V1-V4.In this study, we need to obtain a smaller period of time to determine a greater number of iterations n and a higher step size to guarantee the chaos proposed in Tables 3-5; their values depend on the NA of the CSs proposed and the version of the ES that will be implemented.Given these considerations, we will obtain a higher Q T . is means that the state variables of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs by using the NAs (6)-( 13) have a better representation of f Td , which is very attractive for applications based in chaos such as: master key definition, encryption, and secure communications [9,37,43,56].

Embedded System with 8-Bit PIC Microcontroller.
First, we implemented the ES in the V1 by using the microcontroller PIC16F874A U1.We used Proteus to conduct the electronic simulations of the NAs of the CSs proposed, and the schematic diagram is shown in Figure 6.
Euler algorithm ( 6) is used to obtain the DV of the Lorenz system and its corresponding system is given by Figure 7 shows the results of the Lorenz system simulation in its DV (16), we considered the higher step size τ max � 0.024 according to the results shown in Table 3. e voltage supplied for the ES in V1 is V dd � +5 V and V ss � 0 V, and an external crystal of 16 MHz is used according to the datasheet of U1.
e test in the version 1 on the ES is conducted, and we obtained T Td � 2046 μs and f Td � 488.7 ips; this means that we can obtain Q T �11.7 tu in 1 second by using V1 in the Proteus simulator.
To conduct the hardware implementation on V1 of ES, we used the same electrical parameters used in the simulation of CS (16). Figure 8 illustrates the implementation results of the algorithm ( 16) by using the 8-bit PIC microcontroller U1. Figure 8(b) shows the time evolution of the state variables x (n) and z (n) of Lorenz system (16) for 1 second.We experimentally obtained t c � 1989 μs, t Tg � 57 μs, T Td � 2046 μs, and f Td � 488.7 ips considering the same τ max � 0.024; this means that the simulation conducted by using Proteus and the hardware implementation in the version 1 is consistent, because both have the same units of Q T �11.7 time in 1 second.
e NAs of Euler (6), Heun ( 7) and ( 8), and RK4 ( 9)-( 13) of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs are executed in the V1 of the ES; the NA of RK4 ( 9)-( 13) cannot be executed using U1 because the size of its program flash memory is small and it only supports 4K bytes.We obtained the performance of the ES in the V1, and the time complexity and the iterations per second are detailed in Table 7.     7) and ( 8), and RK4 ( 9)-( 13) of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs are implemented by using the ES in its version 2. Figure 9 illustrates the simulation and implementation of dsPIC33 U2 in Proteus by using the V2 of the ES. e voltage supplied for the ES in V2 is V dd � +3.3 V and V ss � 0 V, and an external crystal of 10 MHz is used according to the datasheet of U2.
We conducted an example to implement the Liu and Chen CS in its DV by using the Euler algorithm (6), and its algorithm is described as follows: Figure 10 shows the simulation results conducted in Proteus of the DV of Liu and Chen CS (17) by using dsPIC33  Figure 11 shows the implementation results of the algorithm (17) of the ES in its V2 considering the same τ max � 0.002, we obtained t c � 86 μs, t Tg � 3 μs, T Td � 89 μs,     8 shows the summarized performance of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DV by using the NAs of Euler (6), Heun ( 7) and ( 8), and RK4 ( 9)-( 13)-the values of time complexity and its equivalence are defined in ips.All the NAs can be executed by using dsPIC33 U2 because its program flash memory is 32 Kbytes, and it allows to execute large NAs.e PIC32MZ is not supported by the Proteus simulator; only Mikro C for PIC32 compiler was used to simulate and execute the NAs.Chen CS in its DV was chosen to carry out the test in the V3 of the ES by using Heun algorithm ( 7) and ( 8), and its algorithm is given by

Embedded System with PIC32
where e performance of the algorithm ( 18) and (19) in the version 3 is t c � 13.3 μs, t Tg � 3 μs, T Td � 16.3 μs, and

Phase plane x(n) versus z(n).
(a) 12 Complexity f Td � 61349 ips.In order to obtain a comparison between the step sizes obtained, Figure 12 shows two implementations of the algorithm ( 18) and (19).For the first test, we considered a small step size τ � 0.001; this means that we obtained Q T � 20 time units in 1 second as is shown in Figure 12(b).For the second test, we used the higher step size τ max � 0.017 as it was described in Table 4. e maximum chaotic degradation is obtained for Q T � 340 time units in 1 second, as is shown in Figure 12(d).
Table 9 shows the time complexity and frequency, expressed in ips, and the performance of ES in V3 by using the NAs of Euler (6), Heun ( 7) and ( 8), and RK4 ( 9)-(13).

Embedded System Implemented with FPGA by Using Nios
Microcontroller.We introduce a novel method to design an embedded microcontroller in FPGA U4 considering the   Complexity similar software and hardware conditions used in the previous implementations of ESs.We create a project in Quartus II (version 12.1) by using the Q sys tool to obtain the hardware design in FPGA U4. e Q sys tool is used to define the specifications of hardware described in a complex arrangement of modules inside FPGA U4; this hardware specification is named Entity, and it can be conducted using the block diagram of Quartus II, e.g., the hardware design of Entity U4 includes a microcontroller as the main processor (its fast version is referred to as Nios II/f which internal clock is configured to 150 MHZ), one program memory, peripherals of control, and external ports, among others; to carry out the implementation of the Entity in an FPGA using the Nios II microcontroller, control modules, and other Q sys tools, we recommend reviewing [47].e hardware implementation is based on the specifications of the FPGA U4 that is included in the hardware of the Terasic DE2i-150 board.
Once the Entity is defined on the FPGA U4, the pins of the SPI control-bus are configured and addressing using the expansion header of the DE2i-150 board where the global peripheral input-output (GPIO) port is configured to write the DACs U4-U6 because the DE2i-150 board does not contain internal DACs. Figure 13 shows the block diagram and the result of the Entity design using Q sys of Quartus II.
Once the hardware structure on FPGA U4 is finished, the Eclipse compiler (version IDE for C/C++ developers) is used to program and implement the NAs of the DV of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in the V4 of the ES.For this example, we used the RK4 algorithm ( 9)-( 13) to obtain the DV of the MACM CS; the algorithm is given by where e performance of the algorithm ( 20)-( 24) in the V4 is t c � 156 μs, t Tg � 3 μs, T Td � 159 μs, and f Td � 6289 ips.As in the previous case, we conduct a comparison between the step sizes obtained.Figure 14 shows the result of two implementations of the algorithms ( 20)-( 24) in the V4.For the first test, we considered a small step size τ � 0.01; Figure 14(b) shows a fewer number of Q T � 62.89 time units generated in 1 second.For the second test, we used the higher step size τ max � 0.547 described in Table 5, a large number of time units are obtained Q T � 3440.1 in one second, and the maximum chaotic degradation is illustrated in Figure 14(d).
Table 10 shows the results of the ES in the V4; the time complexity and frequency, expressed in ips, were obtained by using the NAs of Euler (6), Heun ( 7) and ( 8), and RK4 ( 9)-(13).

Results of Embedded
System for V1-V4.In order to summarise the studies presented in the previous section, we conducted a comparison considering the performance of the 4 versions in the ES of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs.We used (15) to obtain the time units Q T generated in 1 second considering the results obtained of τ max shown in Tables 3-5, and the results of T Td and f Td shown in Tables 7-10.We obtained the best performance of Q T considering τ max of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs using the NA of Euler, Heun, and RK4, and the summarized results are presented in Tables 11 and 12.
For a better understanding, Figure 15 illustrates the trajectories of the first state x (n) of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs by using the NA of Euler (8); the performance of each state x (n) is implemented in the V1-PIC of ES-the results are expressed in the time-units quantity Q T that the ES in the V1 generates in 1 second, and the t axe is included to compare the performance of CSs used.Figures 15(a Figure 16 shows the same trajectories of the first state x (n) of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs by using the same Euler algorithm (8); now the performance is conducted in the V2-dsPIC of the ES-the results also are expressed in the time-units quantity 14 Complexity

Robustness in Digital Implementation of CSs in DV
e literature reports robustness in ESs considering the characteristics of software and hardware [57].Regarding the hardware used in the 4 versions of the ES, it has two ways of powering: the first way is through the USB port connected to a laptop or desktop PC, e.g., for the V4 of FPGA device; the second way is using an external power supply for the V1-V3.
e ESs V1-V4 energized using an external battery makes them portable, which allows the autonomy of each of them.
On the other hand, a robustness diagram based on the variation of two critical parameters in the five 3D CSs in their DVs using the NAs (6)-( 13) was conducted.Figure 17 shows the diagram that determines the regions for two parameters which the existence of chaos is guaranteed for a specific step size obtained in Tables 3-5, each point in the diagram represents the maximum Lyapunov exponent (LE max ).If we have LE max > 0, the dynamics are chaotic denoted in yellow color; otherwise, the blue color is used, previous work was reported in [29].Figures 17(a 7) and (8), and for Figures 17(c), 17(f), 17(i), 17(l), and 17(o), we used the NA of RK4 ( 9)- (13).
Furthermore, it is easy to note that if a value of step size τ less than that considered in yellow color is used, then the chaos regions increase.Taking into account the fact that the preservation of chaos in the DV of the set of 5 CSs in their DVs is robust for the variation of two parameters, considering the characteristics of software and hardware the proposed ES in V1-V4, and the benefits of digital systems, as the elimination of the typical wear of the analog systems, it is stated that the electronical/digital implementation presented in this work is robust.

Conclusions
In this paper, we have presented analytical, numerical, and experimental studies of chaos degradation of the Lorenz, Rössler, Chen, Liu and Chen, and MACM three-dimensional chaotic systems (CSs) in their discretized versions (DVs) by using the numerical algorithms (NAs) of Euler, Heun, and fourth-order Runge-Kutta (RK4).We obtained a novel robustness diagram with the variation of two parameters of the five CSs in their DVs to guarantee the chaos existence where the maximum step size was found by using Euler, Heun, and fourth-order Runge-Kutta (RK4) NAs, the degradation studies showed that the DV of MACM CS exhibits higher chaotic degradation, while the Chen and Liu Chen presented a lower degradation.e step-size values founded can be used, e.g., for encryption applications, as one more parameter, considering the intervals shown in this paper to guarantee chaos.In addition, the step size obtained can be used in others families of 8-, 16-, and 32-bit microcontrollers, DSP, or FPGA where the DVs of these five 3D CSs studied are desired for general purposes.
e numerical studies of Root-Mean-Square Error (RMSE) have shown better performance in the Rössler system, it provided interesting and attractive results with respect to the DVs of the Lorenz, Chen, Liu and

Figure 1 :
Figure 1: τ max summary of chaotic degradation of the five 3D CSs in their DVs.

Figure 4 :
Figure 4: RMSE comparison of trajectory performance of state x of five 3D CSs (1)-(5) in their CVs with respect to their DVs using the NAs (6)-(13).

Figure 6 :
Figure 6: Schematic of the simulation of ES in V1 with the Proteus software.
Channel A : State x(n) Channel B : State z(n) (b)

Figure 7 :
Figure 7: Simulation of ES in the V1 of Lorenz system in its DV by using τ max � 0.024.(a) Phase plane x (n) versus z (n) and (b) evolution of state variables x (n) and z (n) .

Figure 8 :
Figure 8: Implementation of Lorenz CS (15) in its DV by using the V1 of ES: (a) Phase plane x (n) versus z (n) and (b) evolution of state variables x (n) and z (n) .

Figure 9 :
Figure 9: Schematic of the simulation of ES in V2 by using Proteus.

Figure 11 :
Figure 11: Implementation of ES in V2 of Liu and Chen CS (16) in its DV.(a) Phase plane x (n) versus z (n) and (b) evolution of state variables x (n) and z (n) .

Figure 10 :
Figure 10: Simulation of ES in V2 of Liu and Chen in its DV by using τ max � 0.002.(a) Phase plane x (n) versus z (n) and (b) evolution of state variables x (n) and z (n) .

Figure 12 :
Figure 12: Implementation of ES in the V3 of Chen CS (18) and (19) in its DV.(a) Phase plane x (n) versus z (n) , (b) evolution of state variables x (n) and z (n) by using τ � 0.001, (c) phase plane x (n) versus z (n) , and (d) evolution of state variables x (n) and z (n) by using τ max � 0.017.
),15(d), and 15(e) show chaotic dynamics more compactly in the trajectories of state x (n) .Otherwise, Figures15(b) and 15(c) show trajectories of the state x (n) less compact.

Figure 13 :
Figure 13: Schematic diagram of ES in V4 to implement the Nios II Entity and pins distribution on the FPGA U4.

Figure 14 :
Figure 14: Implementation of ES in V4 of the MACM CS (20)-(24) in its DV.(a) Phase plane x (n) versus z (n) , (b) evolution of state variables x (n) and z (n) using τ � 0.01, (c) phase plane x (n) versus z (n) , and (d) evolution of state variables x (n) and z (n) using τ max � 0.057.

Figure 15 :
Figure 15: Time series of the five CSs of Lorenz, Rössler, Chen, Liu and Chen, and MACM in their DVs by using the Euler NA to compare the performance of version 1 PIC of ES expressed Q T for t � 1 second: (a) x (n) of Lorenz, (b) x (n) of Rössler, (c) x (n) of Chen, (d) x (n) of Liu and Chen, and (e) x (n) of MACM.
)-17(c) represent the variation of the parameters σ versus r of the Lorenz system in its DV, the parameter b was fixed in 8/3.Figures17(d)-17(f ) represent the variation of the parameters b versus c of the Rössler system in its DV (the parameter a was fixed in 0.2).Figures 17(g)-17(i) represent the variation of the parameters b versus c of the Chen CS in its DV (the parameter a was fixed in 35).Figures 17(j)-17(l) represent the variation of the parameters b versus c of the Liu and Chen CS in its DV (the parameters were fixed with a � 5, d 1 � − 1, and d 2 � d 3 � 1).Finally, Figures 17(m)-17(o) represent the variation of the parameters b versus d of the MACM CS in its DV (the parameters were fixed with a � 2 and c � 0.5).To generate Figures 17(a), 17(d), 17(g), 17(j), and 17(m), we use the Euler NA (6), for Figures 17(b), 17(e), 17(h), 17(k), and 17(n), we use the Heun algorithm ( 0

Figure 16 :
Figure 16: Time series of the five CSs of Lorenz, Rössler, Chen, Liu and Chen, and MACM in their DVs by using the Euler NA to compare the performance of version 2 dsPIC of ES expressed Q T for t � 1 second: (a) x (n) of Lorenz, (b) x (n) of Rössler, (c) x (n) of Chen, (d) x (n) of Liu and Chen, and (e) x (n) of MACM.

Table 3 :
(6)lysis of chaos degradation for DV of 3D CSs by using the NA of Euler(6).

Table 4 :
Analysis of chaos degradation for DV of 3D CSs by using the NA of Heun (7) and (8).

Table 5 :
Analysis of chaos degradation for DV of 3D CSs by using the NA of RK4 (9)-(13).

Table 6 :
Hardware description of the ES for V1-V4.
T � 22.5 tu in 1 second.Table Microcontroller.A novel family of PIC32MZ microcontrollers is used to implement the

Table 10 :
Performance of ES in the V4 of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs by using Euler (6),

Table 11 :
Performance of the ES expressed in Q T of the 3D Lorenz, Rössler, Chen, Liu and Chen, and MACM CSs in their DVs using (