Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

National ASIC System Engineering Research Center, Southeast University, Nanjing, China Center for Discrete Mathematics and !eoretical Computer Science, Fuzhou University, Fuzhou, China State Key Laboratory of ASIC and System, Fudan University, Shanghai, China Shandong Key Laboratory of Computer Networks, School of Computer Science and Technology, Qilu University of Technology (Shandong Academy of Sciences), Jinan, China


Introduction
As the advanced technology node enters the deep nanometer era, routing has become much challenging because of the enormously growing scale of the large scale of very-large-scale integration (VLSI) circuit [1]. Among the routing problems, bus routing is attracting most research interest and has met new challenges: (1) all bits in each bus must be routed with the same routing topology; (2) nonuniform and complex routing track configurations; and (3) we need to handle obstacles. Particularly, the constraint according to which all bits belonging to the same bus must be routed following the same routing topology makes the previous routers not applicable to current topology-matching bus routing.
Previous works on bus routing focused mainly on printed circuit board (PCB) designs. For example, Tian and Watanabe [2] considered the delay-matching constraint in bus routing to meet several timing specifications. Yan and Wong [3] and Zhang et al. [4] handled the length-matching bus routing such that the wire lengths of all nets on the same bus are within the specified range. However, none of these works considered the constraint of maintaining the same topology for all bits on the same bus. erefore, it is desirable to develop an effective and efficient topology-matching bus routing algorithm.
According to the previous criteria, the bits in a bus are considered to have the same topology if the following four criteria are met: (1) All bits have the same number of wires.
(2) All wires traced from all bits have the same layer sequencing. (3) All wires traced from all bits route towards the same direction. (4) Within each segment (a segment is a set of wires of different bits with the same sequence when traced from a set of pin shapes), the wires of different bits maintain the same or the reverse order as the order seen from the pin shapes. Figure 1(a) illustrates a bus being routed successfully with the same topology. Supposing that we start tracking the wires from the pin shapes on the left, as shown in this figure, all wires traced from all bits have the same direction (rightward, downward, and rightward, resp.) and the same layer sequencing (L1, L2, and L1). In addition, within all segments (seg1, seg2, and seg3), the wires of different bits maintain the same order or the reverse order as the order of pin shapes.
Routing tracks are designed to help routers comply with various design requirements and help mask coloring, which are essential in advanced technology node [5]. Each routing track has a width constraint that only wires with width no larger than the constraint are allowed to be routed on the track. Since the routing requirements of different buses may be different (e.g., different wire widths and different wire spacing), the routing track configuration may be nonuniform. For example, Figure 1(b) shows five tracks that can be classified into two types (blue and green, resp.) based on the width constraints. e blue tracks have a larger width constraint and cover the whole design from bottom to top, while the green tracks have a smaller width constraint and only cover part of the design. Particularly, routing tracks can overlap with each other, and the distribution may be uneven. Such nonuniform routing track configuration imposes a great challenge to the bus routing.
Obstacles such as circuit components and power vias make bus routing even more challenging. Since such obstacles are scattered throughout certain layers, it is not possible to find continuous routable area if bus bits are not allowed to route between some of them.
Due to the high complexity of the routing problems, the routing process is typically divided into global routing, track assignment, and detailed routing. In global routing, the routing region is divided into coarse-grained grid cells (called g-cells), and rough routing regions are determined for each net through the connection between the g-cells.
Next, track assignment allocates routing tracks to iroutes that are extracted from the global routing result. Finally, detailed routing finds a path for each net to connect the iroute and pins and completes the final routing.
In this paper, we propose an effective algorithm to solve the topology-matching bus routing problem considering obstacles and nonuniform track configurations. e major contributions of our work are summarized as follows: (i) A track handling technique is presented to unify the nonuniform routing track configuration with obstacles.
(ii) We formulate the topology-aware single bus routing as an unsplittable flow problem (UFP), which is integrated into a negotiation-based global routing to determine the desired routing regions for each bus.
(iii) Under the guidance of the global routing result, a topology-aware track assignment is proposed to allocate tracks to each segment of buses, which significantly reduces the difficulty of maintaining the same routing topology in the subsequent steps. (iv) A detailed routing scheme considering routing topology for all bus bits is presented to connect the segments of each bus. (v) Experimental results show that our proposed bus routing algorithm is effective. Compared with the top 3 teams of the CAD Contest at ICCAD on Obstacle-Aware On-Track Bus Routing [5], our proposed algorithm can achieve the best overall score within the specified time.
e rest of this paper is organized as follows. Section 2 first introduces the bus routing preference metrics and then gives the problem statement. Section 3 details our bus routing algorithm. Section 4 provides the experimental results. Finally, conclusions are drawn in Section 5.

Preliminaries
In this section, we first introduce the bus routing preference metrics considered in the 2018 CAD Contest at ICCAD [5] and then formulate the topology-matching bus routing problem.

Bus Routing Preference Metrics.
For successfully routed buses, the metrics such as wire length, the number of segments, the width of each segment, and the number of spacing violations are used to measure the bus routing quality in the contest [5]. We detail these four metrics as follows.

Wire Length.
Wire length is a basic metric of routing quality. Longer wire lengths typically imply larger delays and larger power consumption [6]; hence routers are expected to minimize the wire length. e wire length of a bus is calculated by summing up the wire length of all bits, and taking detour will cause an increase in wire length.

Number of Segments.
Since each layer has a preferred routing direction (either horizontal or vertical), more segments indicate that more vias are used. However, vias are undesirable due to their negative impacts on signal integrity, delay, routing area, and manufacturing yields [6]. erefore, an ideal bus router should minimize the number of segments.

Width of Segments.
If the direction of a segment is horizontal, then the width of the segment is defined as the y-coordinate of the topmost wire in the segment minus the y-coordinate of the bottommost wire in the segment; in contrast, if the direction of a segment is vertical, the 2 Complexity calculation is between the x-coordinate of the rightmost and the leftmost wire [5]. e smaller the width of a segment is, the more compact the corresponding bus is.

Spacing Violation.
Each layer has a spacing constraint which specifies the minimum distance that should be maintained between the routing paths of a bit and the design boundary, the obstacles, and other routing wires on that layer. Spacing violation will result in an additional penalty in the evaluation score. Figure 2 shows an example of bus routing preference metrics, where Figure 2(a) gives an inferior routing result with a longer wire length, a large number of segments, and a larger width of segments, while Figure 2(b) gives a desired solution because its wire length and number of segments are minimized, and the width of segments is also smaller.

Problem Statement.
We are given the following: (1) A design with l routing layers L � L 1 , L 2 , . . . , L l . Each layer has a routing direction and a spacing constraint. e routing direction is either vertical or horizontal, and the spacing constraint specifies the minimum distance that should be maintained between the output routing path and the design boundary, the obstacles, and other routing wires in that layer. (2) A set of m routing tracks T � T 1 , T 2 , . . . , T m . Each track T i is represented by a line in a layer with a width constraint WT i . e direction of each track is always the same as the routing direction of the layer that the track is on, and the width constraint requires that only the wires with a width smaller than or equal to the width constraint can be routed on the track. e goal of topology-matching bus routing is to achieve as many successfully routed buses as possible, and the following metrics should also be minimized simultaneously: (1) the total wire length of all buses; (2) the number of segments; (3) compactness of each bus (i.e., the width of segments); (4) the number of spacing violations.
A bus is routed successfully if the following three hard constraints are met: (1) Routing paths of each bit connect all pin shapes of the bit and do not overlap with the paths of other bits. (2) All wires are on-track without violating the width constraint of the tracks and do not overlap with obstacles. (3) All bits are routed with the same topology.

Our Algorithm
e overall flow of our proposed algorithm is summarized in Figure 3, which mainly consists of four parts: (1) preprocessing, (2) global routing, (3) track assignment, and (4) detailed routing. e preprocessing stage unifies the nonuniform routing track configuration with obstacles to support efficient query and simplify subsequent routing operations. In the global routing stage, we formulate the topology-aware single bus routing as UFP and integrate it into a negotiation-based global routing to determine the desired routing regions for each bus. e complexity of subsequent steps can be reduced by confining its search space to the regions identified by the global routing stage. Under the guidance of the global routing result, the track assignment stage allocates tracks to each segment of buses, which significantly reduces the difficulty of maintaining the same routing topology in the subsequent step. Finally, the detailed routing stage connects the segments of each bus bit and obtains the final routing result. We shall detail these four major parts in the following subsections.

Preprocessing.
In this subsection, we perform some preprocessing on the input data to simplify subsequent routing operations. Since the nonuniform routing track configuration and obstacles make the bus routing much more complicated, we first present a track handling technique to unify the track configuration while considering obstacles. Specifically, we treat each routing track uniformly as covering the entire design from top to bottom (or left to right), and each track has a set of intervals for recording the subtracks that have been used. Furthermore, if the centerlines of two tracks overlap, we will shrink or delete the used intervals of the track that has a smaller width. Figure 4 shows three nonuniform routing tracks and an obstacle. In the figure, we treat these three tracks as covering the entire design from top to bottom, and tracks T 1 , T 2 , and T 3 have the sets of used intervals I 1 , I 2 , I 4 , and I 3 ,

Complexity
respectively. e interval I 1 is occupied by the obstacle, and intervals I 2 , I 3 , I 4 are not covered by the corresponding tracks. In addition, since the centerlines of tracks T 2 and T 3 overlap and the track T 2 has a smaller width, we update the set of used intervals of track T 2 by deleting the interval I 4 . en the set of used intervals of track T 2 is finally empty, and thus the wires can go through directly from track T 2 to track T 3 .
Besides, we adopt a minimum spanning tree algorithm to decompose each multipin bit into a set of two-pin bits and determine a preferred direction (horizontal or vertical) for each pin. at is, if the physical locations of the same pin shapes in different bits are horizontally distributed, then the preferred directions of the pin shapes are set as vertical; in contrast, if the physical positions of the same pin shapes in different bits are vertically distributed, then the preferred directions of the pin shapes are horizontal. e preferred direction of a pin is the desired direction of the wire that connects to the pin. For example, the preferred directions of all six pins in Figure 1(a) are horizontal, since the physical positions of the same pin shapes in different bits are vertically distributed.

Global Routing.
To determine the desired routing regions for each bus and reduce the complexity of subsequent detailed routing, we formulate the topology-aware single bus routing as UFP and integrate it into a negotiation-based global routing scheme. e three main steps of our global routing scheme are elaborated as follows.

Grid Graph Construction.
In the global routing stage, each routing layer is partitioned into a set of global cells (gcells) as shown in Figure 5(a), and a corresponding grid graph can be constructed as shown in Figure 5(b). In the grid graph, each vertex represents a g-cell and each routing edge represents a boundary between adjacent g-cells, and any two adjacent layers are connected by vias. In addition, the number on each routing edge of Figure 5(b) indicates the capacity of the edge, which corresponds to the number of routing tracks that can be contained across the edge. Since solving the 3D global routing problem directly is timeconsuming, we further project a multilayered design onto the 2D plane, and then a capacitated graph G(V, E, u) is constructed.
Besides, each pin corresponds to a g-cell. If two pins of any two bits are in the same g-cells, then we temporarily combine the two bits as a bit. In this way, we can reduce the number of bits in each bus greatly in global routing, and the runtime of the global routing stage will be reduced. Take Figure 5(a) for example. ere are two bits in a bus and each bit has two pins. Since the two pins of two bits are in the same g-cells, we combine the two bits as a bit, and the demand (number of tracks consumed) of each routed wire in the merged bit is 2.

Initial Solution Generation.
Too many bends of a routing path not only increase the number of vias, resulting in poor routing quality, but also make it more difficult to maintain the same routing topology due to the increase of the number of segments. erefore, we limit the number of bends in this initial solution generation step. e bits can be categorized into two types based on the preferred directions of pins. Figure 6(a) shows the pins of four bits from different buses with the same preferred direction, and the path connecting each bit has an even number of bends. Conversely, the pins of three bits from different buses shown in Figure 6(b) have orthogonally preferred directions, and the path connecting the two pins of each bit has an odd number of bends. Further, since we set a preferred direction for each pin, a bit has at most one path with one or zero bends, and we only need to determine n − 1 (n ≥ 2) bending points in turn to obtain a path with n bends.
In this step, the number of bends of a path connecting each bit is limited to four. For each bus, let d i represent the demand of bit i, P i denote the set of paths for bit i, and P T i represent the set of paths with the same routing topology T in P i . Note that, the topology in global routing ensures that (1) all bits have the same number of wires and (2) all wires traced from all bits route towards the same direction, while temporarily ignoring the relative order of the wire of different bits. In addition, for each P ∈ P i , we have a nonnegative variable x(P) and a weight w(P) associated with it. e weight w(P) of path P is the sum of the weights of all the edges on the path, and the weight of edge e is defined as where d(e) represents the sum of the demands of the bits passing through e and u(e) is the capacity of the edge e. For each edge e, the demand d(e) is initialized to 0 and is updated once a bus is routed successfully. e weight w(e) Complexity 5 decreases dramatically as the demand approaches the capacity but grows slowly in the undercapacity and overcapacity parts.
We determine the order of routing topology according to the number of bends and the weight of path w(P). A smaller number of bends have a higher priority.
For each bus, we try the topologies of the bus one by one until the bus is routed successfully. Further, we introduce a new variable x i for each bit i, where x i � P∈P T i x(P), and let u ′ be a copy of u. en, the global routing problem of the bus with topology T can be formulated as UFP as follows: In the formulated UFP, the objective is to maximize the number of routable bits, and the total weight of all selected paths is as large as possible (i.e., the congestion is as small as possible). e constraints in the first line ensure that at most one path is selected per bit, and the constraints of the second line limit the total demand of bits that can pass through each edge. u ′ will be increased if all the topologies of the bus fail to be routed. A bus is successfully routed if all bits of the bus are successfully routed (i.e., x i � 1, 1 ≤ i ≤ n bit ). Once a bus is successfully routed, we update the demand d(e) and weight w(e) of each edge e and then handle the next bus.
Based on the combinatorial algorithm for UFP in [7], Algorithm 1 provides an algorithm for problem (1). Let |E| � m and u min (u max ) be the minimum (maximum) edge capacity and d min , d max , w min , w max be the minimum/maximum demand/weight among all bus bits. In Line 1, we first partition the set of bits T into two disjoint sets T 1 and T 2 . T 1 consists of bits for which d j ≤ u min /2, and the rest of the bits are in T 2 . For each bit j and a given path P of bit j, we adopt F(j, P) in [7] to measure the weight gain relative to the added demand load. We set the lower bound α lb and the upper bound α ub on F in Line 3. e order of bits are sorted in Line 6, and then we handle the bits one by one to select a path for each bit in Lines 7-11. L j−1 (e) in Line 8 denotes the relative load of edge e after routing bit j. e time complexity of Algorithm 1 is O(n bit · |E P T |), where n bit is the number of bits in a bus and |E P T | is the number of edges of the paths that have the same routing topology T for the bus. In detail, as can be seen from Algorithm 1, Line 1 requires O(n bit ) time, Line 6 requires O(n bit · log(n bit )), and Lines 8-9 need O(|E P T |) time. Besides, since the number of loops in Line 2 and Line 4 is constants, the number of loops in Line 7 is n bit . Hence, Algorithm 1 requires O(n bit · |E P T |) time for each bus. Proof. Consider an optimal solution routing bits in Q⊆T. For each j ∈ Q, let Q j be the route chosen for j in the optimal solution. e total weight of either Q ∩ T 1 or Q ∩ T 2 is at least w(Q/2). Denote that set by Q ′ and its index by i ′ ∈ 1, 2 { }, and let α ′ � 2 k′ be the highest such that w( j ∈ Q ′ |F(j, Q j ) > α ′ }) ≥ w(Q)/4. Let Q high ′ � j ∈ Q ′ |F(j, Q j ) > α ′ } and Q low ′ � j ∈ Q ′ |F(j, Q j ) ≤ 2α ′ be sets of higher and lower quality routes in Q ′ . According to the definition of F, we have w(Q low ′ ) ≤ 2α ′ e 1 � 2mα ′ , where the inequality is true since an optimal solution cannot overflow an edge. erefore, we have w(Q) ≤ 8mα ′ . In addition, since F(j, P j ) > α ′ for every j ∈ P, according to [7], we have w(P) � α ′ e L l (e) ≥ (1/4) �� m √ α ′ . By combining the two inequalities, we get (w(Q)/w(P)) ≤ 32

Rip-Up and Reroute.
Rip-up and reroute is a basic routing technique and is usually combined with the negotiation technique. e negotiation-based rip-up and reroute is widely used in global routing [8,9], track assignment [10], and detailed routing [11] and has been shown to be effective and efficient to improve the routing quality.
At each rip-up and reroute iteration, we first identify and mark a set of buses with overflowed edges or excessive routing cost (equation (9)) that need to be ripped up and rerouted. Rerouting the buses that do not overflow but have excessive routing costs can not only reduce the routing cost but also free up routing resource for other overflowed buses. en, the marked buses are sorted in decreasing order based on the score defined as follows: where is the routing cost defined in equation (9), ne of (B i ) denotes the number of overflowed edges passed by bus B i in the previous iteration, and C 1 is a user-defined parameter which is set as α + β + c.
In addition, the history-based cost function for each routing edge e in [8] is adopted, which is defined as where b(e) is the wire length cost, h(e) is the history cost, p(e) is the current penalty cost, h(e) × p(e) denotes the congestion cost of edge e, and vc(e) is the via cost. e weight of edge e is set as w(e) � (1/cost(e)), and we reroute a bus by solving problem (2).
We repeat the rip-up and reroute process until there is no overflowed edge or excessive routing cost or the given maximum number of iterations is reached. Since we reroute a bus by solving the UFP (2) and the required runtimes is O(n bit · |E P T |), the rip-up and reroute stage requires O(n rb · n bit · |E P T |), where n rb is the total number of buses that need to be ripped-up and rerouted.
After obtaining a 2D global routing solution, we extend the layer assignment method in [12] to map the solution from the projected plane to the original multiple layers. Note that, within each segment of a bus, we ensure that the wires of different bits are assigned to the same layer.

Track Assignment.
After obtaining desired routing regions for each bus in the global routing stage, we propose a topology-aware track assignment in this subsection to allocate tracks to each segment of buses under the guidance of the global routing result. In this track assignment stage, we treat the array of all g-cells in a row or column of a routing layer as a panel, and each straight wire that passes through one or more g-cells is regarded as an iroute.

Initial Track Assignment.
Since all bits in each bus need to be routed with the same routing topology, we handle the buses one by one to assign the tracks to each segment. For each bus, each segment consists of the set of iroutes of different bits that have the same sequence when traced from source pin to sink pin.
In order to maintain the relative order of the iroutes in each segment, our initial track assignment for each segment is as follows. First, we sort the iroutes of each segment in the same order or in the reverse order of bits. Both orders are tested because the results of each order may be different, and the best results are adopted. en, based on the sorted order, for each iroute, we collect the valid tracks in the panels and calculate the cost of assigning the iroute to each valid track. A track is valid if the width constraint of the track is greater than or equal to the wire width of the iroute. Finally, we select a valid track with the minimum cost to accommodate the iroute. e cost function for assigning the iroute ir to the track t is defined as where cost(ir, t) is the total cost of assigning track t to iroute ir, wl(ir, t) is the wire length cost, ol(ir, t) is the overlap cost, blk(ir, t) is the blocked interval cost, cp(ir, t) is the compactness cost, and C 2 , C 3 , and C 4 are the user-defined constants which are set as 0.2, 1000, and 1, respectively. e definition of wire length cost is adopted from the work [10]. Because the routing tracks may be nonuniform or even overlapping, the overlap cost of an iroute being assigned to a track is modified from the work [10], which is determined not only by the overlapping iroutes on that track but also by the overlapping iroutes on other tracks. In addition, since some tracks may only cover a partial design, the blocked interval cost is the sum of blockage cost defined in [10] and the length of the iroute ir that is not on the tracks. According to the 2018 CAD Contest at ICCAD [5], the wires of all bits in a bus should be as compact as possible. us, we define the compactness cost to make each bus more compact and reserve more free space for other buses. Figure 7 illustrates the calculation of the compactness cost. We assume without loss of generality that the panels are horizontal. For the first and last segments of each bus, since the iroutes eventually need to be connected to the corresponding pins in the detailed routing stage, the compactness cost is set as the vertical distance between the iroute and the corresponding pin. For example, Figure 7(a) shows the first segment of a bus, where pin p 1 and iroute a 1 belong to the first bit and pin p 2 and iroute a 2 belong to the second bit. e compactness costs of iroute a 1 on tracks T 1 , T 2 , and T 3 are 0, d 1 , and d 1 + d 2 , respectively, and the compactness costs of iroute a 2 on tracks T 1 , T 2 , and T 3 are d 1 + d 2 , d 2 , and 0, respectively.
For the rest of the segments in the bus that do not need to connect pins, the compactness costs of the iroutes are related to the order in which the iroutes of bits are assigned. If we handle iroute a 1 before iroute a 2 in Figure 7(b), the compactness cost of each iroute is the vertical distance between the iroute and the upper boundary of the panel. Conversely, if we handle a 2 before a 1 , then the compactness cost of each iroute is the vertical distance between the iroute and the lower boundary of the panel. In addition, if the iroutes of a segment are distributed in multiple panels as shown in Figure 7(c), the compactness cost of each iroute in the bottommost panel is the vertical distance between the iroute and the upper boundary of the panel, the compactness cost of each iroute in the topmost panel is the vertical distance between the iroute and the lower boundary of the panel, and the compactness cost of each iroute in the rest panels is 0.

Rip-Up and Reassignment.
After the initial track assignment, there may be overlaps between the iroutes. erefore, we extend the negotiation-based track assignment in the work [10] to minimize the overlaps and wire length while keeping the relative order of the iroutes in each segment. e cost function for reassignment is defined as cost his (ir, t) � θ wl · wl(ir, t) + θ ol · ol(ir, t) where wl(ir, t), ol(ir, t), blk(ir, t), and cp(ir, t) are the same as the definition in equation (5), and his(ir, t) is the history cost from the work [10]. e user-defined parameters θ wl , θ ol , θ blk , θ cp , and θ his are used to balance the cost components. Both θ wl and θ cp are initialized as 1 and gradually decreased to 0.1 as the iteration increases, and θ ol is initialized as 0.1 and gradually increased to 1 as the iteration increases. Besides, θ blk is a very large constant and θ his is set as 1. rough the control of these parameters, we can reduce the overlaps with less wire length and compactness cost at early iterations and focus more on overlap reduction at late iterations.
In order to maintain the same topology for all bus bits, we always keep the relative order of the iroutes in each segment during the rip-up and reassignment stage. However, reassigning an iroute while keeping the relative order of iroutes in the segment may fall into a local optimum, due to the fact that the solution space is limited and we may always select the same set of iroutes or always try to assign an iroute to a small set of tracks. erefore, in each iteration, we may rip up and reassign multiple iroutes to reduce the probability of falling into local optimum. Specifically, when an iroute has no other tracks that can be assigned to or these tracks have been tried several times by this iroute, we will also rip up and reassign some of the iroutes that adjacent to this iroute. e time complexity of reassigning an iroute is O(n pt ) at each iteration, where n pt is the number of tracks in the panel that the iroute is located. Since we may rip up and reassign multiple iroutes simultaneously to reduce the probability of falling into local optimum, if we handle k iroutes simultaneously, the time complexity is O(n k pt ). However, since n pt is not too large (tens to hundreds) and we set k as 3, the running time of this stage depends mainly on the number of iroutes that need to be reassigned. 8 Complexity For example, assume that iroute a 2 in Figure 7(c) needs to be reassigned. Since the relative order of the iroutes of different bits in a segment should be maintained, iroute a 2 can only be placed between iroute a 1 and iroute a 3 . at is, if iroute a 1 is not reassigned to another track, then iroute a 2 cannot be reassigned. erefore, we rip up both the iroutes a 1 and a 2 , and then iroutes a 1 and a 2 can be reassigned to the tracks T 1 and T 2 , respectively.

Detailed Routing.
After track assignment, we need to connect the components of each bit to obtain the final routing result. A bit component is a pin or an iroute of the bit. Algorithm 2 gives the framework of our detailed routing. In Line 3, in order to preserve the same routing topology for all bus bits and honor the global routing result, the components of each bit are sorted according to the trace order of global routing paths from the source pin to the sink pin, and then we only need to connect the adjacent components of each bit one by one.
In Line 4, we adopt L-shaped [13], Z-shaped [13], and the 3-bend routing [14] to connect the adjacent components, because it is easy to control the same topology for all bus bits and is very efficient by using these predefined pattern routing. After that, we use two-stage negotiation-based ripup and reroute to iteratively improve the solution quality in Lines 8-16. ite1 and ite2 in Line 8 indicate the maximum number of iterations for the first stage and the second stage of rip-up and reroute, respectively. In the first stage, we rip up every two adjacent components that have the overlapping wires and reroute them through the patterns routing while maintaining the same routing topology. After each iteration, we increase the history cost of the overlapped interval on a track according to the number of overlapped wires. As a result, a track with a higher history cost tends to have less chance to be routed, and the bits with alternative routes are forced to use other tracks. In the end, the bit that most needs to use this track will eventually use it.
Since the limited search space of the patterns routing and only allowing to rip up and reroute the adjacent components in the first stage rip-up and reroute, it is possible to reduce the wire overlap if some restrictions are removed. In the second stage, we use the A * algorithm [15] to search for the paths and allow paths to be outside the global routing guide. In addition, we also allow some iroutes extracted in the track assignment stage to be removed, thus increasing the freedom of routing. For example, if we remove the second component of a bit, then we are required to find a path to connect the first component and the third component. When a part of a bit is rerouted, we check whether other bits in the bus are the same as its topology. If not, we will adjust the routing paths of other bits based on the path of that bit. We repeat the ripup and reroute process until all the buses are routed successfully or the given maximum number of iterations is reached.
Finally, we construct a conflict graph in which each bus is regarded as a vertex, and each edge represents the conflict between two buses. We iteratively rip up the bus (vertex) with the largest degree and its associated edges until there are no conflict edges in the graph, and the final routing result is obtained.

Experimental Results
To evaluate our proposed bus routing algorithm, we implemented our algorithm in the C++ programming language and tested it on the benchmarks (including the hidden cases) of the 2018 CAD Contest at ICCAD on Obstacle-Aware On-Track Bus Routing [5]. Table 1 lists the benchmark statistics, where "#Layer," "#Track," "#Obstacle," "#Bus," "#Bit," and "#Pin" give the total numbers of layers, tracks, obstacles, buses, bits, and pins, respectively. e score function in the contest [5] is adopted to evaluate the quality of bus routing results, which consists of routing cost C r , spacing violation penalty P s , and fail routing penalty P f . at is, Pin Track Iroute S � C r + P s + P f . (7) e three parts of the score function are calculated as follows: where α, β, c, δ, ε are five weighting parameters given in the input data, and the values of these parameters may vary from different benchmarks. For each bus B i , the wire length cost C w (B i ), the segment cost C s (B i ), and the compactness cost C c (B i ) are defined as follows: Ideally, if a bus B i is routed with the minimum wire length (C w (B i ) � 1) and the minimum number of segments (C s (B i ) � 1) and all segments are routed with widths close to the lower bound (C c (B i ) � 1), then the routing cost C r of the perfectly routed bus is close to α + β + c.
e experimental results of the top 3 teams of the 2018 CAD Contest at ICCAD [5] and ours are listed in Table 2. Our algorithm was run on a Linux workstation with a 2.40 GHz Intel Xeon CPU and 64 GB memory, and the results of top 3 teams of the contest are provided by the contest organizer. Since the binaries of top 3 teams are not available for us, we do not report their runtime. Nevertheless, the specified time for each test case is one hour according to the contest [5], and our program will be killed if the runtime exceeds the specified time.
In Table 2, the columns "First place," "Second place," " ird place," and "Ours" give the corresponding routing results generated by the first place, second place, and third place of the contest [5] and our algorithm, respectively. e latest evaluation script (eval_1.0-a8) provided by the contest [5] was used to obtain the routing cost "C r ," spacing violation penalty "P s ," fail routing penalty "P f ," and score "S." It can be seen from Table 2 that all the buses are successfully routed by our algorithm for the tested cases beta 1, beta 2, beta 3, and beta 4. Particularly, on average, our algorithm outperforms the top 3 teams by 9%, 124%, and 357% in the final scores, respectively. e experimental results show that our proposed bus routing algorithm is effective.

Conclusions
In this paper, we have presented an effective algorithm to solve the topology-aware bus routing problem considering the existence of both nonuniform track configuration and obstacles. We first presented a track handling technique to unify the nonuniform routing track configuration together with obstacles. en, we have formulated the topologyaware routing problem of single bus as UFP, which is integrated into a negotiation-based global routing problem of determining the desired routing regions for each bus. Moreover, we presented a topology-aware track assignment method which can allocate the tracks to each segment of buses regarding the guidance of the global routing result. Lastly, a detailed routing scheme has been presented to connect the segments of each bus. We have evaluated our routing results with ICCAD benchmark suites. Compared with the state-of-the-art methods, the experimental results have shown that our proposed method achieves the best overall score within the specified time.
Data Availability e data used in this study can be accessed via http://iccadcontest.org/2018/problems.html.

Conflicts of Interest
e authors declare that they have no conflicts of interest.