An FPGA-Based PID Controller Design for Chaos Synchronization by Evolutionary Programming

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Introduction
In recent years, chaos synchronization has attracted the interest of researchers in various fields 1 .Chaos synchronization has many potential applications in physics and engineering and particularly in secure communication 2 .The idea of synchronizing two identical chaotic systems was first introduced by Pecora and Carroll 3 .In continuous-time chaotic systems, synchronization is usually achieved by a master-slave or drive-response approach.Given a master drive and slave response in a chaotic system, the goal is synchronizing the behavior of the slave response system to that of the master drive system.To achieve the synchronization, a nonlinear controller must be designed to obtain signals from the master and slave systems and to manipulate the slave system.Recently developed control methods can achieve chaos synchronization between two identical chaotic systems with different initial conditions 1 .However, none of the proposed methods in our surveyed papers can obtain an optimal or near-optimal digital controller for synchronizing continuous chaotic systems according to a performance index specified by an FPGA chip.
Conversely, evolutionary programming EP algorithms have proven effective and easy to implement for global optimization of complex functions and for solving complex control problems in engineering 4, 5 .Generally, the four steps in the global optimization algorithm are initialization, mutation, competition, and reproduction.Furthermore, Cao 4 also developed a quasirandom sequence QRS for generating an initial EP population that avoids formulating clusters around an arbitrary local optimal.
In fact, implementing this technique in digital electronic devices such as field programmable gate arrays FPGAs can accelerate the development of prototype circuits such as control and real-time simulation circuits 6 .The FPGA comprises thousands of logic gates, some of which are grouped into a configurable logic block CLB to simplify higherlevel circuit design.Because of its simplicity and programmability, the FPGA is the preferred option for chip prototype design.
The main objective of this work was to develop an EP-based digital PID control scheme for solving synchronization problems in FPGA-based chaotic systems.The EP algorithm derived optimal control gains in PID-controlled chaotic systems such that the performance index of integrated absolute error IAE was minimized and the master and slave chaotic systems were synchronized.The optimal architecture for digital controller was then implemented and simulated by very high-speed description language VHDL and ModelSim.The developed architectures for each component were then implemented and tested under the Xilinx Spartan-3 FPGA.Finally, simulation and experimental results were compared to confirm the effectiveness of the proposed EP-based digital PID scheme for chaos synchronization.

System Description and Problem Formulation
First, consider two single-input single-output SISO master and slave systems described by the following differential equations: Master system: The y m t ∈ R and y s t ∈ R are the outputs of the master and slave systems, respectively.The B ∈ R n×1 and C ∈ R 1×n are the system matrices.The u t ∈ R is the control input included in the slave system 2.2 to synchronize the master and slave systems.Generally, many chaotic systems can be expressed by 2.1 .For example, the Sprott circuit, the modified Chua's circuit, the Duffing-Holmes system, the Lorenz system, and the Lu system all belong to the class defined by 2.1 .
Let the error states be e 1 x m1 − x s1 , e 2 x m2 − x s2 , . . ., e n x mn − x sn .The objective of this study was to use the EP algorithm to design a simple but effective PID controller u t that can synchronize coupled systems 2.1 and 2.2 under different initial conditions such that lim The procedure for determining the PID controller u is to first define the output error signal y e y m − y s and then to define the continuous form of a PID controller with input y e • and output u • .The conventional equation is where K p is the proportional gain constant, T i is the integral time constant, and T d is the derivative time constant.When using the FPGA chip to implement this controller, the continuous-type PID controller 2.4 is reformulated as a digital-type PID controller as shown below: Here, u k is the kth sampling output data of the PID controller, S k y e k is the error sum, and T is the sampling time constant.Therefore, 2.5 can be rewritten as where The performance criterion or objective function of a controller design can generally be defined according to the desired specifications.The two performance criteria typically considered in the EP algorithm are the integrated squared error ISE and the integrated absolute error IAE .This study uses the IAE index as the objective function OF , which is given as where E k e 1 , e 2 , . . ., e n , • is the Euclidean norm of a vector, k is the sampling time point, and k f is the total number of samples.Below, the EP algorithm is used to minimize the objective function score 2.7 by tuning the digital PID controller and optimizing the gain parameters.

Evolutionary Programming (EP) Algorithm for Solving the Optimization Problem
Since the EP algorithm is considered an easily implemented and promising technique for the global optimization of complex functions, this study introduces an EP algorithm for solving this problem.Figure 1 shows the proposed EP-based PID control system includes synchronized master and slave chaotic systems, a PID controller, and an EP algorithm.The y m is the output of the master system, y s is the output of the slave system, and u is the control input generated by the PID controller as defined in 2.5 .The parameters of the proposed PID controller are derived by the EP algorithm such that the value of IAE given in 2.7 is minimized.This section proposes an extended EP algorithm for obtaining the digital PID controller with optimal gain parameters to minimize the following objective function OF score 2.6 .Let g be the continuously differentiable matrix-valued function defined for g ∈ S, where S {g ∈ R 3 | 0 ≤ g i ≤ M i , i 1, 2, 3} and M i is the bounded search space.The optimization problem is to find g * K * p , K * i , K * d ∈ S such that the OF performance index of the system is minimized.Mathematically, the optimization problem P1 can be formulated as follows.
P1 : To find g * ∈ S such that OF IAE Based on the simulation results obtained in 4 , an extended EP algorithm for solving the above optimization problem is applied as follows.
Step 1. Generate an initial population P 0 p 1 , p 2 , . . ., p N of size N by randomly initializing each 3-dimensional solution vector p i ∈ S, i 1, 2, . . ., N according to the quasirandom sequence QRS .Step 2. Calculate the fitness score objective function f i f p i for each p i , i 1, 2, . . ., N, where

3.2
Step 3. Mutate each p i , i 1, 2, . . ., N, based on the statistical data to double the population size from N to 2N, and generate p i N by using where p i,j denotes the jth element of the ith individual, N 0, βf i /f Σ represents a Gaussian random variable with a mean zero and variance βf i /f Σ , f Σ is the sum of all fitness scores, and β is a parameter to scale f i /f Σ .
Step 4. Use 3.2 to calculate the fitness score f i N for every p i N , i 1, 2, . . ., N. In the stochastic competition process, p i , i 1, 2, . . ., N randomly competes with p j , j N 1, . . ., 2N.If f i < f j , p i wins; otherwise, p j wins, and p i is replaced by p j .After completing the competition process, select N winners for the next generation, and let the individual with the minimum objective function in the winners be p 1 .
Step 5.If the value f Σ converges to a minimum value, then let g * p 1 be the global optimum value and g * K * p , K * i , K * d such that the OF performance index of the system is minimized.Otherwise, return to Step 3.

Simulation and Experimental Results
This section describes the proposed EP-based digital PID controller design for synchronizing Sprott circuits, which are the chaotic systems typically studied in the literature 7, 8 .Now consider the following Sprott circuits: Master:

4.1
Slave: where ẋm and ẋs denote the derivatives of x m and x s , respectively, with respect to time t.
In this example, the initial conditions for master and slave are x m1 0 , x m2 0 , x m3 0 0.1 0.1 0.1 and x s1 0 , x s2 0 , x s3 0 −1 − 1 − 1 , respectively.Matlab and Simulink are used to solve the optimization problem P1 , where N 30 and β 0.001.The proposed EP algorithm generates P 0 p 1 , p 2 , . . ., p 30 according to the QRS.Several manipulations of the EP algorithm gets the convergence curve of IAE value versus iteration depicted in Figure 2.  x m 2  Figure 4 shows the output response when using the resulting PID control gain z * .The simulation results confirm that the EP algorithm and proposed PID controller effectively synchronize Sprott chaotic systems.The proposed PID controller was then tested in an actual system.Figure 5 8 shows the experimental results when 4.1 and 4.2 were applied in a circuit connected in a master/slave configuration.Figure 6 shows how the controller was implemented with Xilinx Spartan-3 FPGA and AD/DA converters and a 1289 kHz sampling rate.Figure 7 shows that the slave circuit response was synchronized to the master circuit response after the control was activated at t 20 second.The experimental results of error dynamics in Figure 7 d show the convergence to a very small synchronization error.

Conclusions
A simple and successful digital PID controller for an FPGA chip was proposed for using an evolutionary programming algorithm to synchronize two chaotic systems.The derived

Figure 1 :
Figure 1: Block diagram of chaos synchronization system.

Figure 4 :
Figure 4: Time responses using the EP-based PID controller.a x m1 versus x s1 .b x m2 versus x s2 .c x m3 versus x s3 .d The error states e 1 , e 2 , e 3 .e The control input.The control u t is activated at t 20 sec. .

Figure 2
Figure 2 clearly shows that convergence occurs after about 170 iterations, and the final value of IAE is f g * 0.7592.The corresponding PID control gains are g * K * p , K * i , K * d 20 0.0018 20 .Figure 3 also shows the K p , K i , and K d trajectories during the evolutionary procedure.Figure4shows the output response when using the resulting PID control gain z * .The simulation results confirm that the EP algorithm and proposed PID controller effectively synchronize Sprott chaotic systems.The proposed PID controller was then tested in an actual system.Figure58 shows the experimental results when 4.1 and 4.2 were applied in a circuit connected in a master/slave configuration.Figure6shows how the controller was implemented with Xilinx Spartan-3 FPGA and AD/DA converters and a 1289 kHz sampling rate.Figure7shows that the slave circuit response was synchronized to the master circuit response after the control was activated at t 20 second.The experimental results of error dynamics in Figure7d show the convergence to a very small synchronization error.
R n are the state vectors of master and slave systems, respectively.The f : R × R n → R n is a given nonlinear function.