A Process Optimization Method of the Mini-LOCOS Field Plate Pro ﬁ le for Improving Electrical Characteristics of LDMOS Device

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Introduction
Recently, the semiconductor industry has been extending rapidly to artificial intelligence, the Internet of things, biology, and automotive fields over the current area.The laterally diffused metal oxide semiconductor (LDMOS) devices play increasingly implant roles in power management integrated circuits (PMICs).The PMICs fabricated with the bipolar-CMOS-DMOS (BCD) process own the advantages of highpower density, high speed, and easy integration [1,2].Many researches have been published about LDMOS performance enhancement [3,4].For example, Hebert et al. [4] majorly focus on specific on-resistance performance improvement, and Gavoshani and Orouji [3] can effectively improve device robustness, including both the self-heating effect and breakdown voltage through a novel triple oxide trench deep gate LDMOS structure.
There are also many research works about novel structures, including surrounded stress dielectric layer LDMOS [2], folded accumulation LDMOS [5], optimized high-temperature oxide field plate, and the decoupled plasma nitridation LDMOS [6], H-shape shallow-trench isolation (STI) field plate LDMOS [7], or even silicon-on-insulator LDMOS [8], and high breakdown voltage devices with new material Ga 2 O 3 [9].These papers provided certain innovative device structures with encouraged R on,sp or BV ds,max performance by simulation results or small amounts of electrical results.However, these structures will bring in a very complex fabrication process and high cost for production.Basically, these ideas are still in the early phase of production and have a long way to step into the large-scale production of integrated circuits.
Therefore, according to the advantages of simple process, low cost, good compatibility, and high reliability, the conventional LDMOS, with the mini-LOCOS field plate structure, is still the first choice for high-performance PMICs chips mass production [10,11].However, the mini-LOCOS field plate has a complex physical profile, such as an inherent "abrupt" bottom surface, which will lead to breakdown voltage degradation of the final LDMOS device.Therefore, it is of great practical significance for further study and optimization of existing mini-LOCOS field plate processes.
In this paper, an effective process method for mini-LOCOS field plate bottom surface optimization is proposed.The measurement results indicate that the structural profile of the mini-LOCOS field plate has been obviously improved, and the electrical performance, including the figure of merit (FOM) and safe operation area (SOA) curves, is improved accordingly.The principle of the mini-LOCOS field plate technology is shown in Section 2. The experiments and results are shown in Section 3. A conclusion is drawn in Section 4.

Studies on "Abrupt" Field Plate Profile
2.1.Process Observations.A brief schematic of the LDMOS [12] device with a mini-LOCOS field plate is shown in Figure 1.During the high-performance BCD platform development in 12-inch Can.-FAB to fabricate the mini-LOCOS field plate, a hard mask approach is applied for field plate photo and etching before high-temperature thermal oxidation.Under this process condition, an inherent defect, called an "abrupt" profile, is observed on the bottom surface of the mini-LOCOS field plate, as shown in Figure 2.
Specific description as follows: the oxide thickness of the mini-LOCOS field plate changes not so smoothly, and an "abrupt" physical profile occurs, which will cause additional charge accumulation Q A at the bottom surface.Breakdown voltage degradation will be the side effect of Q A at the "abrupt" location.The related analysis will be raised in Section 2.2.
It is a pity that physical profiles such as transmission electron microscope (TEM) or scanning electron microscope images about mini-LOCOS field plates are not sufficient from published papers.However, the authors still suspect the "abrupt" profile should be a common issue through related industry experiences and some undisclosed benchmark data from other LDMOS device vendors.Another supporting data are the electrical data enumerated in Sections 3.3 and 3.4, which indicate the device FOM performance from the reference vendors still needs to be improved.Thus, our work on process optimization can address the current BCD manufacturing industry with more process solutions.

Theory Analysis.
The source-drain breakdown voltage of this device in Figure 1 mainly depends on the electric field distribution of the drift region under the mini-LOCOS field plate [13].
For all types of LDMOS devices with oxide field plate, such as mini-LOCOS field plate, mini-STI field plate, and high-temperature oxide field plate, the source-drain breakdown voltage can be qualitatively expressed [14] as follows: where V ds is the source-drain breakdown voltage of the device, t ox the oxide thickness of the mini-LOCOS field plate, E si the electric field in the Si substrate when the PN junction breaks down, V FB the flat band voltage of LDMOS, V GS the gate bias, V A the potential at the location A, which close to the bottom surface of the field plate, cosT the normal component of the potential shift-vector.As signified in Figure 3, take the dielectric constant of oxide ε ox = 3.9, the dielectric constant of silicon ε Si = 11.5, and minimum electric field E SiO 2 is acquired when cosT 2 = 1, then we can get the relationship between E SiO 2 and E si : Further, V A can be expressed approximately as follows: where C ox is the normalized capacitance.Considering the thickness t ox variation of different locations of the mini-LOCOS field plate, an integral calculation needs to be carried    IET Circuits, Devices & Systems out along the bottom surface of the field plate, thus Equation (1) and can be extended as follows: where L is the perimeter of the bottom surface of the mini-LOCOS field plate, W is the width of the mini-LOCOS field plate.Combine Equations ( 1) and (2) into Equation ( 3), the relation between maximum source-drain breakdown voltage BV ds;max and the mini-LOCOS field plate oxide thickness t ox and carrier accumulated Q A can be expressed as follows: In other words, the source-drain breakdown voltage BV ds,max does not only depend on the thickness t ox of the oxide from the mini-LOCOS field plate but also depends on the charging accumulation Q A at the bottom surface location and the negative charge accumulation induced by the "abrupt" profile should be eliminated.

Technology Computer-Aided Design (TCAD) Simulation.
For further study on the effects of "abrupt" field plate bottom profile on device performance, TCAD simulation [11,15] is carried out with the 2-D models of Sivaco software.
Figures 4(a) and 4(b) illustrate the doping profile at the "initial state."The "initial state" means no bias forced on the devices, V g = V ds = 0 V.At the "initial state," a flat doping profile is considered an ideal profile due to it means less charging accumulation.From Figure 4(c), the comparison results between the "abrupt" field plate and "smooth" field plate, it can be seen the "abrupt" field plate doping profile is not so flat from point "A" to point "B" along the X-axis.Therefore, the doping profile from an "abrupt" field plate could certainly be done with an optimization.
Figures 4(d) and 4(e) illustrate the electric fields at the "off-state," and the "off-state" means high voltage forced to the drain terminal, while the gate terminal and source/body terminal keep zero bias, V gs = 0 V, V ds = breakdown voltage.
At the "off-state," a lower electric field peak is considered a good distribution due to the higher breakdown voltage that can be acquired.From Figure 4(f ), the comparison results between the "abrupt" field plate and the "smooth" field plate, it can be seen the "abrupt" field plate owns a higher electric field at point B. Postoptimization, the electric field peak value from the "smooth" field plate decreases by around 6.3%.That is the reason why "smooth" profile yields higher breakdown voltage.What is more, as shown in Figure 4(d), at the silicon surface and the bottom corner of field plate, electric field spike is observed, which is also an indication for lower breakdown behaviors in "abrupt" field plate.

Experiments and Results
3.1.Experiments.Figure 5 is the brief 153 nm BCD process flow in Can.-FAB, which includes seven steps: Step (1) Deep N-well isolation with an extra high-energy (higher than 3,000 keV) implant, followed by high temperature (higher than 1,100°C) and longtime (more than 4 hr) drive-in.
Step (3) Drift region implant.Normally, there is no call for additional thermal post this step implant.However, the thermal budget of the following oxidation process, including oxidation/rapid time anneal, etc., should be carefully considered for drift region design.
Step (4) Field plated process.Here, the conventional but low-cost, high-quality mini-LOCOS process is used.
Step (6) Light doping drain module, then oxide-Si 3 N 4 -oxide spacer, source/drain engineering process.Step (7) Back end of the line connection with AlCu metal.
The process of the mini-LOCOS field plate is the most critical process [16,17].It can be divided into six steps: Step (1) ∼200 A pad oxide deposition.
Step (4) Field plate pattern dry etching is shown in During these process steps, Step (4), dry etching, is the key process.This process has a great impact on the final field plate bottom surface.The reason is that the silicon surface can be easily damaged by the plasma process during dry etching, and then the following oxide growth behavior will be changed accordingly.
Thus, design of experiments (DOE) about silicon loss is designed as shown in Table 1: (1) Group 1 is the control group with baseline production process conditions, and the silicon loss is around 200 A; (2) Group 2 is the bias power reduction group.12

Physical Results.
Taking the silicon substrate boundary as the reference plane, as described in Figure 7(a), the upper angle of the field plate is defined as θ 1 , and the angle of the bottom surface is defined as θ 2 .The thickness of the upper field plate and bottom field plate are defined as H up and H bottom , respectively.The oxide thickness ratio H up /H bottom and the bottom surface θ 2 are calculated as the factors for field plate bottom profile characterizations.Obviously, a higher ratio of H up /H bottom and higher angle θ 1 stands for a smoother bottom surface profile.Figure 7(a) illustrates the physical results from four DOE groups; it can be seen Group 4 owns the best field plate structure.Compared with the baseline result of Group 1, the angle of the bottom surface θ 2 is improved from 11.9°t o 12.6°, while the angle of the upper surface θ 1 nearly no change.Meanwhile, the oxide thickness ratio H up /H bottom increases from 71.8% to 76.6%.An "abrupt free" field plate has been produced successfully.IET Circuits, Devices & Systems  Figures 7(b) and 7(c) illustrate the silicon loss effects on H up /H bottom and θ 1 : from the "0" silicon loss point, both H up / H bottom and θ 1 begin to increase obviously.The possible reason is that "0" silicon loss means no plasma damage on the silicon surface, and then the diffusion of H 2 and O 2 to the silicon surface under Si 3 N 4 film becomes easier and smoother.Thus, "0" silicon loss is a fundamental requirement for the "abrupt free" field plate profile.
Figure 8 illustrates the FOM curves of N-type LDMOS, and the data are listed in Table 2.It can be seen that the process-optimized devices achieve much better electrical performance, even better than that of 130 nm devices [18].Take the same production line (red line and green line); the specific on-resistance R on,sp can be improved by about 19.3% (at the same breakdown voltage of 37.4 V).With no doubt, the field plate bottom physical optimization contributes to the electrical enhancement.
Furthermore, Figure 9 illustrates the SOA results of a typical 24 V device.The SOA curves are measured under a transmission line pulse (TLP) environment, and the test condition is that the pulse width of the TLP V ds is 100 ns with an external capacitance C gs = 10 nF.The drain current I ds are measured under a variable V gs from 0 V to 1.1 × V dd .
From the comparison with Kim et al. [6], it can be seen that our device owns a better (or called larger) SOA region, which is also an indication of the robustness of the optimized process condition.

Conclusions and Discussion
Though mini-LOCOS LDMOS is popular, researches on this type of device is still on track, and optimization works on the inherent defect, "abrupt" bottom field plate surface, is with great significance.The impact of the field plate physical profile on LDMOS electrical performance, especially for BV ds, max , is theoretically analyzed and simulated in this paper.An  IET Circuits, Devices & Systems effective optimization process by etching bias power and time reduction is proposed, and it is proved by TEM cut samples through the analysis of thickness ratio H up /H bottom and bottom surface angle θ 2 .Finally, the optimization condition has been implemented in our real BCD circuit production line, series of LDMOS are measured, and R on,sp of typical 24 V N-type device achieves as low as 11.3 mΩ mm 2 while BV ds,max arrives at 37.4 V. From the FOM curves analysis, specific on-resistance R on,sp performance is improved around 19.3%.From the I-V curves measurement under the TLP environment, a larger SOA window is acquired as well.Beyond this work, there are still other studies that need to be carried out for future production improvement, including how to eliminate the "convex" upper profile on the field plate and how to integrate the mini-LOCOS field plate with the mini-STI field plate together.These works call for great industry line efforts, but they can bring us promising industry easily.

FIGURE 2 :
FIGURE 2: Inherent defect on the bottom surface of mini-LOCOS field.

FIGURE 3 :
FIGURE 3: Electric field at silicon and oxide interface.

FIGURE 7 :
FIGURE 7: Effects analysis of the field plate profile: (a) TEM result of mini-LOCOS field plate profile; (b) effects of silicon loss on field plate lower profile through H up /H bottom ; (c) effects of silicon loss on field plate lower profile through θ 1 and θ 2 .

FIGURE 9 :
FIGURE 9: SOA of 24 V LDMOS with optimized min-LOCOS field plate.

TABLE 1 :
Experiments design for field plate profile optimization.

TABLE 2 :
Electrical parameter for 130-350 nm LDMOS devices with mini-LOCOS field plate.