IJAPInternational Journal of Antennas and Propagation1687-58771687-5869Hindawi Publishing Corporation94897210.1155/2012/948972948972Research ArticleFull-Wave Analysis of Traveling-Wave Field-Effect Transistors Using Finite-Difference Time-Domain MethodNaraharaKoichiYuanNingGraduate School of Science and EngineeringYamagata University4-3-16 JonanYonezawaYamagata 992-8510Japanyamagata-u.ac.jp20121512012201227062011240920112012Copyright © 2012 Koichi Narahara.This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Nonlinear transmission lines, which define transmission lines periodically loaded with nonlinear devices such as varactors, diodes, and transistors, are modeled in the framework of finite-difference time-domain (FDTD) method. Originally, some root-finding routine is needed to evaluate the contributions of nonlinear device currents appropriately to the temporally advanced electrical fields. Arbitrary nonlinear transmission lines contain large amount of nonlinear devices; therefore, it costs too much time to complete calculations. To reduce the calculation time, we recently developed a simple model of diodes to eliminate root-finding routines in an FDTD solver. Approximating the diode current-voltage relation by a piecewise-linear function, an extended Ampere's law is solved in a closed form for the time-advanced electrical fields. In this paper, we newly develop an FDTD model of field-effect transistors (FETs), together with several numerical examples that demonstrate pulse-shortening phenomena in a traveling-wave FET.

1. Introduction

The generation of a short electrical pulse with picosecond duration is one of the keys to producing a breakthrough in high-speed electronics. The applications of short pulses include measurement systems with picosecond temporal resolution, over-100-Gbit/s communication systems, and submillimeter-to-teraherz imaging systems . We recently found that a transmission line periodically loaded with resonant tunneling diodes (RTDs) greatly compresses the temporal width of the pulse input to it . Once the input pulse crosses the peak voltage of the loaded RTDs, the exponential wave is developed at voltages smaller than the peak voltage, and the sinusoidal wave is coupled to it at larger voltages, whose wave number becomes much larger than that of the input; therefore, the input pulse experiences significant shortening. The similar pulse shortening can be realized in traveling-wave field-effect transistors (TWFETs). A TWFET is a special type of FET whose electrodes are employed not only as electrical contacts but also as transmission lines . We consider the case where a decreasing voltage pulse is applied to the gate line and an increasing one is simultaneously applied to the drain line. By properly designing the top and bottom levels of the applied pulses, every FET simulates an electronic switch (the switch is open for voltages greater than some fixed threshold, and closed otherwise). This arrangement guarantees the pulse shortening owing to the development of the exponential-sinusoidal waves as observed in an RTD line .

In order to evaluate the above-mentioned results in monolithically integrated devices, we have to develop the models of nonlinear devices such as RTDs and FETs for use in a finite-difference time-domain (FDTD) electromagnetic solver . In FDTD-based solvers of Maxwell’s equations, a circuit element such as a capacitor, an inductor, or a nonlinear device, is usually implemented in an extended Ampere’s law as a field-dependent conductance/capacitance in a single Yee cell . Unfortunately, it requires some root-finding routine such as the Newton-Raphson method to solve it to obtain the temporal advanced electrical fields for numerical stability . The situation becomes more cumbersome, when the physical extent of devices cannot be ignored. Because we have to evaluate several adjacent cells for the terminal voltages that determine the device operation, a root-finder for multiple-variable functions is needed, which is very time-consuming. Moreover, we consider nonlinear transmission lines, which generally include numerous nonlinear devices.

Recently, we developed a concise model of nonlinear devices that contributes to eliminating the time-consuming root-finding procedures mentioned above. It approximates the voltage dependence of the device current by a piecewise-linear function and solves an extended Ampere’s law in a closed form. Actually, we successfully demonstrated an FDTD calculation of the pulse shortening in an RTD line . The similar modeling can be applied not only for diodes but also for three-terminal devices such as FETs. Based on our strategy, we first discuss an FDTD model of FETs after giving brief reviews and then show the results of full-wave calculations that demonstrate the pulse compression in a TWFET.

2. Diode Model in FDTD

When the conduction current density flowing in the device is denoted by JL, the temporal evolution of the electromagnetic fields is calculated on the basis of an extended Ampere’s law asEt=1ϵ×H-1ϵJL, where E, H, and ϵ are the electric field, magnetic field, and dielectric constant, respectively. By the single-cell implementation of the lumped device, (1) is converted as follows: Eyn=Eyn-1+Δtϵ(×Hn-1/2)y-ΔtϵΔxΔzIL(VL)n-1/2, where Δx, Δz, and Δt show the cell size in x, z, and t directions, respectively. The superscripts show the temporal positions, by which we represent the alternative evaluations of electrical and magnetic fields in FDTD. Moreover, IL and VL show the device current and terminal voltage, respectively. The current is assumed to flow in the y direction and is equal to |JL|ΔxΔz. Moreover, VL is given by EyΔy at the cell corresponding to the device. Thus, (2) becomesEyn=Eyn-1+Δtϵ(×Hn-1/2)y-ΔtϵΔxΔzILn-1/2(Eyn). As mentioned above, the argument of IL is evaluated at time n for numerical stability. When a device occupies N adjacent cells, the difference equations to be solved becomeEyn[i]=Eyn-1[i]+Δtϵ(×Hn-1/2[i])y-ΔtϵΔxΔzILn-1/2(Eyn,Eyn,,Eyn[N])(i=1,2,,N), where X[i]  (X=Ey,H) represents the field at the ith cell occupied by the device.

To solve (4) explicitly, we approximate the voltage dependence of the device current by a piecewise-linear function. The key is the fact that Eyn[i] is solved by hand in (4), when ILn-1/2 is a linear function of the arguments. Setting IjIL(Vj) for M different voltages Vj, (j=1,,M), IL is approximated by the following piecewise-linear function:IL(V)=Ij+1-IjVj+1-Vj(V-Vj)+Ij, where V(Vj,Vj+1] for j=1,M-1. Substituting (5) into IL in (4) and setting V=Δyk=1NEyn[k], we obtainEyn[i]=Eyn-1[i]+Δtϵ(×Hn-1/2[i])y-αjk=1NEyn[k]-βj, whereαj=ΔtΔyϵΔxΔzIj+1-IjVj+1-Vj,βj=ΔtϵΔxΔzIjVj+1-Ij+1VjVj+1-Vj.

By straightforward calculations, (6) is solved with respect to Eyn[i] to giveEyn=A[j]-1S[j],A[j]kl=δkl+αj,S[j]k=Eyn-1[k]+Δtϵ(×H[k])y-βj, where Eyn shows the column vector (Eyn,Eyn,,Eyn[N])T. Moreover, A[j]kl,  (k,l=1,2,,N) and S[j]k,  (k=1,2,,N) show the (k,l)th entry of A[j] and the kth component of S[j], respectively. Note that A[j]-1 is obtained in a closed form asA[j]kl-1=δkl-αj1+Nαj. After obtaining Eyn[i] using (8), we have to check if the terminal voltage V is really in the range (Vj,Vj+1] with V=Δyi=1NEyn[i]. If not, the procedure is repeated with other j values, until V(Vj,Vj+1]. The presented diode model successfully demonstrated the wave properties traveling in an RTD transmission line [8, 9].

3. FET Model in FDTD

There are many different equivalent circuits of an FET, depending on the accuracy and the application to use. For clarity, we first consider the simplest representation: an FET is represented only by the drain-source current IDS as a function of both the gate-source and drain-source voltages. Then, an extended Ampere’s law is given byEyn=Eyn-1+Δtϵ(×Hn-1/2)y-ΔtϵΔxΔzIDSn-1/2(VGS,VDS), where VGS and VDS represent the gate-source and drain-source voltages, respectively. Again, the current is assumed to flow in the y direction. The adjacent MD cells are used for calculating VDS. Moreover, the electrical field components used for VDS are denoted by Ey,,Ey[MD]. The difference equations to be solved becomeEyn[i]=Eyn-1[i]+Δtϵ(×Hn-1/2[i])y-ΔtϵΔxΔzIDSn-1/2(VGS,Δyk=1MDEyn[k])(i=1,2,,MD).

At this point, we approximate the voltage dependence of IDS by a piecewise-linear function and solve algebraically (13) with respect to Eyn[i] (i=1,,MD). The procedure is similar to the above-mentioned diode case, except that VGS must be upgraded by corresponding electrical field components at time n.

Next, we consider more practical FET models shown in Figure 1(a), called the Statz model . The model takes the gate-source, gate-drain currents together with the drain-source current into consideration. Moreover, the parasitic resistances and capacitances are also modeled. The device current-voltage relationships are given byIGn-1/2=-rs(VDSn-xdsn)+(rs+rd)(VGSn-xgsn)rgrs+rsrd+rdrg,IDn-1/2=(rs+rg)(VDSn-xdsn)-rs(VGSn-xgsn)rgrs+rsrd+rdrg,ISn-1/2=IGn-1/2+IDn-1/2, where IG, ID, and IS represent the gate, drain, and source currents, respectively. The auxiliary voltage variables xgs and xds are solved with respect to VGS and VDS by the following expressions resulting from Kirchhoff’s law:ISn-1/2=IDS(xgsn,xdsn)+CDSxdsn-xdsn-1Δt+IGS(xgsn)+CGS(xgsn)xgsn-xgsn-1Δt,IDn-1/2=IDS(xgsn,xdsn)+CDSxdsn-xdsn-1Δt-IGD(xgsn,xdsn)+CGD(xgsn,xdsn)xdsn-xgsn-xdsn-1+xgsn-1Δt. For definiteness, we assume that the adjacent MG cells are used to evaluate VGS and adjacent MD cells are for VDS. Moreover, the gate and drain currents are assumed to flow the former MG and the latter MD cells, respectively. Then, we denote the electrical field components used for VGS as Ey,,Ey[MG], and the symbols Ey[MG+1],,Ey[MG+MD] are reserved for those representing VDS. The difference equations to be solved becomeEyn[i]=Eyn-1[i]+Δtϵ(×Hn-1/2[i])y-ΔtϵΔxΔzIXn-1/2(VGS,VDS), where IX represents IG(ID) for i=1,,MG(i=MG+1,,MG+MD).

FET model in FDTD. (a) The Statz model and (b) A triangulation of VGS-VDS plane.

To obtain a piecewise-linear function that approximates the device currents, we triangulate the VGS-VDS plane. For the present device currents, a simple triangulation shown in Figure 1(b) suffices. Setting IG(D),i,jIG(D)(VGS,i,VDS,j) for MG×MD different voltages (VGS,i,VDS,j),  (i=1,,MG,j=1,,MD), IX  (X=G,D) is approximated by the following piecewise-linear function for (VGS,VDS)Si,j in Figure 1(b):IX(VGS,VDS)=IX,i+1,j-IX,i,jVGS,i+1-VGS,i(VGS-VGS,i)+IX,i,j+1-IX,i,jVDS,j+1-VDS,j(VDS-VDS,j+1)+IX,i,j+1. On the other hand, for (VGS,VDS)Ti,j in Figure 1(b), it isIX(VGS,VDS)=IX,i+1,j-IX,i,jVGS,i+1-VGS,i(VGS-VGS,i+1)+IX,i,j+1-IX,i,jVDS,j+1-VDS,j(VDS-VDS,j)+IX,i+1,j. Hereafter, we denote the piecewise-linear counterparts of ID(G) as ID(G)=aD(G),ijVGS+bD(G),ijVDS+cD(G),ij for convenience. Substituting them into ID,G in (16), we obtainEyn[i]=Eyn-1[i]+Δtϵ(×Hn-1/2[i])y-ΔtϵΔxΔz×(aX,jkΔyl=1MGEyn[l]+bX,jkΔyl=MGMG+MDEyn[l]+cX,jk), where X has to set to G and D for i=[1,,MG] and i=MG+1,,MG+MD, respectively.

We again obtain the column vector Eyn=(Eyn,,Eyn[MG],Eyn[MG+1],,Eyn[MG+MD])T in the form of Eyn=A[jk]-1S[jk]. The lth component of S[jk] is given byS[jk]l=Eyn-1[l]+Δtϵ(×H[l])y-γX,jk, where γX,jk represents cG,jk  Δt/ϵΔxΔz for i=1,,MG, and cD,jk  Δt/ϵ  Δx  Δz for i=MG+1,,MG+MD. Moreover, the matrix A[jk] is given byA[jk]lm={δlm+αG,jk,(l,m)[1,MG],δlm+βD,jk,(l,m)[MG+1,MG+MD],βG,jk,l[1,MG],  m[MG+1,MG+MD],αD,jk,l[MG+1,MG+MD],  m[1,MG], where αG,D,jkaG,D,jkΔtΔy/ϵΔxΔz and βG,D,jkbG,D,jkΔtΔy/ϵΔxΔz. For the present case, A[jk]-1 is explicitly given ashlmA[jk]lm-1={[(1+MDβD,jk)(1+MGαG,jk)-MGMDαD,jkβG,jk]δlm-(1+MDβD,jk)αG,jk+MDβG,jkαD,jk,(l,m)[1,MG],[(1+MDβD,jk)(1+MGαG,jk)-MGMDαD,jkβG,jk]δlm-(1+MGαG,jk)βD,jk+MGαD,jkβG,jk,(l,m)[MG+1,MG+MD],-βG,jk,l[1,MG],  m[MG+1,MG+MD],-αD,jk,l[MG+1,MG+MD],  m[1,MG],where hlm=(1+MDβD,lm)(1+MGαG,lm)-MGMDβG,lmαD,lm. After obtaining Eyn[i], we have to check if the terminal voltages VGS and VDS are really in the range we presume. Otherwise, the procedure is repeated with coefficients corresponding to another triangularized regions in VGS-VDS plane. Moreover, when the device model includes capacitors such as CGS and CGD, these terminal voltages must be recorded, which are required for evaluating xdsn-1 and xgsn-1 in (15).

In the following, we demonstrate the pulse shortening in TWFETs by FDTD calculations. Although the line structure we set up is rather impractical, we successfully observed the shortening of the pulse traveling along a TWFET. It is observed, only when the nonlinear operations of a large amount of FETs are properly simulated. We thus believe that this example calculation clarifies the validity of our models. Before showing calculation results, we briefly review the mechanism of the pulse shortening in TWFETs.

4. Pulse Shortening in TWFETs

Figure 2(a) shows the equivalent representation of a TWFET. One end of each electrode line labeled as Vgin(Vdin) is for signal applications. Figure 2(b) shows the required pulse shapes applied at Vgin(Vdin). The voltages biasing the gate and drain lines are denoted by VG1 and VD1, respectively. The drain pulse has the opposite parity to the gate pulse. Moreover, the top and bottom voltage levels of the drain (gate) pulse are set to VD2 (VG1) and VD1 (VG2), respectively. At this point, VG2 is set below the FET threshold voltage VTO, and both of VD1 and VG1 are set to approximately 0 V. The thin curves in Figure 2(c) show the drain current-voltage relationships for several different gate bias voltages. The uppermost and lowermost curves correspond to the relationships for VG1 and VG2, respectively. Because of the presence of electromagnetic couplings between the gate and drain lines, two different propagation modes, called the c mode and the π mode , are developed on a TWFET. We can design a TWFET to amplify only the pulses carried by one of the two modes and attenuate the pulses carried by the other mode . The conditions are given by simple inequalities using three variables us, uc, and uπ defined asus=LmCgd(LgLd-Lm2),uc,π=X1±X12-2X2X2,   where the upper (lower) signs are for c (π) mode. Moreover, we used two variables X1,2 for brevity: X1=CgsLg+CdsLd+Cgd(Lg+Ld)-2CgdLm and X2=2(CgsCds+CgsCgd+CdsCgd)(LgLd-Lm2). It is then found that the c-mode pulse is generically amplified when us>uc, while the π-mode pulse is amplified when us<uπ. Because uc is always greater than uπ, we can see that when the characteristic velocity us is less than both uc and uπ, the slower mode is the unique amplified mode; in contrast, when us is greater than both uc and uπ, the faster mode is the unique amplified mode.

Setup of TWFETs for shortening traveling pulses. (a) A representation of a TWFET, (b) the signal application to a TWFET and (c) the equivalent current-voltage relationship of an FET for a pulse traveling in the drain line.

When the TWFET succeeds in amplifying the unique mode, we can assume the simultaneous propagation of the leading edges of the gate and drain pulses. At this point, every FET operates as an electronic switch that is open for Vdin>Vb, and closed for Vdin<Vp as shown in Figure 2(c). As a result, the pulse is influenced by finite shunt conductance for voltages less than Vp and is otherwise loss-free. Owing to this nonlinearity, a short-wavelength sinusoidal wave supported by an exponential edge develops . Figure 3 schematically explains the mechanism of pulse-shortening phenomena. When a pulse of width linit is input to the drain line ((1) of Figure 3), the above-mentioned short-wavelength sinusoidal wave is shown in (2). Because the drain line attenuates voltage waves only below Vp, the small-amplitude parts of the wave disappear with the shorter propagation than the large-amplitude ones ((3) in Figure 3). Finally, a short pulse is obtained at the output ((4) in Figure 3).

Operation principle of pulse shortening in TWFETs.

5. Demonstration of Pulse Shortening in TWFETs

Three-dimensional FDTD calculations were carried out for demonstrating nonlinear pulse propagation along a TWFET. The total number of cells was 400×150×100. The spatial increments in the x, y, and z orientations were set to 10, 2, and 10 μm, respectively. The calculation setup is illustrated in Figure 4(a). The gate and drain lines were aligned in the x direction. At one of the ends of the lines, the inputs were applied with the hyperbolic secant pulses with the opposite parity. To maximize the coupling between the gate and drain lines, the spacing between two lines was set small and no ground plane was placed except the source. The dielectric constant of the substrate was set to 13.6. Moreover, a Mur’s 2nd-order absorbing boundary condition (ABC) was employed. FETs are placed every 30 μm along the electrode lines, whose widths were all set to 10 μm. Each FET was modeled as the drain-source current IDS:IDS(VGS,VDS)={β(VGS-VTO)2tanh(αVDS),VGS>VTO,0,VGS<VTO,where we set β, VTO, and α to 20.0 mA/V2, −1.0 V, and 2.0 V−1, respectively. We ignore the influences caused by the gate-source current with the parasitic capacitors and resistors for clear observations of the nonlinear properties of a TWFET. We modeled IDS as a piecewise-linear function with respect to VDS with 2000 segments. The cross-section of electrodes is shown in Figure 4(b). For VGS, we summed up the y components of the electrical fields of the nine subsequent cells connecting the gate line and the source (the cells labeled by “G” in Figure 4(b)). Similarly, neighboring fifteen cells were used for evaluating VDS (the cells labeled by “D” in Figure 4(b)).

Setup of FDTD calculations. (a) The longitudinal and (b) the transverse structure of the calculated TWFET.

To obtain a rough estimation of the model TWFET, we carried out the quasi-TEM analysis . The 2×2 capacitance matrix C and inductance matrix L are obtained by the numerical estimation of electrical charges stored in the electrode lines. By solving the Poisson equation for the case where VGS and VDS are set to 1.0 and 0.0 V, respectively, we can obtain the electrical charges stored in the gate and drain lines: Q11 and Q21. Those for the case where VGS and VDS are, respectively, set to 0.0 and 1.0 V, called Q12 and Q22 are similarly obtained. Then, the 2×2 matrix Q, whose components are given by Qij (i,j=1,2), gives C. On the other hand, we consider the case where the electrodes are in vacuum; that is, the dielectric constant of each cell is set to unity for L. To obtain L, it is required to evaluate the capacitance matrix C0 in vacuum by the same procedure as obtained C, because L has to be equal to c-2C0-1 (c: the light velocity). As a result, we obtain the line parameters as listed in Table 1. Using them, uπ and uc are calculated to be 0.29 c and 0.32 c, respectively. Moreover, us satisfies the condition, us<uπ, so that the π-mode pulse is expected to be uniquely amplified; therefore, the pulse shortening can be observed in the one carried by the slower π mode. The black curves in Figure 5 show the results from numerical integration of the transmission equations of a TWFET using the parameters listed in Table 1. Hyperbolic secant waveforms shown in Figure 5(a) are applied. The temporal waveforms monitored at five different FET cells, each separated by twelve FET cells, are shown. The thin and thick waveforms represent the pulse on the gate and drain lines, respectively. Because the discrepancy between the c- and π-mode velocities is small, the pulse carried by the π mode is still overlapped with that carried by the c mode even in Figure 5(f). However, it is observed that the pulse carried by the slower mode experiences shortening. On the other hand, the results from FDTD calculations are shown by the red curves in Figure 5. Five temporal waveforms are plotted and recorded at 480 μm intervals along the line in Figures 5(b)5(f). Qualitatively, the waveform transients have good resemblance with those obtained by quasi-TEM calculations. The steep exponential edge is developed and the pulse starts to exhibit an oscillatory behavior and then is shortened. We have found that even a TWFET with practical FET properties succeeds in pulse shortening in the framework of the transmission line theory. Moreover, we experimentally confirmed the pulse shortening using actual FETs at low frequencies . We believe that the FDTD calculations may contribute to the design of the monolithically integrated TWFETs as pulse compressor, when they are solved with a practical FET model.

Line parameters of test TWFET.

 Cgs 0.10 pF/mm Lg 0.73 nH/mm Cgd 0.17 pF/mm Ld 0.70 nH/mm Cds 0.09 pF/mm Lm 0.42 nH/mm

Wave propagation on test TWFET. The waveforms on the gate and drain lines are shown by the thin and thick curves, respectively. The black and red curves correspond to the quasi-TEM and FDTD calculations, respectively. (a) shows the input waveforms. Waveforms recorded at the nth FET cell are shown. (b), (c), (d), (e), and (f) represent the waveforms at n=36, 48, 60, 72, and 84, respectively.

6. Conclusions

We demonstrated full-wave calculations that illustrate the pulse propagation characteristics of a TWFET. The pulse shortening in a TWFET was properly observed in the full-wave calculations. By using piecewise-linear modeling, FETs were characterized in FDTD without significant computational costs.

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