Influence of Surface Morphology on the Effective Lifetime and Performance of Silicon Heterojunction Solar Cell

1Department of Materials Science and Engineering, Dayeh University, Changhua 515, Taiwan 2Department of Materials Science and Engineering, National Chung Hsing University, Taichung 402, Taiwan 3School of Software and Microelectronics, Peking University, Beijing 100871, China 4Graduate Institute of Precision Engineering, National Chung Hsing University, Taichung 402, Taiwan 5Department of Materials Science and Engineering, MingDao University, Changhua 52354, Taiwan


Introduction
In recent years, heterojunction (HJ) silicon solar cells have been drawing increasing attention owing to their high conversion efficiency (up to 24.7%) [1][2][3], low fabrication temperature [4], low temperature-conversion efficiency dependence [5], and shorter fabrication time.The HJ cells make use of the large band gap of hydrogenated amorphous silicon (a-Si:H) as an emitter with silicon wafer, and the electrons or holes can move in one direction only due to the large band offset.However, dangling bonds on the wafer surfaces serve as recombination centers for the carriers.Such recombination losses will mainly affect the device open-circuit voltage ( oc ), the resistance losses that affect the fill factor (FF), and the optical losses which have direct impact to the shortcircuit current density ( sc ).Several improvements have been reported.One of the most important approaches is the insertion of intrinsic (i-) a-Si:H at the interface between a-Si:H emitter and wafer to passive dangling bonds on wafer surfaces, thus reducing recombination losses [6].Another concern is the reflection losses at the front surface due to the large refractive index of a-Si:H.To reduce the optical losses two practical methods have been used, (i) using an antireflection coating [7] and (ii) texturing the wafer surface [8][9][10].Currently, wet etching by an alkaline solution is the standard process for industrial solar cell texturing.The most widely used etching solution is a low concentration potassium hydroxide (KOH) or sodium hydroxide (NaOH) solution in water with the addition of isopropyl alcohol (IPA) to achieve good lateral uniformity of pyramidal structures across the Si wafer surface by modifying the surface wettability [11,12].The wet etching process not only roughens wafer surfaces but also removes sawing damage simultaneously.However, only few groups have achieved high efficiency HJ solar cells [13,14] because the wet etching texturization can have significant influences on carrier lifetime.Iencinella et al. [15] reported 2 International Journal of Photoenergy that the K + and Na + released from etching solutions are extremely fast-diffusing alkali metal ions that can possibly cause contamination of wafers and limit carrier lifetime.Furthermore, IPA is highly volatile so that its fraction in the etching solution is not easy to remain constant.Several methods have been proposed in an attempt to improve the texturization.Stegemann et al. and Kegel et al. [16,17] indicated that a-Si:H/c-Si solar cells fabricated on IPA-free textured wafers conversion efficiencies above 20% were achieved by quantitative evaluation and optimization of the texture and interface passivation.Deligiannis et al. [18] used repeated cycles of nitride acid oxidation procedure to remove contamination and nanoscale roughness on the facets of pyramidal structures to improve passivation quality.Li et al. [19] used NaClO to produce smaller pyramids than that created by KOH or NaOH, and the small pyramids can lead to better coverage and contact between a-Si:H and wafer.Some groups also used dry etching techniques [20], but so far they have no reports of a HJ solar cell with a conversion efficiency higher than 17%.
In this study, we adopt industrial standard texturization using KOH and IPA mixed solution.Different etching times are used to etch silicon wafers so as to remove saw damage and produce rough surfaces.The impact of etching times and resultant surface morphologies on carrier lifetime and surface passivation quality are investigated.Furthermore, simulation was carried out to evaluate the cell characteristics.

Experimental
Single polished, -type, ⟨100⟩ single-crystal silicon wafers with thickness of 250 m, resistivity of 1-10 Ω-cm, and area of 15.6 × 15.6 cm 2 were used as substrates.Wafers were cleaned and then dipped in a 2% HF solution for 30 s to remove native oxide, prior to the etching process.Pyramidal texturization was carried out in a 5 wt.%KOH solution with 2 wt.%IPA at 85 ∘ C for different etching time (from 0 to 120 min).The alkaline solution can cause pyramidal structures on the wafer surface because of the difference in etching rates of (100) and (111) planes.The involved chemical reactions can be found in [21].During etching, hydrogen bubbles are created, and IPA is used for removal of the bubbles, so that the better lateral uniformity of the pyramids across the wafer surface can be achieved.After etching, an RCA2 clean, consisting of a solution of 6 : 1 : 1 H 2 O : HCl : H 2 O 2 , was performed at 80 ∘ C for 5 min to remove metal ions that might possibly remain on the wafer surface.The passivation of the wafer surface dangling bonds was done by two methods, iodine-ethanol solution passivation and a-Si:H passivation.The a-Si:H was deposited by PECVD, and the detailed deposition conditions can be found in [22].
For HJ solar cell simulation, the device structure was indium tin oxide (ITO)/(n) a-Si/(i) a-Si/(p) c-Si/Al back surface field (Al-BSF).The main properties of the layers in the device structure were obtained by experimental characterization of each layer.The (i) and (n) a-Si:H thicknesses were 5 and 10 nm, respectively.ITO film with a thickness of 90 nm was deposited using electron-gun evaporation in order to enhance the lateral conductivity and minimize reflection losses.Al film with a thickness of 5 m was sputtered on the wafer backside and annealed at 800 ∘ C for 30 s.
The film thickness was evaluated by using an alpha-step profiler.The wafer minority carrier lifetime was measured using quasi-steady-state photoconductance (QSSPC) system.The texture morphologies were observed by scanning electron microscopy (SEM) and high resolution transmission electron microscopy (HRTEM).

Results and Discussion
Figure 1 shows the SEM micrographs and surface profiles of the wafers etched for 0-120 min.Pyramids are formed as the etching rate in a ⟨100⟩ orientation is far higher than that in a ⟨111⟩ orientation [23,24].The pyramids size increases with increasing the etching time and seems to reach the maximum at 90 min.Further increasing of the etching time to 120 min leads to overetching which reduces the pyramids size.It is worth noticing that, from the surface profiles, the edges of the pyramids are not smooth but rather contain several smaller subpyramids.We define a "turning point" as the point at the mountain or the valley of a pyramid with a base width larger than 1 m.The numbers of the counted turning points, which are also labeled in the figure, are 0, 17, 21, 45, and 33 for the wafers etched for 0, 30, 60, 90, and 120 min, respectively.Note that the 90 min etched wafers thus have not only the highest surface roughness but also the largest number of turning points.
Figure 2 shows the carrier lifetime of the wafers with different etching times and passivation methods.In particular, the a-Si:H passivation is compared to the iodineethanol solution passivation, which is generally used to evaluate the optimal passivation conditions.It can be seen that, without any passivation, all the carrier lifetimes of the wafers are low, in the range of 25-50 s, due to high amount of surface dangling bonds.The effect of the etching time is thus covered.Considering the wafers with iodine-ethanol solution passivation, the lifetime is significantly higher than that of the unpassivated wafers and increases from 148 through 325, 321, and 153 to 225 s when the etching time increases from 0 to 120 min.The low values of the nonetched wafers result from the lack of saw damage removal, while the lifetime variation between the etched wafers could be related to increased surface defect states due to expanded surface area and decreased mobility due to the increased roughness [25].The lifetimes of the wafers with a-Si:H thin-film passivation are similar to the wafers with iodineethanol solution passivation at the etching time of 0, 30, and 60 min, and this implies the high passivation quality of our a-Si:H films.Nevertheless, the difference of the lifetimes between the wafers with the two passivation methods at 90 min becomes larger, suggesting a significantly weakened passivation capability of a-Si:H compared to iodine-ethanol solution passivation.
Figure 3 shows schematic diagrams of surface passivation using iodine-ethanol solution and a-Si:H thin-film.As shown in Figure 3(b), a large number of dangling bonds exist on the surface of a wafer.During the iodine-ethanol solution passivation process, the surface dangling bonds (Si ∘ ) are removed, according to Detailed information can be found in [26].Since ethanol is liquid phase, it could uniformly contact with wafer surfaces and provide great passivation quality, as shown in Figure 3(c).On the other hand, silicon and hydrogen atoms are solid phase, so that they might irregularly deposit on the wafer surfaces, as is shown in Figure 3(d).The passivation quality especially at the mountain and valley regions is expected to be reduced.In other words, a-Si:H is assumed to have a lower passivation capability for a wafer having more mountains or valleys (i.e., more turning points).Therefore, this possibly explains the lower lifetime of the 90 min etched wafer with a-Si:H passivation as compared to that with iodine-ethanol passivation.
The cross-sectional morphologies of the etched wafers are investigated, and they show similar results without distinguishable difference.As a representative, Figure 4 shows the TEM cross-sectional images of a pyramid on surfaces of the 90 min etched wafer with a-Si:H passivation.Figures 4(a  is reported to be detrimental to final device performance [27].On the contrary, the hillside region shows a clear interface between wafer and a-Si:H, as shown in Figure 4(c).Therefore, these TEM images support the mechanism of a-Si:H passivation proposed previously.The experimental values of the carrier lifetimes of the wafers with different etching times and with a-Si:H passivation were input to the one-dimensional simulation software PC1D [28,29] to provide theoretical analysis about the cell performance.The main parameters are summarized in Table 1.The simulation result of  oc , which is the mostly affected, and the conversion efficiency () of the HJ solar cells as function of the carrier lifetime are plotted in Figure 5(a).Generally, an increased carrier lifetime will lead to a reduced diode dark current and thus improve  oc , according to [30] where / is the thermal voltage and  0 is the diode dark current.In order to exclude variables other than the lifetime, the reflectance was kept to a constant value of 5%, so that  sc in (2) would be influenced mainly by carrier lifetime as given by [31]  sc = √    + √    , where  is the carrier generation rate,   (  ) is the diffusion coefficient of holes (electrons), and   (  ) is the lifetime of holes (electrons).Three regions are divided for discussion.Firstly, the wafer lifetimes ranging from 25 to 50 s correspond to the wafers without passivation, so that  0 is large due to huge amount of surface dangling bonds.In this region,  oc is less than 630 mV and  is lower than 20%.
Secondly, the lifetimes in the range of 80-150 s result from the wafers having saw damage or considerable turning points, leading to poor a-Si:H passivation quality.The intermediate  oc of about 640-650 mV and  of 20.5%-21% are observed.Thirdly, high lifetime regions of 250-400 s can correspond to a wafer with little turning points and a good a-Si:H passivation close to the ideal passivation conditions.The resultant  oc and  can be higher than 660 mV and 22%, respectively.Figure 5(b) shows the - characteristics and external parameters of the HJ solar cells with different wafer etching times.Note that the effect of light reflection caused by surface roughness of the etched wafers was taken into account by inputting the experimental front reflectance values of the fabricated devices with ITO.The ITO acts as not only front electrode but also antireflective layer, so that the device reflection is significantly lower than that of the wafers.The device reflectance values are 13.36%, 4.95%, 2.60%, 2.71%, and 3.02% for the etching times of 0, 30, 60, 90, and 120 min, respectively. oc values still match well the result shown in Figure 5(a), in which the poor passivation region corresponds to the 0, 90, and 120 min etching times, while the good passivation region corresponds to the 30 and 60 min etching times.The trend of  sc is mainly determined by the device reflectance and the carrier lifetime, shown in (3).The former has much larger dependence on  sc .FF does not change significantly as the wafer etching time varies.It should be noted that the optimal  is determined by a trade-off between  oc and  sc .These two parameters increase for the early etching stage (0-40 min).However, when the etching time increases,  sc remains increasing until the etching time exceeds 90 min, while  oc decreases due to the notable amount of turning points produced.Overall, the maximum  of 21.94% occurs at the etching time of 60 min.

Conclusions
This study investigates the influence of the etching time on a-Si:H passivation capability, wafer carrier lifetime, and HJ solar cell performance.It is found that different etching time will greatly affect the a-Si:H passivation capability according to the produced turning points.A small number of the turning points lead to good a-Si:H passivation capability which can even be comparable to the ideal iodine-ethanol solution passivation.However, a wafer with high turning points may lead to poor a-Si:H passivation which greatly reduces the carrier lifetime.The a-Si:H layer is found to be difficultly well-deposited at the turning points as evidenced by the fact that the interfaces between the a-Si:H and wafer surface are deteriorate.Finally, with different etching time, there is a trade-off between  oc and  sc to obtain the optimal conversion efficiency.In this case, the maximum conversion efficiency is 21.94% for a HJ solar cell with a wafer etching time of 60 min.

Figure 2 :
Figure 2: Effective minority carrier lifetime of wafers with different etching time and different passivation methods.

Figure 3 :
Figure 3: (a) Surface profile of the 90 min etched wafer and schematic diagrams of the wafer surface dangling bonds (b) without passivation, (c) passivated by iodine-ethanol solution and (d) a-Si:H.

Figure 4 :
Figure 4: HRTEM cross-sectional micrographs of (a) peak, (b) valley, and (c) hillside of a pyramid of the 90 min etched wafer passivated by a-Si:H.

Figure 5 :
Figure 5: (a) Simulated open-circuit voltage and conversion efficiency as a function of minor carrier lifetimes.(b) Simulated - curves of HJ solar cell with different etching times.

Table 1 :
Simulation parameters for HJ silicon solar cells.
* Measured from experimental data.