International Journal of Reconfigurable Computing

Volume 2014 (2014), Article ID 502942, 15 pages

http://dx.doi.org/10.1155/2014/502942

Research Article

FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, and Zhenan Tang

Dalian Institute of Semiconductor Technology and School of Electronic Science and Technology, Dalian University of Technology, Dalian 116023, China

Received 27 June 2014; Revised 3 August 2014; Accepted 6 August 2014; Published 31 August 2014

Academic Editor: Nadia Nedjah

Copyright © 2014 Kaiyu Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types of carrier recovery loops and obtain a more robust performance in the procedure of carrier recovery. Besides, considering that, for MLFE, the accurate estimation of frequency offset is associated with the linear characteristic of its frequency discriminator (FD), the Coordinate Rotation Digital Computer (CORDIC) algorithm is introduced into the FD based on MLFE to unwrap linearly phase difference. The frequency offset contained within the phase difference unwrapped is estimated by the MLFE implemented just using some shifter and multiply-accumulate units to assist the ADCOL to lock quickly and precisely. The joint simulation results of ModelSim and MATLAB show that the performances of the proposed ADCRL in locked-in time and range are superior to those of the ADCOL. On the other hand, a systematic design procedure based on FPGA for the proposed ADCRL is also presented.

1. Introduction

Along with the continuous development of the technologies of field programmable logic gate array (FPGA) and digital signal processing, the FPGAs in possession of large capacity and low power dissipation make it possible to realize a true software defined radio and integrate a whole digital communication system into the chips in order to reconfigure flexibly the continuously evolving communication protocols and minimize the volume of spacecraft. A typical example applying the software defined radio (SDR) based on FPGA to deep space communication is the National Aeronautic and Space Administration (NASA) Electra radio, in which the baseband processing is entirely implemented in a FPGA. Virtually any channel code, modulation, and data rate may be accommodated via suitable reprogramming of this SDR [1].

In communication system, the style of modulation and demodulation plays an important role and directly influences the performance of the system. However, in deep space communication, both power efficiency and bandwidth efficiency of a communication system should be simultaneously considered. Therefore, the modulation and demodulation method of QPSK have been widely used into deep space communication. With respect to QPSK demodulator, there are two different solutions to demodulate. They are noncoherent demodulation and coherent demodulation, respectively. Compared with noncoherent demodulation, coherent demodulation can be implemented in a simpler structure so as to save the logic resources of FPGA. Hence, this paper takes the QPSK coherent demodulator as the object of our study.

In QPSK coherent demodulator, a special phase-locked loop (PLL), namely, Costas loop, is used to synchronize the locally generated carrier with the carrier contained in the received input buried by external noise. It is well known that the PLL has an outstanding ability to restrain noise as a result of its narrow-band characteristic. Therefore, it can precisely realize carrier tracking. Nonetheless, in the design procedure of the PLL, the pair of contradictions between lock-in frequency range and tracking precision is always difficult to reconcile. In particular, in deep space communication, Doppler shift is common and will introduce a considerable frequency offset between transmitter and receiver. In this situation, for the PLL, to increase lock-in frequency range, loop noise bandwidth must be broadened, whereas the precise tracking of its carrier in the condition of a relatively low signal-to-noise ratio (SNR) is dependent on a narrow loop noise bandwidth. So, a large lock-in frequency range (loop noise bandwidth) and a high tracking precision cannot be simultaneously satisfied [2]. In practical designs, a compromise between them is a best choice.

Except for PLL, there are also many kinds of methods referred to as automatic frequency control (AFC) for carrier recovery, such as the frequency recovery loop based on feedback control [3] and the frequency offset estimator (FOE) based on estimation theory [4–6]. They are usually used in burst communication where the speed of carrier recovery must be very quick. However, a fatal flaw for these methods is a relatively low tracking precision. Thus, in low SNR environments, they do not present a perfect performance.

To recover carrier quickly and precisely in the two situations, a large frequency offset and a relatively low SNR, some approaches combining PLL and AFC are proposed to take advantage of their own merits. In [7], a kind of all-digital phase-locked loop (ADPLL) for QPSK combining a first-order frequency recovery loop based on feedback control with a second-order phase-locked loop is proposed. But due to the use of the FD in possession of a sinusoid characteristic (nonlinear characteristic), namely, the second algorithm shown in Table 1, extra noises are introduced into the loop in the circumstance of a low SNR. On the other side, [8] applies fast Fourier transformation (FFT) into the output of the phase discriminator (PD) of QPSK ADCOL, to roughly estimate frequency offset and then speed up the procedure of the carrier recovery of the ADCOL. However, when phase offset is considerable, its PD performs the nonlinear characteristic. On the other hand, for FFT accurate frequency estimation is proportional to the number of its points, which implies that to estimate precisely frequency must consume many logic resources of FPGA. From the above analysis, we can see that PD and FD also influence carrier recovery. Therefore, [9] proposes an all-digital phase-locked loop (ADPLL) taking Hilbert transform and CORDIC algorithm as its PD, resulting in that the locked-in range of the ADPLL is broadened to the sample frequency of the system (Nyquist rate). Given that our design is to combine MLFE with QPSK ADCOL and then use the former to roughly estimate a large frequency offset to assist the latter to lock quickly and precisely, which makes it possible for the ADCOL to operate within the linear range of its PD, we just draw our attention to the liner characteristic of the FD of the MLFE. Thus, a kind of FD which can implement frequency discrimination linearly is proposed. In other words, our proposed design considers not only the merits of the MLFE and the ADCOL, but also the linear characteristic of the FD of the MLFE so that carrier can be recovered quickly and precisely. Furthermore, the lock-in frequency range is also broadened so that the pair of contradictions hardly reconciled for ADCOL can be alleviated. On the other hand, the whole design process of the ADCRL based on FPGA presented by us will also provide a guideline for the readers anxious to implement an excellent FPGA-based ADCRL for QPSK, which is hardly found in published literatures.

Table 1: Two kinds of typical frequency discriminators.

The algorithm used
Frequency offset output
Output characteristic
Hardware complexity

Nonlinear
Moderate

Nonlinear
Simple

In the following, the design procedure of the ADCOL based on FPGA is presented step by step. Next, our proposed the FD of linear characteristic, MLFE based on phase domain, and the overall design of our QPSK ADCOL are described in Section 3. In Section 4, simulation results and comparative analyses are given. Finally, conclusion and outlook are obtained in Section 5.

2. FPGA-Based All-Digital QPSK Phase-Locked Loop

With respect to QPSK ADCOL, there are three basic components. They are PD, loop filter, and numerical control oscillation (NCO), respectively. Because it is also a kind of ADPLL, the design procedure of it is the same as the normal ADPLL. Therefore, it is indispensable to analyze the design procedure of the normal ADPLL. The normal ADPLL is derived from the result of digitizing analogy PLL. The analysis and design for analogy PLL has been well known. Some monographs have discussed some analogy PLLs which have different orders [10]. As it is sufficient for our QPSK demodulator to use a second-order ADPLL, we just discuss the digitizing procedure of a second-order analogy PLL.

2.1. The Modeling for All-Digital Phase-Locked Loop

Figure 1(a) shows the phase domain model of a second-order analogy PLL. It consists of the PD modeled by a subtractor with gain , the loop filter which is modeled by a first-order low pass filter, proportion integral filter, with the -domain transfer function to minimize the phase noise of the output of the PD, , and a voltage control oscillator (VCO) tuned by to make the output phase closed to the input phase , which acts like a radian frequency integrator as a result of , and have the -domain transfer function .

(a) Phase domain model of a second-order analogy PLL

(b) Phase domain model of a second-order ADPLL

Figure 1: The different modes of PLL.

From the above the analysis, a set of equations describing the -domain transfer functions of the phase domain model of a second-order analogy PLL can be obtained:

where is natural radian frequency, is damping factor, is the gain of the VCO, is the gain of the PD, and are time constants of the proportion integral filter, and is the -domain transfer function of the analogy PLL. Please note that the above the equations are just reasonable on the condition that the phase difference between and makes it possible for the PD to work within its linear range.

To digitize the analogy PLL, bilinear transformation which is often used to digitize analogy filter [11] is adopted. Let’s set the transformation as

where is the sample time of a discrete-time system.

Taking (4) into (1) and (2), then we can obtain

where and .

Therefore, as shown in Figure 1(b), the model of ADPLL can be acquired. On the basis of Figure 1(b) and the two equations (5); the based-model discrete-time transfer function of the ADPLL can be expressed as

2.2. Parameter Calculation of All-Digital Phase-Locked Loop

Form (6), we can see that to obtain the based-model discrete-time transfer function of the ADPLL, the values of the parameters, , , , and are needed. However, it is not easy to calculate them after knowing about the model of ADPLL. Nonetheless, none of researches published present the procedure. Thus, in the following we will display how to calculate them.

First of all, the method to acquire and is given.

Equation (6) is just the -domain transfer function based on the model of Figure 1(b) and the two equations, (5). On the other hand, taking (4) into (3), and the -domain transfer function of the ADPLL based on bilinear transformation can be obtained:

Let us set the denominator of the two -domain transfer functions of the ADPLL; (6) and (7) obtained by different methods to be equal and the two equations about and can be given:

where the two approximations are just true when . Namely, assuming that the PD of ADPLL lies in its linear operation range and for ADPLL the characteristic of frequency response is within the range of its passband.

Secondly, on the basis of [12], when , second-order PLL can meet the optimal value of Wiener theory. So we can get that .

The third step is to determine .

For PLL, the natural radian frequency determines locked-in frequency range and the performance of suppressing noise. The pair of contradictions between locked-in frequency range (loop noise bandwidth) and tracking precision stem from it.

In the following, we are going to discuss the range of from the two aspects, fast capture bandwidth of ADPLL, and its loop SNR, so as to make a compromise between the locked-in range and the tracking precision.

In the case of ADPLL, there are two kinds of noises, external phase noise and internal phase noise. The external noise caused by additive white Gaussian noise (AWGN) is a main part which has an influence on the performance of the ADPLL, and the internal noise caused by the finite word length effect can be improved by the reasonable selection of word length. Herein, the impact on the selection of is external phase noise. Thus, we just take it into consideration.

The channel of deep-space communication is quite benign, with AWGN being the dominating impairment [1], and thus the phase noise of ADPLL caused by AWGN can be given by [13]

where is the bandwidth of input signal of the ADPLL, is its input SNR, and is loop noise bandwidth.

For the second-order ADPLL taking proportion integral filter as its loop filter, can be expressed as

For ADPLL, the ability to suppress noise can be reflected by the loop SNR:

It determines the size of phase jitter. The result of linear analysis [14] manifests that PLL cannot work normally until .

Taking (10) into (11) and considering that ADPLL can operate normally, the upper bound of can be expressed as

The tracking procedure of ADPLL contains frequency tracking and phase tracking, and the former needs longer time than the latter. In design of our ADCRL, however, we firstly use maximum likelihood frequency offset estimator (MLFOE) to assist ADCOL to implement frequency tracking in that for MLFOE the speed of tracking a large frequency offset is superior to ADCOL. Therefore, we just take the phase tracking into consideration in the procedure of designing our ADCOL. In the case of ADPLL, the fast capture bandwidth is defined as the largest frequency offset which ensures that ADPLL can be locked in the procedure of the phase tracking. It can be expressed as

To meet the frequency tracking in the presence without the assistance of the MLFOE, the lower bound of is given by

Thus, from (12) and (14), we can get acquire the range of :

Until now, except for and , the parameters needed for calculating and have been acquired. Because the and are associated with some practical system parameters, we will discuss about them in the following.

2.3. Parameter Calculation of All-Digital QPSK Phase-Locked Loop Based on FPGA

In the above discussions, we have obtained the corresponding parameters for a normal ADPLL. But, as mentioned at the beginning of Section 2, QPSK ADCOL is also a kind of ADPLL. Thus, the above methods are suitable for QPSK ADCOL.

As shown in Figure 2, QPSK ADCOL is comprised of the PD covered by the shaded area, loop filter surrounded by dashed line, and numerically controlled oscillator (NCO). Now, based on Figure 2, we begin to discuss how to obtain and .

Figure 2: Structure diagram of QPSK all-digital phase-locked loop.

First of all, the analogy-digital converter (ADC) shown in Figure 2 samples the modulated signals from transmitter and acquires a series of discrete-time signals sampled :

where is the radian frequency of the signals sampled, is their initial phase, and and are the QPSK signals evaluated as in our design.

Secondly, the signals are mixed with the two outputs of the NCO and then filtered to eliminate the double frequency components generated by the mixing. The two signals filtered can be expressed as

 upper branch (in-phase branch):

 bottom branch (quadrature branch):

where is the radian frequency difference between signals sampled and the two outputs of the NCO and is their initial phase difference.

Finally, the function of the PD of the QPSK ADCOL is implemented by the following:

Herein, to save hardware resources of FPGA, the sign decision and the multiplication operation within (19) are replaced by a multiplexer controlled by the most significant bit (MSB) of the outputs of the two low pass filtersand an inverter shown in Figure 2 (because the outputs of the two low pass filters are signed numbers). Therefore, the output characteristic of the PD can be obtained:

Based on (20), the output characteristics curve of the PD can be obtain and shown in Figure 3. From Figure 3 we can see that only if the phase offset is within the linear range of the PD , the gain of the PD approximates to 1, namely, the slope of the curve. So this is also one reason why we use MLFE to assist QPSK ADCOL to recover carrier quickly and precisely.

Figure 3: Phase offset versus output voltage amplitude of PD.

Next, we start with discussing the gain of the NCO.

In [15], the authors implement NCO on a Xilinx FPGA in three types of ways, and the conclusion that the method based on Xilinx ROM is superior to the other two is acquired. Thus, we select the method based on Xilinx ROM to implement our NCO [16].

On the basis of the principle of NCO, the frequency of its output signal can be expressed as

where is sample frequency, is frequency control word, and is the bit width of the input signal of NCO. In our design, , where is a given value determined by carrier frequency, and its block diagram named as frequency control word can be seen in Figure 2; is the output of the loop filter that is tuned by the frequency offset between transmitter and receiver.

So the radian frequency of NCO is given as

On the basis of the model of ADPLL shown in Figure 1(b), NCO is equivalent to a radian frequency integrator. So the output phase of NCO is given as

where is the update period of the frequency control word , namely, the sample period of the output of loop filter , and is often set to be .

Therefore, the gain of our NCO is given by

So far, we have obtained all methods to calculate the parameters of the QPSK ADCOL, whereas we must note that, in our QPSK ADCOL based on FPGA shown in Figure 2, an extra gain will be introduced as the result of the changes of the bit width between the inputs and outputs of the different modules. Regardless of the sign bit, the bit width of the inputs of the two multipliers is 7, and the bit width of their outputs is 15. The bit width of the inputs of the two low pass filters is 15, and the bit width of their outputs is 31. Thus the gain of the two multipliers is , and the gain of the two low pass filters is . The rest of the parts showed in Figure 2 have no change in bit width between their inputs and outputs. Therefore, the gain from the changes of bit width is , and (8) should be rectified as

On the basis of the core idea of software defined radio, the parts of digital signal processing should be closed to the front end of radio frequency (RF) as much as possible. Therefore, we make our QPSK ADCOL operate in intermediate frequency (IF), namely, the ADC sample frequency  MHZ and carrier frequency (the output frequency of NCO)  MHZ.

On the other hand, To ensure that our QPSK ADCOL can normally operate under the conditions of a large frequency offset and a low SNR, let us set the fast capture bandwidth to be 100 KHZ the least, and the input SNR to be 1 dB. We have known that the gain of PD is , and the damping factor is . To decrease internal phase noise caused by word length effect, we set the bit width of input signal of NCO to be . Therefore, based on (15), (24), and (25), the range of the natural radian frequency can be obtained and the one of the values is chosen as

Next, take , (25), and (26) into (6), we can obtain the model-based discrete-time transfer function of our QPSK ADCOL:

From (27), the poles of our QPSK ADCOL can be obtained. They are . Based on the theory of the stability of discrete system, the system is stable if all poles are located inside the unit circle. Therefore, our QPSK ADCOL is stable.

Now, the frequency response characteristic and phase response characteristic of our QPSK ADCOL can be acquired and shown in Figures 4(a) and 4(b), respectively.

(a) Frequency response characteristic

(b) Phase response characteristic

Figure 4: QPSK ADCOL characteristic curve.

From Figures 4(a) and 4(b), we can see that when sample frequency is 26 MHZ, the passband of our QPSK ADCOL ranges from 0 to 200 KHZ (namely, is true) and its margin of phase is 120 degree below. Thus, this also indicates that our QPSK ADCOL meets the conditions of the stability of negative feedback control system. What is more, Figure 4(a) also displays that QPSK ADCOL is of the property of low pass.

3. The Design of Phase Domain Maximum Likelihood Frequency Estimator and Its Frequency Discriminator

3.1. The Frequency Discriminator of the Linear Characteristic

To use MLFE to obtain an accurate frequency offset, the performance of its FD is a key factor which must be considered. Two kinds of FDs used widely are summarized in Table 1 [17]. From Table 1, we can see that they are all of nonlinear characteristic. Because in the case of , is true only if varies within a small range. However, in deep space communication (or in the condition that a large Doppler shift is common), the approximation is hardly possible. On the other hand, to discriminate phase offset, the dot product and cross-product from two sample points separated by a sample interval must be conducted, and their results divide by the sample interval .

Therefore, we introduce a kind of FD in possession of linear characteristic and the ability to acquire the corresponding signals of our ADCOL so as to transform them into the inputs of the MLFE. Its block diagram surrounded by the dashed line is shown in Figure 5.

Figure 5: The block diagram of the FD and MLFE (MLFOE).

From Figure 5, we can see that after a series of transformations for the two equations, (17) and (18), the two signals of the front end of the CORDIC algorithm block can be obtained. They are

Feed them into the CORDIC algorithm block which implements the algorithm , and the phase offset can be acquired. After that, the MLFE will be used to estimate the frequency offset . It is clear that this is a procedure of resolving linearly frequency offset. Because the CORDIC algorithm can easily be implemented on FPGA just using snifters and add operations [18], we just discuss about how to implement MLFE on FPGA using as few logic resources as possible.

3.2. Phase Domain Maximum Likelihood Frequency Estimation Algorithm

In the case of the FD shown in Figure 5, a mapping transformation from Cartesian domain to phase domain can be realized by CORDIC core and expressed as

where and . is the discrete phase of th sample point. The amendment of is due to that the output range of our CORDIC core is within .

To use MLFE for estimating frequency offset, we first need to obtain the discrete phases of continuous sample points and then take the first sample point as initial reference point to obtain absolute phases, which can be expressed as

where (the output of our CORDIC core) is the discrete phase of th sample point, and it ranges from to . is an absolute phase of th sample point, which takes as the point of reference, and has no the limitation of phase ranging from to . The amendment of is due to the phase difference between the th sample point, , and the th, , crosses over a cycle of the outputof our CORDIC core.

After that, a recursive formula of the absolute phases can be obtained:

where is the phase noise caused by AWGN (for the sake of simplicity, we neglect it in (16), (17), (18), and (28)), is the sample frequency, is the frequency offset between the output of the NCO and the modulated signal from transmitter, and is initial phase difference of the two signals. When SNR is as low as 10 dB, numerical results have been demonstrated that can be considered as the Gaussian approximation accurate which has a zero mean and variance [19].

Let’s set to be , namely,

Equation (35) can be also written in vector form:

where

Consequently, is a Gaussian random vector with probability density function:

where .

The maximum likelihood estimators and can be obtained by equating the gradient to zero and solving a two-dimensional linear system:

where

The maximum likelihood estimators in (36) and (37) are minimum variance unbiased estimations achieving the Cramer Rao Bound [19, 20]. On the other side, the higher the estimation accuracy is, the larger the sample points and SNR are.

Please note that (31) is . If we use (36) to estimate frequency offset , the value of estimation must multiply by 4. In the case of FPGA, the multiplication of just needs to shift n bits towards the left.

On the other hand, in part 3, Section 2, we select update period of frequency control word of the NCO to be . Therefore, to enable frequency offset estimation block shown in Figure 5 and the QPSK ADCOL shown in Figure 2 to operate as synchronously as possible, we set the number of the sample point of MLFE to be . Therefore, based on (36), (34), (32), and (31), we can obtain the frequency offset estimated:

where  MHZ is sample frequency and , is absolute phase generated by (30).

Using to assist the QPSK ADCOL shown in Figure 2 to recover carrier quickly, must be transformed into frequency control world of the NCO. On the basis of (21), we can obtain frequency control world of that is

Taking (39) into (40), we can get

where , are signed decimals, which are expressed as the fixed-point number with 3 bits’ integer number and 29 bits’ decimal. is bit width of input signal of the NCO. Because frequency control world of NCO is an integer number, the result of (41) should multiply by so as to eliminate the affection of the decimal expressed by 29 bits’ binary format. Therefore, actual frequency control world should be

Due to , maximum likelihood frequency estimation can be implemented just using shifters and multiply-accumulate units.

In deep-space communication, to confirm that the signals buried by noise can be successfully detected by receiver, a parameter named link margin is used to specify minimal SNR of the received signals. In the practical design of the communication systems, its value usually ranges from 3 dB to 6 dB [21]. In our design, we select two types of link margins to investigate the performance of our frequency offset estimator. They are the low link margin of 5 dB and the high link margin of 20 dB, respectively. Therefore, we simulate our MLFE under the condition of sample frequency  MHZ and carrier frequency  MHZ by MATLAB. The simulation results are shown in Figure 6.

(a) Signal-to-noise ratio is 20 dB

(b) Signal-to-noise ratio is 5 dB

Figure 6: Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios.

From Figure 6, we can see that although the estimation rang of the frequency offset decreases along with the decline of SNR, the range still approximates −2 MHZ MHZ under  dB. In the case of low and medium earth orbiting satellite where the greatest Doppler shifts are  KHZ and  KHZ [22], respectively, the rang completely meets as well.

3.3. Entire Design of All-Digital Carrier Recovery Loop of QPSK

Figure 7 shows the block diagram of our ADCRL. It consists of the MLFOE in shadow and QPSK ADCOL surrounded by dashed line, respectively.

Figure 7: Block diagram of QPSK ADCRL.

First of all, the frequency offset will be estimated roughly and then transformed into the frequency control words of the NCO by MLFE to speed up QPSK ADCOL to quickly implement the tracking of the carrier.

Secondly, with the assistance of MLFOE, the QPSK ADCOL is locked quickly and then starts with tracking the carrier precisely.

From Figure 7, we can see that the bit width of the outputs of the two low pass filters is 32. If we apply directly the width to MLFOE, the cost of hardware resource for FPGA is considerable. So in our design, a truncated bit width will be used. To ensure that the impact of the truncation on the performance of our system is minimal, a simulation is conducted, which uses different bit widths for the two input signals of MLFOE (the bit widths of the outputs of the two low pass filters) and the widths range from 8 to 32 bits to test which one is the best for the frequency offset error  KHZ under the situations of  dB. The simulation result is shown in Figure 8. From Figure 8, it is clear that when the bit width is equal to 11, the frequency estimation value of the MLFOE is almost the same as that of having bit width equal to 32 under the three types of SNRs. Thus, we set the bit width of the two inputs of MLFOE to be 11.

Figure 8: The quantization level of the two input signals of MLFOE under the condition of the frequency offset error and .

4. Simulation Results and Comparative Analysis

To verify that the proposed architecture is valid, the FPGA simulation tool, ModelSim SE 6.5, is used to observe the implementation performance of our proposed architecture based on FPGA. On the other hand, MATLAB is also used to generate the QPSK modulated signals with a frequency offset under the conditions of different SNRs and process the simulation results generated by the ModelSim so as to have a better visual comparison, resulting from that the outputs of the ModelSim that are just some values of decimal or binary format.

The data streams of the entire simulation procedure are shown in Figure 9.

Figure 9: The data stream of entire simulation procedure.

The input stream generated, quantized and stored into the textfile, Textfile_A, by MATLAB, is QPSK modulated signals with the following specifications:

(i)the number of symbols randomly evaluated as is equal to 1000;(ii)the frequency of symbols  KHZ;(iii)the frequency of carrier  MHZ, namely, frequency offset  KHZ;(iv)SNRs are 20 dB and 5 dB;(v)quantization level of the 1000 QPSK modulated signals is 8 bits to imitate the input signals of 8-bit ADC;(vi)sample frequency  MHZ.

The output streams generated and stored into another two textfiles, Textfile_B, and Textfile_C by ModelSim are the outputs of the NCO and the loop filter with the following specifications:

 Textfile_B:(i)the frequency of carrier  MHZ, namely output frequency of NCO;(ii)sample frequency  MHZ;(iii)the quantization level of the output amplitude of the NCO evaluated as is 8 bits; Textfile_C:(i)sample frequency  MHZ;(ii)the quantization level of the output of the loop filter is 32 bits.

Textfile_A is generated by MATLAB before starting ModelSim simulation and then fed into QPSK ADCRL (to imitate the output of the ADC) in the procedure of the simulation of ModelSim, when Textfile_B and Textfile_C are simultaneously generated by ModelSim. At the end of the simulation of the ModelSim, the two files from the ModelSim, Textfile_B and Textfile_C, will be read into MATLAB in order to further process in the two procedures, MATLAB_process_A and MATLAB_process_B.

Because the traditional measure of the performance of PLL is based on locked-in time, steady-state phase error, and locked-in frequency range, our QPSK ADCRL also uses the methods.

Based on the principle of our QPSK ADCRL displayed in Figure 7, when there exists the frequency offset between the input of the QPSK modulated signals (Textfile_A) and the local carrier signals (the output of NCO), the offset can be obtained through taking the output of the loop filter (Textfile_C) into (21). In our design, the carrier frequency of the input modulated signals is 3.9 MHZ and the frequency of the output of the NCO is 4 MHZ. Therefore the frequency offset is 100 KHZ.

If our QPSK ADCRL is locked, the frequency offset evaluated through taking the output of loop filter into (21) will approximate to 100 KHZ. At the same time, the output phase of the NCO (Textfile_B) should be equal or approximate to the phase of the QPSK modulated signals (Textfile _A).

On the basis of above discussion, as shown in Figures 10, 11, 12, and 13, (a) and (b) are the outputs of the loop filter from ModelSim simulation, and its results processed by MATLAB (MATLAB_process_B shown in Figure 8), respectively. (c) is the result of the phase comparison of the two signals, QPSK modulated signals, and the outputs of the NCO, which is from the simulation of ModelSim and then processed by MATLAB (MATLAB_process_A shown in Figure 9).

(a) ModelSim output of loop filter

(b) MATLAB processing of output of loop filter

(c) MATLAB processing of ModelSim the output of NCO and input of QPSK modulated signal

Figure 10: The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL.

(a) ModelSim output of loop filter

(b) MATLAB processing of output of loop filter

(c) MATLAB processing of ModelSim the output of NCO and input of QPSK modulated signal

Figure 11: The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL.

(a) ModelSim output of loop filter

(b) MATLAB processing of output of loop filter

(c) MATLAB processing of ModelSim the output of NCO and input of QPSK modulated signal

Figure 12: The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL.

(a) ModelSim output of loop filter

(b) MATLAB processing of output of loop filter

(c) MATLAB processing of ModelSim the output of NCO and input of QPSK modulated signal

Figure 13: The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL.

Figures 10 and 11 are the simulation results of the classic QPSK ADCOL shown in Figure 2 without the assistance of MLFOE shown in Figure 6 under the two conditions of SNR = 20 and 5 dB.

From the two figures, Figures 10(b) and 10(c), we can see that when SNR is equal to 20 dB, the tracking time is about 0.15 ms and the maximal steady-state phase error approximates to 0 degree.

As shown in the two figures, Figures 11(b) and 11(c), when SNR is equal to 5 dB, the tracking time is about 0.3 ms and the maximal steady-state phase error approximates to 2 degree.

Figures 12 and 13 are the simulation results under the two conditions of SNR = 20 and 5 dB, where the MLFOE has been enabled.

In contrast to Figures 10 and 11, after enabling the MLFOE, from the two figures, Figures 12(b) and 12(c), we can see that when SNR is equal to 20 dB, the locked-in time is about 0.05 ms and the maximal steady-state phase error also approximates to 0 degree. As shown in the two figures, Figures 13(b) and 13(c), when SNR is equal to 5 dB, the lock-in time is about 0.1 ms and the maximal steady-state phase error approximates to 3 degree.

On the other hand, in the case of the four figures, Figures 10(b), 11(b), 12(b), and 13(b), when QPSK ADCRL is locked all frequency offset evaluated by the output of loop filter are equal to 100 KHZ.

From the above simulation results, it is clear that after the MLFOE is enabled, whether SNR is high or not; the performance of our QPSK ADCRL in locked-in time is two times faster than that of the QPSK ADCOL without the assistance of the MLFOE, while the maximal steady-state phase error is almost stable.

On the other hand, in the two conditions of SNR = 20 dB and 5 dB, we test the maximal frequency offset which enables our QPSK ADCRL and the QPSK ADCOL without the assistance of MLFOE to be locked and the corresponding locked-in time and steady-phase error. The results are shown in Table 2. From Table 2, we can see that after the MLFOE is enabled, except for the advantage in locked-in time, the locked-in frequency range of our QPSK ADCRL is four times wider than that of the QPSK ADCOL. Therefore, our QPSK ADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision, which are hardly reconciled for the QPSK ADCOL.

Table 2: The performance advantage of our QPSK ADCRL in locked-in frequency range.

SNR
Architecture
Maximal locked-in
Locked-in time (ms)
Steady-phase error (degree)

Frequency Range (KHZ)

20 db
QPSK ADCOL
±170
0.18
Approximating to 0

20 db
Our QPSK ADCRL
±680
0.05
Approximating to 0

5 db
QPSK ADCOL
±120
0.4
Approximating to 2

5 db
Our QPSK ADCRL
±510
0.13
Approximating to 4

There is no doubt that our QPSK ADCRL has a more robust performance than the QPSK ADCOL without the MLFOE. What is more, to obtain the same improvement in performance as our ADCRL for the existing QPSK ADCOL [23, 24], the simple revision is to add the MLFOE shown in Figure 4 to the QPSK ADCOLs.

Finally, in order to acquire their hardware cost for the different modules of our QPSK ADCRL based on FPGA, the FPGA synthesis tool, ISE Design Suite 12.2, from FPGA vendor Xilinx is used, and its chip of Virtex5 family, XC5VLX50, which supports dynamic reconfiguration technology seen as a core technology to implement SDR [25] on FPGA is selected. The synthesis results are given in Table 3. From Table 3, we can see that although the MLFOE consumes more logic resources than QPSK ADCOL (because many multiplication operations are used, and a pipelined CORDIC architecture [26] is adopted so as to meet the requirement of the latency time), this is worthy for some applications which need a more robust QPSK ADCRL.

Table 3: The hardware cost of the different modules for our QPSK ADCRL.

Module
Number of slice registers
Number of slice LUTs
Number used as logic

QPSK ADCOL
174 out of 28800
580 out of 28800
612 out of 28800

MLFOE
FD
875 out of 28800
892 out of 28800
790 out of 28800

MLFE
603 out of 28800
516 out of 28800
592 out of 28800

Total hardware cost
1652 out of 28800
1988 out of 28800
1994 out of 28800

On the other hand, we can also see that the hardware cost of the whole QPSK ADCRL just make up a small part of logic resources for the FPGA chip selected.

Except for the hardware cost of our QPSK ADCRL, we also investigate its power consumption for the different operating frequencies by the power analysis tool from Xilinx, XPower, which is also important very much in some applications where communication systems need to work continuously by means of a portable power source. The results are shown in Table 4. Form Table 4, we can see that when our QPSK ADCRL operates under the condition of maximum clock frequency, 312 MHZ, which is from the logic synthesis’s result of ISE 12.2, the total power is just 0.594 (W).

Table 4: The power consumption of our QPSK ADCRL for different operating frequencies.

Clock frequency (MHZ)
Dynamic power (W)
Quiescent power (W)
Total power (W)
Junction temp. (C)

312
0.060
0.526
0.594
50.9

250
0.058
0.526
0.583
51

200
0.048
0.525
0.574
51

150
0.039
0.525
0.564
50.9

5. Conclusion and Outlook

In this paper, an efficient QPSK ADCRL is proposed, and a systematic procedure of designing the carrier recovery loop based on FPGA is displayed. On the other hand, a FD in possession of linear characteristic is introduced to supply a more precise frequency offset to MLFE, which is implemented just using shifters and multiply-accumulate units to estimate the frequency offset and assist QPSK ADCOL to lock quickly. The joint simulation results of ModelSim and MATLAB has proved that our proposed architecture can smoothly operate on FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOL. Synthesis result has shown that the hardware cost of FPGA for our QPSK ADCRL is very few, and the result of the power analysis also has proved that our design is valid in power consumption.

Looking at the future, the exploration aiming at deep space must be the tendency of the human development, and the FPGA-based soft defined radio suitable for the environment will be also more widely applied and further studied.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

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