Design of an Interleaved High Step-Up DC-DC Converter with Multiple Magnetic Devices for Renewable Energy Systems Applications

An interleaved high step-up converter topology based on the coupled inductor (CI) and built-in transformer (BIT) is proposed in this study to provide high step-up voltage gain and high efficiency with a low number of power electronic components for renewable energy applications.*e voltage gain is increased by both of the turns’ ratio of CI and BIT, so there is no need to extend duty ratio to obtain high voltage gain. *e proposed topology is much more flexible than those with only either CI or BIT. Moreover, the voltage stress across semiconductor devices can be relatively decreased by adjusting the turns’ ratio of the CI and BIT. In addition, the input current ripple can be reduced when the interleaved structure is applied at the input of this converter. Furthermore, turned-OFF and turned-ON zero current switching (ZCS) conditions for the diodes and power MOSFETs are achieved, respectively, thanks to the leakage inductances of the magnetic devices. Hence, due to the control of the falling current rate of the diodes by the leakage inductances, reverse recovery problem is alleviated. Moreover, the energy of the leakage inductances is recycled by the clamp capacitors avoiding high spikes across MOSFETs. As a result, according to the abovementioned advantages of the proposed converter, MOSFETs with low ON-state resistance and diodes with low forward voltage drop can be used to decrease the conduction losses. A 600W laboratory prototype with 27–400V voltage conversion at switching frequency 50 kHz is built to verify the performance of the proposed converter. Experimental results confirm the theoretical analysis. *e efficiency reaches to 94.6% at full load which is close to the calculated of 95.8%.


Introduction
Renewable energy sources, such as photovoltaic (PV) and fuel cell (FC), have been receiving more attention in recent years as a result of a substantial increase in demand for clean energy, concerns related to electricity generation based on FC, and environmental effects of greenhouse gas (GHG) emissions [1]. e output voltage of FCs and PV panels are relatively less than the required amount. In isolated converters, high voltage gain can be achieved by adjusting the transformer ratio. In [2,3], isolated LLC resonant converters have been proposed. Introduced configuration in [2,3] not only reduces the voltage stress across MOSFETs to half of the input voltage in the low voltage side but also makes the converter suitable for high power applications. Moreover, high operation frequency, high energy density, and wide output ranges are advantages of such converters. Meanwhile, nonisolated converters are typically used to increase the output voltage of PV panels and FCs. e conventional boost converter (CBC) with a simple structure and low cost can be used as a fundamental solution [4]. As a result, appropriate voltage levels can be reached for the inverter-fed AC utility when connecting to the electricity grid. However, the CBC should operate in a high duty ratio to achieve high step-up voltage gain, leading to problems such as the increased voltage rate of power MOSFETs and high peak currents.
Consequently, power MOSFETs with higher on-state resistance should be selected, increasing conduction losses, reducing performance operation, and decreasing conversion efficiency [5]. In [6], a quadratic boost converter is used to increase the voltage step-up gain. Although it does not call for a high duty ratio, this structure still suffers from the high voltage stress across power MOSFET. Switched capacitor (SC) and switched inductor (SI) topologies (known as transformer-less converters) are presented in [7][8][9][10][11] to increase voltage gain. However, SI-based structures suffer from problems such as high voltage stress across semiconductor devices. To deal with this problem, voltage multiplier cell (VMC) converters are introduced [12][13][14].
ese converters can achieve high voltage gain while reducing cost, voltage stress, and duty ratio. By increasing the number of VMCs, voltage gain can be boosted. However, the more the number of VMC is, the more the circuit complexity will be. High switching losses and reverse recovery due to operating under hard switching conditions are other issues associated with these converters. Coupled inductors (CI) are other structures to obtain high step-up voltage gain [15][16][17][18][19][20][21][22].
ey can provide zero current switching (ZCS) turn-on for MOSFETs thanks to the leakage inductances of the CI, which will decrease switching losses and attenuate the reverse recovery problem. Nevertheless, voltage spike during switching transition due to the leakage inductor is the main disadvantage of CI-based converters. Passive clamp circuits can be implemented to recycle the leakage-inductor energy and avoid efficiency degradation. To decrease voltage stress across semiconductor devices, improve efficiency, and recycle the leakage-inductor energy, CIs can be implemented with VMCs [23][24][25][26]. A high step-up converter is developed in [23] with low voltage stress across the main power switch, in which voltage gain is increased by applying one CI and two VMCs. Moreover, a capacitor is being charged during the switch-off period using the energy stored in the CI, increasing the voltage transfer gain. e energy stored in the leakage inductance is recycled using a passive clamp circuit, reducing voltage spike during switching transition. In addition, a built-in transformer (BIT) can be utilized with CI to improve voltage gain further. Due to the zero average current of the primary windings of the BIT, the RMS current is also reduced. us, a low volume core can be selected when fabricating the BIT. Nevertheless, the single-phase nature of these converters restricts them to low power levels. To use high voltage gain converters at high power, minimize the input current ripple, and increase reliability, interleaved converters have been introduced. e abovementioned structures (i.e., SC, CI, and VMC) are adopted to interleaved topologies to achieve high step-up voltage gain [27][28][29][30][31][32][33][34][35][36][37][38][39]. An interleaved boost converter with a bi-fold Dickson voltage multiplier is presented in [40], in which several diodes and capacitors are employed to increase the overall voltage gain. However, the added number of diodes and capacitors increases losses and reduces efficiency. Another interleaved boost converter using two CIs and a VMC is developed in [41], achieving a very high step-up voltage gain without a high turn ratio. e voltage stress across the semiconductor switches and the passive components is reduced to lower than the output voltage. Interleaved high step-up converter presented in [42] uses BIT and VMC to have more flexible voltage gain. is topology delivers benefits such as high voltage gain, low voltage stress across the power MOSFETs, a low number of components, and low input current ripple. To reduce the size and improve transient response, switching frequency should be increased, leading to increased switching losses. Interleaved boost converter in [43] utilises the clamp capacitors and integrates the secondary winding of the BIT. Nevertheless, the voltage gain is low and can be increased when adding CI structure.
In this study, a new interleaved topology is proposed by locating the secondary windings of the CI between the main MOSFETs and the primary winding of the BIT. In such a topology, the voltage gain is proportional to the multiplication of the turn ratios of CI and BIT. e proposed converter delivers the following advantages: (1) High voltage gain (as a result of windings of the BIT and CI) (2) Low voltage stress across MOSFETs and diodes (3) Low input current ripple (4) Zero current switching (ZCS) turned-OFF condition for diodes (5) Zero current switching (ZCS) turned-ON condition for MOSFETs (6) Alleviated reverse recovery problem of the diodes (7) High conversion efficiency (8) Low number of components e rest of this study is organized as follows. e proposed converter and its operational principle are presented in Section 2. e performance analysis of the proposed converter is studied in Section 3. Performance comparison and numerical design are discussed in Section 4 and 5, respectively. e experimental results are given in Section 6. Finally, conclusions are drawn in Section 7.

Operational Principle of the
Proposed Converter e abstract model of the proposed converter is illustrated in Figure 1. As can be seen, the built-in transformer (BIT) and coupled inductor (CI) structures are utilized in this converter.
is converter can achieve high voltage gain by adjusting the turns' ratio of the BIT and CI. Two main power MOSFETs (S 1 and S 2 ), four diodes (D 1 , D 2 , D 3 , D 4 ), and three capacitors (C 1 , C 2 , C 3 ) are some other components of this converter. L m1 and L m2 also represent the leakage and magnetizing inductances of the CIs, respectively. BIT consists of primary, secondary, and tertiary windings with N 1 , N 2 , and N 3 number of turns. L LKb also indicates its leakage inductor. Turns' ratios of the CI and BIT are defined as n � n 2 /n 1 and N � N 2 /N 1 � N 3 /N 1 , respectively. e proposed converter has 10 main operating modes in a single switching period. However, due to the symmetrical feature of the topology, only five operating modes are analyzed in detail in the following. e key waveforms of the proposed converter 2 International Transactions on Electrical Energy Systems and the related equivalent circuits in each mode are depicted in Figure 2 and Figure 3, respectively. (2) . At t 1 , S 2 is turned-OFF. During this mode, the parallel capacitor C S2 is being linearly charged by the current of i Lm2 . e voltage across the switch S 2 is given by At t 2 , the diodes D 2 and D 4 are turned-ON. In this mode, the leakage inductance L LK2 is discharged into the clamp capacitor C 1 . A positive voltage is applied across the primary winding of the BIT. e output load is supplied by the output capacitor and the secondary winding of the BIT:

Mode 4 [t 3 − t 4 ].
At t 3 , the current of diode D 2 reaches to zero, and it is turned-OFF with ZCS. During this mode, the clamp capacitor voltage V C1 is equal to the voltage across power MOSFET S 2 . e current flowing through D 4 is proportional to the leakage inductor's current i LKb . At the end of this mode, the turn-ON pulse is applied to S 2 and turns it ON with ZCS performance: At t 4 , S 2 is in ON-state. During this mode, the current through L LKb is decreasing. At the end of this mode, the current flowing through L LKb reches to zero.
In addition, the current through D 4 decreases and its falling rate is controlled by the leakage inductances:

Voltage Gain Expression.
e voltage across L m1 is equal to V in and V in − V C2 for the switch S 1 being in ON-and OFF-state, respectively. By applying the volt-second balance principle to L m1 , the voltage across the capacitor C 2 can be calculated as   International Transactions on Electrical Energy Systems 3 e voltage across L m2 is equal to V in and V in − V C1 for S 2 being in ON-and OFF-state, respectively. By applying the volt-second balance principle to L m2 , the voltage across the capacitor C 1 can be obtained as Using the average currents of the diodes and equations (4) and (8), the curring passing through them diodes can be calculated as where D 23 and D 78 are normalized time durations of mode 3 and mode 8, respectively. Using (13)- (17), the average currents of the magnetizing inductances can be obtained as According to Figure 2, the following equation is obtained:  International Transactions on Electrical Energy Systems By considering the leakage inductances in the steadystate analysis, the voltage conversion ratio is derived as where For Q � 0, the ideal voltage gain of the proposed converter can be calculated as e effect of the leakage inductance on the voltage gain is shown in Figure 4. As can be seen, the voltage gain of the proposed converter is decreased by increasing the leakage inductances.

Voltage Stress Analysis of the Semiconductor.
From the mode 3, voltage stress of the power MOSFETs can be expressed as e voltage stress across diodes are given by (24) Figure 5 shows the normalized voltage stress across the semiconductor devices. As seen, the voltage across MOS-FETs is decreased when increasing the turns' ratio of the CI. Figure 2 and the steady-state analysis, the current stresses of the MOSFETs and diodes are obtained as i S1,rms � i S2,rms � I out N(n + 1)  International Transactions on Electrical Energy Systems From (26) and (27), the RMS currents through the capacitors C 1 , C 2 , and C O are derived as

Current Stress of the Components. According to
Current i LK1 (i LK2 ) is equal to I Lm1 − Ni C2,rms (I Lm2 + Ni C2,rms ), so using (29), its RMS value can be expressed as e RMS value of i LKb can be derived using (27) as below:

Input Current
Ripple. e input current ripple of the proposed converter is given by e normalized input current ripple with the base value of V out /L m f S is shown in Figure 6. As shown, the input current ripple is decreased by the turns' ratio of the BIT and CI. Figure 7 shows the equivalent circuit of the proposed converter together with its parasitic resistances. In fact, the effects of ON-state resistances of MOSFETs and diodes, forward voltage drops of the diodes, switching losses, resistances of the windings of the magnetic devices, and equivalent series resistance (ESR) of the capacitors should be considered to calculate the efficiency.

Efficiency Estimation.
Due to the ZCS turn-ON condition for MOSFETs, the total power losses in the MOSFETs relates to conduction losses and the switching losses during turning OFF: with r DS1 and r DS2 being the ON-state resistances of S 1 and S 2 , respectively. ON-state resistance (r D ) and forward voltage drop (v FD ) of the diodes can also contribute to power losses as below: e power losses related to equivalent series resistance (ESR) of the capacitors can be written as e core losses are given by where V e is the volume of core, B is maximum flux density, A, α, and β are the Steinmetz parameters given in datasheet of the selection core. e calculated core losses for each of the CIs are about 2.25 W, where it is about 1.5 W for the BIT. erefore, the total dissipations of the cores is about 6 W. Total power losses of the proposed converter can be written as P Loss � P MOSFETs + P D + P C + P Wire + P core .   Figure 7: e equivalent circuit of the proposed converter considering the parasitic resistances. 6 International Transactions on Electrical Energy Systems Finally, the efficiency and the voltage gain of the proposed converter can be obtained as By calculating the RMS currents through the circuit components in Section 3.3, the power losses related to these components can be calculated. e components specifications of the fabricated prototype in Table 1 are assumed to be as e conversion efficiency and the voltage gain of the proposed converter are plotted in Figure 8. As shown, at a given voltage gain, by implementing of higher turns' ratios, the duty ratio can be decreased.

Performance Comparison
A performance comparison is made between the proposed converter and the previously presented interleaved converters in [28,31,35,[38][39][40][41]43]. e results are provided in Table 2 and Figure 9. According to Figure 9(a), the voltage gain of the proposed converter with n � N � 1 is higher than the proposed converters in [38,43]. e presented converters in [28,35] have higher voltage gain than the proposed converter; however, as shown in Table 2, these converters have more number of components than the proposed converter. Moreover, Figure 9(b) shows the voltage stress across semiconductor devices versus different turns' ratio. As can be seen, the proposed converter has resulted in the lowest voltage stress across power MOSFETs among all other converters for the turns' ratios more than 3. Moreover, as shown in Table 2, measured efficiency of the proposed converter is 94.6%. According to the output voltage 400 V, output power 600 W, and switching frequency 50 kHz, measured efficiency of the proposed converter is a reasonable and acceptable value. Furthermore, the voltage gain and the voltage stress across the semiconductors in the proposed converter can be controlled by the turns' ratio of the CI and BIT, making the design more flexible than its similar competitors.

Numerical Design
In this study, the circuit components are designed based on the following values: In addition, the turns' ratios of the CI and BIT are assumed to be n � 1 and N � 2, respectively.

CI and BIT Design.
e magnetizing inductors of the CI are designed based on the input current ripple, which is considered 3% of input current: EE55 ferrite cores are chosen for CI. e cross-sectional area A C and the maximum flux density B sat are 354mm 2 and 320mT, respectively. n 1 is obtained as e value of n 1 can be obtained as where B MAX � 300mT is the maximum allowed swing of the flux density. During mode 3, when S 1 is in ON-sate and S 2 is in OFFstate, the voltage across the primary winding of the BIT can be obtained as EE55 ferrite cores are chosen for BIT. e cross-sectional area A C and the variation of the magnetic flux density ΔB are 354mm 2 and 200mT, respectively. N 1 is calculated by Proposed Converter and [31], [39], [40] with K=2, [41] [28] [35] [38], [43] 0.  International Transactions on Electrical Energy Systems to section 3). e voltage across the capacitors C 1 � C 2 and C out are 69.2V and 400V, respectively.
By assuming the voltage ripples as x%V C1,2 � 8%V C1,2 and x%V Cout � 3%V out , the capacitors' values are obtained as follows:

Selection of Semiconductor
Devices. e semiconductor devices are selected according to their voltage stress and the currents flowing through them (the maximum and RMS values). us, (25)- (27) can be used to select appropriate semiconductor devices.

Experimental Verification
To validate the practical feasibility of the proposed topology a 600 W, 27 V input to 400 V output laboratory prototype with the specifications provided in Table 1 is fabricated. e photograph of the prototype is illustrated in Figure 10. e duty ratio is approximately 0.61. In Figure 11(a), the experimental results of the input current and the currents through the leakage inductances of the CI are shown. As shown in this figure, according to the symmetrical configuration, input current phases are equal and also the input   current ripple is small. erefore, due to the equal current sharing between two phases, the ripple cancellation is obtained. Figure 11(b) shows the output voltage and the output current. In Figure 11(c) and Figure 11(d), the experimental results of the voltage and current waveforms of the main switches S 1 and S 2 are illustrated. As can be observed, ZCS turn-on condition is provided for both switches. Figure 12(a) and Figure 12 (23) and (24), the voltage stress of diodes are obtained V D1 � V D2 � 133.3V and V D3 � V D4 � 600V. As it clearly shows, ZCS turn-off condition is achieved for all of diodes. So, the reverse recovery problem of the diodes is alleviated. Dynamic response is shown in Figure 12(e).
Measured and calculated efficiency curve of the proposed converter is illustrated in Figure 13(a). e maximum efficiency of 96.5% is occurred at 500 W. Measured efficiency under full-load condition (600 W) is 94.6% which is almost close to the calculated of 97%. Figure 13(b) shows pie graph of the losses distribution at full load (600 W) which is 18.51 W. Power losses due to windings, cores, diodes, MOSFETs, and capacitors are 4.95 W, 6 W, 3.81 W, 3.36 W, and 0.39 W. It is seen the calculated and measured conversion efficiencies are almost close and confirm each other.

Conclusion
An interleaved high step-up converter topology based on the coupled inductor (CI) and built-in transformer (BIT) is proposed in this study. e proposed converter has the following features: (1) By using BIT and CI, high voltage gain without extreme duty ratio is achieved.
(2) e proposed converter is much more flexible than the converters with only one of this magnetic means because of having an extra degree of freedom with simultaneous implementation. (3) By increased turns' ratio of CI and BIT, the voltage stress across MOSFETs relatively is decreased which facilitates the utilization of low voltage-rated MOSFETs with low ON-state resistance. (4) Due to the interleaved structure at the input of this converter, the input current ripple is minimized (5) e leakage inductances of the BIT and CI provide turned-OFF and turned-ON ZCS conditions for all the diodes and power MOSFETs, respectively. (6) e energy of the leakage inductances is recycled by the clamp capacitors avoiding high spikes across MOSFETs. Moreover, the reverse recovery problem of the diodes is attenuated due to the leakage inductances of CI.
It is worth noting that the voltage stress across output diodes is higher than the output voltage which is the main advantage of the proposed converter. Finally, a laboratory prototype with 27 V-400 V voltage conversion with the conversion efficiency of 94.6% at full load (600 W) has been implemented and tested to demonstrate performance of the proposed converter. As a result, the proposed converter is suitable for renewable energy system applications.

Abbreviations
ZCS: Zero current switching D: Duty ratio M: Voltage gain n: Turns' ratio between n 1 and n 2 N: Turns ratio between N 1 and N 2 and N 1 and N 3 µF: Micro-Farad µH: Micro-Henry

Data Availability
e data used to support the findings of this study are available from the corresponding author upon request.

Conflicts of Interest
e authors declare that they have no conflicts of interest.