Design and Implementation of Radar Cross-Section Models on a Virtex-6 FPGA

. The simulation of radar cross-section (RCS) models in FPGA is illustrated. The models adopted are the Swerling ones. Radar cross-section (RCS) which is also termed as echo area gives the amount of scattered power from a target towards the radar. This paper elucidates the simulation of RCS to represent the specified targets under different conditions, namely, aspect angle and frequency. This model is used for the performance evaluation of radar. RCS models have been developed for various targets like simple objects to complex objects like aircrafts, missiles, tanks, and so forth. First, the model was developed in MATLAB real time simulation environment and after successful verification, the same was implemented in FPGA. Xilinx ISE software was used for VHDL coding. This simulation model was used for the testing of a radar system. The results were compared with MATLAB simulations and FPGA based timing diagrams and RTL synthesis. The paper illustrates the simulation of various target radar cross-section (RCS) models. These models are simulated in MATLAB and in FPGA, with the aim of implementing them efficiently on a radar system. This method can be generalized to apply to objects of arbitrary geometry for the two configurations of transmitter and receiver in the same as well as different locations.


Introduction
Radar cross-section is used to describe the amount of scattered power from a target towards the radar, when the target is illuminated by RF energy.The intensity of backscattered energy that has the same polarization as the radar's receiving antenna is used to define the target RCS [1].RCS is used as means of discrimination.In simulations, the control parameters in the resulted RCS model are optimally tuned using an algorithm so as to show the full potential of the proposed RCS model.The algorithm along with mathematical calculations computes and plots Swerling statistical models.
The methodology adopted to design the simulation of RCS model is as follows: (a) development of RCS models for simple and complex objects; (b) generation of the Swerling Random Sequences; (c) verification of results in MATLAB R-2013 real time simulation software; (d) implementation of RCS models in FPGA using VHDL code by Xilinx ISE v12.1ISE; (e) application of simulated models to a radar system.
Here the RCS models are developed for simple and complex objects such as ellipsoid, sphere, and cylinder using MATLAB which calculates the backscattered RCS for a perfectly conducting sphere and Spherical Bessel functions are computed using series approximation and recursion.Then Swerling Random Sequences are generated for exponential and Chi-square, degree 4. Then all the above results are simulated in MATLAB and implemented on FPGA using VHDL code using XILINX software.Finally the simulated models are applied to the radar system.

Generation of Swerling Random Sequences
Swerling Target Models are models of probability density function of the radar backscatter from a complex target for rotating surveillance radar [2].Table 1 illustrates this concept for scan-to-scan and pulse-to-pulse probability density function of power for exponential and Chi-square, degree 4.
In this paper we use primarily two methods to generate Swerling models; they are as follows: (1) exponential power distribution, (2) 4th degree Chi-square power distribution.
Probability density functions are simulated to verify if random variables are following the distribution.The radar cross-section of complex objects is given by Swerling models.The characteristic plot of Swerling random variables obtained in real time simulation environment is the probability distribution function for RCS fluctuation of complex objects [3].
The exponential power distribution is as defined by the following equation: where  = − ln  and further   () = probability density function,  = random number,  = mean RCS, and  = RCS.The exponential power distribution method to generate a Swerling model is observed in the Agilent spectrum analyzer and the simulation results of exponential power distribution [4] are obtained, which are illustrated in the following: where  = −/2ln (12),   () = probability density function,  = random number,  = mean RCS, and  = RCS.

Generation of Uniformly Distributed Random Numbers
We use linear feedback shift registers for generating our 32-bit uniformly distributed random number.The term uniformly distributed random number makes it clear that the exponential distributions and the Chi-square distributions are derived by these uniformly distributed random numbers and the methods are stated in the algorithm designed along with the mathematical formulations in VHDL syntax as illustrated below.A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state.
The IP core generator used in XILINX is CORDIC IP core generator.It is a trigonometric Sine-Cosine generator.Libraries cannot be used as they are only for simulation and cannot be used for synthesis purposes [5].
The following are the steps to obtain the received power from the target for the generated RCS models.(c) Scale the random number between 0 and 1 using divider (if 16-bit random number is generated we need to divide by 65,536 to get in range 0-1).
(d) Input the values to tanh −1 to calculate logarithm.
(e) Multiply ln values with RCS average.
(f) The RCS models generated are used to get the received power from a target.
The algorithm for random variable generation in VHDL is designed as follows, as the description of the designed algorithm helps to ground what techniques are adopted.Input the values to tan −1 h to calculate logarithm and multiply the natural log ln values with RCS average.
The RCS models generated are used to get the Received power from a target.

FPGA Implementation
The block diagram in Figure 1 illustrates the FPGA implementation [6].The Chip Scope Pro tool is used to model the XILINX ISE design on to the Hardware FPGA-Virtex-6.The bit stream file generated in XILINX ISE is ported on the Virtex-6 FPGA kit.The digital to analog converter takes the digital data from Virtex-6 FPGA and converts it into analog format and displays it on the oscilloscope.Chip Scope Pro tool solution helps minimize the amount of time required for downloading and debugging.Further it is described how the target RCS influences the radar detection performance which constitutes the representation of control parameters of RCS.The FPGA implementation is done through both compile time and run time parameters which include normalization range, distance threshold, and fade cycle length which are involved in registers, which are user defined and also can be changed during the run time.These control parameters create a user defined environment in which the response obtained from FPGA can adapt itself to this environment both statically at compile time and dynamically at run time.The streaming data obtained from this FPGA solution response is further processed onto the host computer.The FPGA implementation is modular in nature in which the design consideration can be further modified based on the future requirements in the FPGA implementations.
The FPGA implementation is verified in simulation using XILINX ISE and in hardware on an innovative integration Virtex-6 FPGA hardware board running at frequency of 200 MHz.
The following procedure was performed for FPGA hardware.
(1) The host P.C sends the input RCS models to the hardware in the form of input first-in first-out (FIFO) over the FMC Bridge-PCI Express Bus.
(  The advantages of using the target RCS on FPGA hardware are as follows.
The XILINX Virtex-6 implementation is estimated as very much faster than equivalent "C" language program running on a 3 GHz Intel Xeon processor.The FPGA implementation is further implemented in radar pulse deinterleaving which is basically utilized as an electronic warfare application.The other applications of this FPGA implementation involve the streaming with the data evolved.

Results Obtained in FPGA
The simulation is carried out using Model-Sim software.The target device selected is Virtex-6.The functional and timing simulations were carried out.The output is obtained after 156 clock cycles.The maximum frequency obtained is 35.750MHz's.In this case the target device selected is xc6vlx240t--3ff324.The simulation time is 2,000,000 s.In this the model based design approach is provided for an integrated workflow [6].This model based design speeds up the algorithm development with a unified design environment and automates the manual steps in FPGA implementation to enable shorter iteration cycles from the XILINX environment [5].
Figures 2 and 3 illustrate the simulation results for different objects with respect to the object names as seen in these figures such as clock (clk1 and clk2), exp rv, rcs avg, rnd num,tanh den, tanh num, temp num, tanh out, and ln out along with various instances and processes for FPGA based exponential distribution as well as for 4th degree Chisquare.Further the synthesis results are determined by a  The analog to digital converter simulated in a XILINX based chip scope pro analyzer above is a 12-channel ADC elucidated in Figure 4, in which the data port is a 12-channel ADC RAM Component.The above simulation is done through the JTAG chain which consists of two devices which are device 0 consisting of SYSTEM ACE COMPONENT and device 1 consisting of ADC RAM Component (from channel 0 to channel 12) where in this case the sample buffer is full.The plot in Figure 3 is a data versus time plot in which the -axis represents the minimum 0 to maximum 511 units, and -axis represents minimum −8192 to maximum 8191 units.
In the working hardware the RCS models are received directly on FPGA from chip scope pro analyzer which is a pulse measurement module in the form of analog to digital converter simulated as shown in Figure 4 with a multiplexer control and the streaming output data is streamed continuously to the hardware processing unit at the frequency of 5 microseconds and 10 microseconds via a USB-FPGA interface module 1.15x as illustrated in Figure 7 to Figure 10 for both 4th degree Chi-square power distribution and exponential models.The FPGA implementation is capable of keeping the RCS models at the rate that is expected to be received from the environment.Working procedure for both 5 microseconds and 10 microseconds exponential and 4th degree Chi-square models is as follows.
Figure 5 illustrates the exponential power distribution, with a free run trigger in the Agilent spectrum analyzer with the attenuation of 40 dB. Figure 4 also elucidates the radar signal simulation with the processing environment to generate a Swerling model.The average type of power used is the log power.The video bandwidth of the spectrum analyzer is given as 270 kHz and the resolution bandwidth is 270 kHz; the center frequency is given as 210 kHz with span of 30 MHz.There is a sweep of 1 ms with 1001 pts.Further the intermediate frequency (IF) gain is low.
Figure 6 illustrates the 4th degree Chi-square power distribution Swerling model, with a free run trigger in the Agilent spectrum analyzer with the attenuation of 40 dB.The figure also elucidates the radar signal simulation with the processing environment to generate a Swerling model.The average type of power used is the log power.The video  bandwidth of the spectrum analyzer is given as 270 kHz and the resolution bandwidth is 270 kHz; the center frequency is given as 210 kHz with span of 30 M Hz.There was a sweep of 1 ms with 1001 pts.The probability density function of power as illustrated in Table 1 is for the individual echo powers with radar cross-section proportional to each other.
As seen from Figures 7 and 8, the echo power in Figure 6 represents the exponential probability density function of power which is equal to −51.7 dBm with the marker frequency of 5.55 MHz, while the echo power in Figure 7 represents the 4th degree Chi-square probability density function of power which is equal to −53.55 dBm with the marker frequency of 5.76 MHz.
The plot shown in Figure 7 illustrates the exponential model operated at 5 s frequency.The multiplexer controlled streaming output data is streamed continuously to the hardware processing unit at the frequency of 5 microseconds.
The plot shown in Figure 8 illustrates the exponential model operated at 10 s frequency.The multiplexer controlled streaming output data is streamed continuously to the hardware processing unit at the frequency of 10 microseconds.
Further as illustrated in Figures 9 and 10 for 5 s and 10 s, frequency for 4th degree Chi-square power distribution is via a USB-FPGA interface module 1.15xs as illustrated.

RCS Variation for Two Point Scatters in MATLAB
The algorithms in MATLAB real time simulation environment are illustrated in Sections 6.1 to 6.4 with the detailed mathematical expressions with the MATLAB based syntax of the RCS of different objects and calculation steps, as the description of the designed algorithms helps to ground what techniques are adopted.
(a) First generate random numbers using VHDL code.(b)Those random numbers are taken as .

Figure 4 :
Figure 4: Bus Plot of ADC for the FPGA device XC6VLX240T.

Figure 7 :
Figure 7: For the 5 s frequency for exponential model.

Figure 12 :
Figure 12: Variation in RCS of two isotropic scatterers with frequency.

Figure 13 :
Figure 13: Maximum radar range dependency on RCS.
Point scatterers are separated by scat spacing meter.Initially the two scatters are aligned with radar line of sight.The aspect angle is changed from 0 degrees to 180 degrees and the equivalent RCS is computed according to the mathematical expressions in MATLAB based syntax illustrated below.Plot