Design of an Adaptive Predistorter for Solid State Power Ampliﬁer in Wireless OFDM Systems

Orthogonal frequency division multiplexing (OFDM) is a powerful modulation choice for wideband wireless communication systems. However, its high peak-to-average power ratio greatly limits the high power ampliﬁer (HPA) power e ﬃ ciency. Here, we present the design of an adaptive predistorter to compensate the distortion caused by the HPA. Speciﬁcally, we deal with the implementation issue of the proposed predistorter in Lee and de Figueiredo’s work (2006). The performance improvement by predistorter is veriﬁed by both ﬂoating-point simulation and ﬁxed-point simulation, where the latter includes the distortion e ﬀ ects from the hardware. The bit widths for OFDM signals, ADC, and DAC are evaluated, and the bit width of 10 is shown to be su ﬃ cient for the hardware design.


Introduction
Othogonal frequency division multiplexing (OFDM) has attracted a lot of attention from the modern wireless communication community, because of its several desirable features for high-speed data transmission.In OFDM, a broadband signal is broken down into multiple narrowband subcarriers and implemented efficiently by using the IFFT algorithm [1].OFDM advantages include: lower intersymbol interference, efficient use of frequency/spectrum through the use of different modulation/coding across subcarriers, and superior narrowband interference suppression capabilities.However, we need to consider the practical hardware limitations of low-cost RF and mixed signal devices when designing OFDM systems for broadband wireless data transmission.One of them is the high power amplifier (HPA) linearity and dynamic range, since OFDM signals have higher peak to average power ratios (PAPRs) than other high-performance modulations, and thus extra care is required.One of the most promising approaches to the mitigation of the PAPR problem is to use a predistorter applied to the OFDM signal prior to its entry into HPA.Its purpose is to compensate the nonlinearity of the HPA and improve the system performance.Many researchers have been investigating OFDM predistorter schemes [2][3][4][5].However, all of these techniques are based on a general approximation form for the nonlinear system, rather than exploiting specific forms gleaned from physical device considerations.Due to this reason, we proposed a closedform predistorter represented by a few parameters [6].
In this paper, we will apply Rapp's SSPA model [7] for HPA devices and show the implementation plan of the predistorter which was introduced in [6].Furthermore, this paper also provides the design of a tracking algorithm for the case in which the practical HPA is unknown and varying.Finally, the simulation results are presented to investigate the performance improvement from predistorter, and study the distortion effects caused by saturation, overflow, and quantization with different number of bit widths, since the bit width of OFDM baseband (OFDM BB) and DAC/ADC is limited by cost and design constraints in real systems.

System Description
As shown in the block diagram of Figure 1, the proposed OFDM predistorter is placed after the OFDM baseband (BB) block to compensate for the degradation function in HPA.
In Figure 1, r, q, and u are amplitudes of output of the BB, predistorter, and HPA block, respectively.From the normalized Rapp's SSPA model [7], we have where u is the HPA output amplitude, A 0 > 0 is the maximum output amplitude from HPA, and p > 0 is the parameter which controls the smoothness of the transition from the linear to the saturating region.Please note that the phase distortion for HPA is very small and hence can be neglected [7], and thus, the predistorter mainly focuses on amplitude compensation.In order to compensate the nonlinearity of the HPA, using the predistorter, the HPA output u is targeted to be linear to r.Thus, q(r) Thus, we can derive the following equation [6]: When r ≥ A 0 , (3) has no solution, and q has to be clipped which will be explained in the following section.Figure 2 shows a compensation example of the predistorter [6].The upper and lower lines pertain to the PD and SSPA model, respectively, and the solid line represents the compensated effect.It shows similar effect with soft envelop limiter.

Design Architecture
The closed form expression of predistorter output q is shown in the previous section.However, the information of HPA parameters A 0 and p are unknown and time varying in practice.Figure 3 shows the detailed design of the architecture of our predistorter for a real time-varying environment.
The major block in the OFDM predistorter is an LMS block to update A 0 and p estimations and q estimation block which will be explained next in detail.As for other supporting blocks, R/P (rectangular coordinates transfer to polar coordinates) and P/R (polar coordinates transfer to rectangular coordinates) are employed with a 12-stage cordic algorithm.A look-up table is used to store the precalculated values for the calculation of LMS update and q estimation.

LMS Update.
The total period is divided into two stages: the training stage covers the start time and periodic pilot time, and the remaining time is the operation stage (see Figure 4).
During the training stage, q estimation block is off, that is, q is set to be equivalent to the input signal magnitude of r, and correspondent HPA output u is known.The goal during this stage is to track the solution of time-varying A 0 and p by LMS algorithm.We define mean square error as follows: From the appendix, we have the expressions of ∂J(A 0 , p)/∂A 0 and ∂J(A 0 , p)/∂p.For LMS algorithm, expected value is replaced by instantaneous value.Therefore, where μ 1 and μ 2 are step factors which will be defined in the following section, and the initial settings are A 0 (0) = 1 and p(0) = 1. the remaining time (operation stage).Within the operation stage, predistorter is on, and q estimation is calculated based on the LMS estimations of A 0 and p.That is,

q Estimation
Please note that when r(n) ≥ A 0 (n), q(n) is clipped to q max .In this paper, we set q max = 8, which will be shown to be suitable in the numerical result session.

Look-up Table.
Five sets of function results are required to be stored in the look-up table to calculate the following functions: 16.The total size for all of these five look-up tables is 26874 × 16 whose area is less than 0.5 mm 2 for CMOS18.

Complexity Evaluation.
Based on the precalculated parameters, ( 5) can be expressed as After HPA parameters A 0 and p estimation, the q is estimated by Therefore, the complexity in total includes 5 addition/subtracitons and 15 multiplications which are relative low.

Numerical Results
From (1), HPA results in a highly nonlinear situation with high input amplitude, and small distortions vice versa.Therefore, a relative level of power back off is required to reduce HPA distortion.Here, we define input back-off (IBO) as where P in is input average power of OFDM signal.Next, we will perform the algorithmic level and hardware level (fixedpoint) simulations, while the latter include all the distortion effects in hardware such as round-off error and coefficient quantization.
OFDM BB  Float point without predistorter Float point with predistorter 12 bits without predistorter 12 bits with predistorter 10 bits without predistorter 10 bits with predistorter 8 bits without predistorter 8 bits with predistorter We set the simulation parameters as follows.
(ii) The average input back-off power is 6.375 dB, if not being mentioned.
(iii) The start training sequence is employed with a length of N 1 = 160 training samples, and every training sample per N 2 = 16 OFDM symbols is applied to the following sequence.
(iv) A 0 and p are both assumed to be Gaussian random numbers with mean of 1 and variance of 0.0025.(v) Step factor μ 1 = 1.5 in training stage and 0.5 in the operation stage, while μ 2 is set to be as much as six times of μ 1 .(vi) The bit width of OFDM output I x , Q x , the bit width of DAC input I y , Q y , and ADC output are evaluated, since the former is limited by the area cost, and the latter is limited by DAC/ADC design.(vii) The channel is assumed as AWGN with variance of η 0 /2.
From Figure 5, it shows that the bit width of 10 is recommended for OFDM BB output, DAC input, and ADC output, since there is not much improvement to increase bit width beyond 10.The proposed implementation plan of predistorter is shown to improve system performance even including degradation effect from hardware.

Conclusion
In this paper, we have provided an implementation plan of the proposed predistorter in [6] to compensate the nonlinear distortion of SSPA.We used an LMS algorithm for time-varying environment, which we have shown to be capable of tracking SSPA parameters.Finally, a fixedpoint simulation including hardware degradation factor was performed to verify the superior performance of the proposed implementation scheme.

A. Derivative of J(A
• −

Figure 4 Figure 2 :
Figure 2: Compensation and clipping effect of SSPA with PD.

Figure 5 :
Figure 5: Bit error rate versus E b /N 0 .