This paper deals with an optimized software implementation of a narrowband power line modem. The modem is a node in automatic meter reading (AMR) system compliant to IEC 61334-5-1 profile and operates in the CENELEC-A band. Because of the hostile communication environments of power line channel, a new design approach is carried out for an S-FSK demodulator capable of providing lower bit error rate (BER) than standard specifications. The best compromise between efficiency and architecture complexity is investigated in this paper. Some implementation results are presented to show that a communication throughput of 9.6 kbps is reachable with the designed S-FSK modem.
International concerns about natural environment preservation have been increasingly serious during the last decades. In fact, one of the most ecologically influencing factors is energy. Besides, energy consumption rise was unexpectedly important and quick, neglecting efficiency and ecological considerations. These facts have pushed several countries to try to change their energy consumption policies.
The widest idea behind operating energy efficiently is called SmartGrid. This concept, as its name suggests, involves integrating intelligence into the whole power grid; generation, transmission, distribution, and management are concerned. The goal is to increase power generation, transmission, distribution, and usage efficiency by reducing power waste, favoring renewable energies, and sensitizing consumers about their actual consumption [
This big concept was only expressed lately after arise of more specific and actually applicable ideas. The first is automatic meter reading (AMR), enabling automated remote meter reading. Later were introduced automatic meter infrastructure (AMI) and automatic meter Management (AMM), which are two expansions providing more consumer- and management-oriented services.
Despite its obvious advantages, AMR have not been yet rolled out significantly. Actually, a major broad deployment inconvenient of smart meters was the lack of reliability on hostile communication environments of power line channel. In fact, early implementations of PLC modems were basic on ordinary amplitude shift keying (ASK) or frequency shift keying (FSK) techniques.
In this paper, we investigate the importance of spread frequency shift keying (S-FSK) modulation scheme to make transmissions robust against narrowband noise and attenuation in such hostile channel. Hence, an intelligent power line communication (PLC) modem solution for automatic meter reading using International Electrotechnical Commission (IEC) S-FSK profile is simulated and implemented using digital signal processor (DSP) [
The paper is organized as follows. In Section
The evolution of meter reading has been outstanding during the last decades. Several power suppliers, distributers jointly with their technological partners, have tried several novel approaches in order to automate meter reading.
The evolution from traditional manual meter reading to actual and future intelligent infrastructures passing through e-meters, semiautomatic meter reading, and fully automated meter reading gave these actors a great experience in this ever-evolving field.
Despite the abundance of the available technologies, power line communication has been agreed to be the best fit for last-mile meter reading and meter management communication. In fact, this technology has one of the lowest costs and is easily set up. Moreover, the technology is now considered as sufficiently ripe to be widely deployed.
PLC, as a technology, is very wide. A myriad of techniques are available using different modulation techniques and different protocols. From another side, the regulation is still under work. Nevertheless, some profiles have already been standardized and are being adopted by the market. The IEC S-FSK profile, for example, is actually one of the most used for AMR because it proved its simplicity and maturity.
In this section, we will briefly introduce automatic meter reading concepts, then present PLC from both technical and technological sides, and finally give a short survey on S-FSK PLC modems.
Automatic meter reading is a technique used to collect data from electricity, gas, water, or other utility meters. Unlike manual meter reading, automatic meter reading relies on communication technologies to collect users’ consumption. Meters send data automatically through a communication network to the management system. Collected data can be then transferred to a central database to be analyzed and used for billing. This means that billing can be based on actual consumption rather than on an estimate based on previous consumption statistics, giving customers better control of their usage of electric energy, gas, or water. From the other side, predicting energy usage remains a key advantage for energy distributors. With AMR, distributors can get accurate information of consumption profile of each consumer and monitor the network in order to prevent or capture defects.
The advantages of AMR are several and obvious: increasing meter reading and billing accuracy and security; permitting a flexible tariff changing; giving user the control over its consumption; enabling a better grid monitoring and load management; remote power disconnection and reconnection.
Automatic meter reading system is summarized by Figure
Different automatic meter reading techniques.
Several automatic meter reading technologies can be used depending on grid topology. Most important ones are as follows handheld, walk-by, and drive-by AMR; public switched telephone network-based AMR; wireless communication-based AMR; power line communication-based AMR.
Power line communication consists of the use of the power lines as a physical communication medium. PLC has been used for data transfer for both indoor and outdoor networks. Anyhow, the profile of these applications is different.
Concerning PLC use for AMR and outdoor communication, PLC is the most approved technology by electricity distributors. In fact, electric network is already well expanded and offers a great coverage. Thus, no additional wireless or wired communication medium needs to be used and deployment costs are then cut.
The main idea behind PLC is the use of the power line to carry radio frequency signals. Actually, a low power modulated signal containing information is added to the electric signal. Data then propagates over the electric network and is detected by remote stations.
Several modulation techniques can be used to transport data over power lines. But most of them are based on frequency modulation. Actually, data is converted to a higher frequency signal which is superimposed to the 50 Hz/60 Hz electrical signal. The signal is then repeatedly transmitted over the network until it reaches the destination node.
Several PLC communication profiles have been proposed and each profile is essentially based on the modulation scheme chosen.
Two different modulation scheme classes can be distinguished: single-carrier modulations; multicarrier modulations.
The first technique is the simpler one. It uses a narrow frequency band for data transfer. Examples of these modulation schemes are FSK, S-FSK, and continuous phase frequency shift keying (CPFSK). These modulation schemes are often chosen for their maturity and implementation simplicity. Though, they do not offer great data transfer rates. Actually, data rates generally range from 300 bps to 2.4 kbps [
The second uses multiple adjacent carriers in order to transfer data. Usually orthogonal frequency division multiplexing (OFDM) or a derived modulation scheme is used. These modulation schemes are applied in order to increase raw data throughput and/or to cope with harsh channel conditions. Broadband PLC is seen as an exciting and effective technology for multimedia distribution within homes.
In either case, AMR PLC technique must handle poor channel quality. In fact, outdoor power lines are exposed to several noise sources. Furthermore, power lines present highly varying impedance due to topology changes and high attenuation. Hence, power line channel quality is considered as time, space, and frequency dependent [
In order to overcome these impairments, high performance processing is unavoidable. This includes channel estimation and equalization, strong forward error correction algorithms, and signal repetition.
In addition to noise and channel quality difficulties, PLC-based AMR has two other main challenges. The first is that unlike usual communication techniques where transfer speed is the most significant criteria, cost and reliability are the most important factors in AMR. The second is the existence of a lot and very different protocols and standards, their specific underlying problems, and interoperability issues.
The communication profile described by the IEC 61334-5-1 standard is based on the S-FSK modulation technique.
S-FSK is a modulation and demodulation technique which combines some of the advantages of a classical spread spectrum system (e.g., immunity against narrowband interferers) with the advantages of a classical FSK system (low-complexity, well-investigated implementations).
As the classical FSK, S-FSK uses two frequencies to transmit binary information at each bit time. By spreading the two used frequencies, S-FSK makes these two channels independent. This characteristic is then used by the demodulator and ensures a better reception quality than FSK. In fact, if signal qualities of the two channels are close, the demodulator makes the decision by comparing the signal on both channels. Otherwise, demodulation is based only on the channel having a better reception quality. Channel quality estimation is calculated using a predefined preamble preceding transmitted data.
Synchronization in this profile is based on zero crossing detection of electric signal. Therefore, the transmission and reception must start on the main zero cross. Due to the phase shift between 50 Hz and the carrier, the zero cross signal may provide incorrect timing of the bit-wise synchronization. To recover this delay the bit synchronization adjustment method is implemented in the modem software. This algorithm based on correlation method can move bit border during reception.
Time is divided into system wide synchronized time slots, and physical frames are only transmitted with the beginning of timeslots.
Timeslot synchronization is achieved using detection of any frame’s preamble and delimiter as described in Figure
Physical frame structure.
As described earlier, communication between meters and management system is done through a special node called access node usually placed at the medium/low voltage (MV/LV) transformer stations. Access nodes are specific nodes that manage the communication on a specific meter network.
This profile uses a master/slave communication paradigm based on polling mechanism. In fact, meters can only respond to queries made by master station. This method combined with slotted time simplifies considerably medium access control.
The modem that we propose in this paper is an AMR PLC modem using IEC61334-5-1 compliant profile and operates in the CENELEC—A band [ digital stage including DSP processor and external memories. DSP processor provides flexible software implementation and easily upgrade to new software version or merging standards; mixed front end based on digital to analog converter (DAC) and line driver for transmitter section, analog to digital converter (ADC) and variable gain amplifier (VGA) for receiver section, and external band-pass filter (BPF); coupling interface makes connection between the mixed front end and the power lines. It provides protection from high voltage and peak voltage/current, attenuation of 50/60 Hz signal, impedance matching to the mains for both transmitter and receiver paths, and nonisolated power supply.
PLC modem functional block diagram.
The use of a DSP permits a greater control over the signal processing stage and a greater flexibility of the implemented S-FSK modem.
This section details S-FSK modulation principle and gives theory and simulations of suboptimum receiver.
S-FSK modulation consists of a binary FSK modulation in which the frequency deviation
The symbols to be transmitted are generated with a rate
A digital signal waveform with binary signaling consists of two kinds of signals
A frequency selective channel with an additive nonwhite Gaussian noise is considered; however, the channel gain
In practical channels, the received signal phase is very difficult or even impossible to track. Thus, the detection process may have to disregard the phase information to avoid complex circuits, at some expense of performance degradation. This is called noncoherent detection [
Using the channel model early presented the received signal under hypotheses
The unknown phase is random with a power density function
The correlation receiver correlates the input signal
The modulus of the envelop detectors’ outputs may be modeled as follows for two orthogonal S-FSK signals:
Under the assumption that the noise is Gaussian, the sampled outputs of the envelope detectors
Under hypothesis
Under hypothesis
Assuming the symbols
In particular, the decision rule uses the following decision values:
The decision rule is to compare likelihood functions and choose the largest:
Implementation of the ML receiver is difficult due to the complexity of formulae from (
In order to describe the receiver, the log-likelihood ratio
Using the distributions (
Logarithm and Bessel function are approached using approximating function. Let
The approximation is defined over
Using (
The proposed receiver decides accordingly to (
Assuming to have knowledge of the first
The performance of different receiver is compared through communication schema implementation using Matlab. A packet-based transmission has been adopted, with preamble length
Figures
BER versus SNRav with
BER versus SNRav with
BER versus SNRav with
From the previous figures, the FSK receiver loses in performance with the increasing of the unbalancing factor; however, the ML S-FSK receiver presents relevant improvement on balanced channels. For bit error rate equal to 10−4, more than 6 dB gain at
For
Priority in design was given to modularity, simplicity, low cost, and reliability. A 32-bit-fixed point general purpose DSP architecture is considered to optimize the software implementation of the S-FSK receiver. The DSP-based digital part communicates, through serial port in full duplex, with the host device. At the other end, DSP communicates, in half-duplex, through power line via a mixed front end coupling interface.
The DSP programming structure was defined to handle in real-time transmitting or receiving S-FSK signal.
The S-FSK base-band modem is obtained by the implementation of an S-FSK modulator at the transmitter side and an improved ML receiver at the receiver one.
The transmitter is composed by three stages: a numeric stage involving a DSP that performs frequency synthesizing with a direct digital synthesizer (DDS); a digital to analog convertor (DAC) capable to generate a linear signal up to its full scale output; line driver delivering amplified signal.
As described in Figure
Modulator block diagram.
It is important to minimize the LUT size since the implementation will be done in an embedded processor where the resources especially the memory size are limited. The sampling frequency
Once the appropriate sine samples are read they serve as input for the DAC. The generated signal by the DAC pin is amplified by the line driver.
The S-FSK modulator generates signal in the CENELEC band from 3 kHz to 95 kHz responding to the following specifications: frequency bandwidth programmable bit rate frequencies
The sampling frequency
The step index
The minimum LUT lengths that satisfy the conditions already cited and the generation of the frequencies
In Table
Orthogonality frequency choice for baud rate 9.6 kbps.
CENELEC band | Frequency (kHz) | Carrier frequency (kHz) | |
---|---|---|---|
|
| ||
A band | 91.2 | 72 | 81.6 |
86.4 | 67.2 | 76.8 | |
81.6 | 62.4 | 72 | |
76.8 | 57.6 | 67.2 | |
72 | 52.8 | 62.4 |
Coherent FSK signals can be noncoherently demodulated to avoid the carrier recovery. The improved ML demodulator is a quadrature receiver capable of detecting signals with unknown phases.
It can be implemented with four correlators as shown in Figure
Implemented improved ML S-FSK receiver architecture.
The signal consists of an in-phase component and a quadrature component. Thus, the signal is partially correlated with
The first
All samples of received bits are processed according to Figure
Different configurations are possible; we have to choose the one that maximizes
Thus, samples’ count during bit time
The DSP processor BF506F, sited to an evaluation board [
To evaluate the complexity of the S-FSK modem software, it is important to determine the consumed cycles and the consumed data memory space [
We have used the data memory to store the LUT table that contains 656 samples encoded on 16 bits.
The cycles’ consumption is limited by the available number of cycles per sample that is governed by the DSP speed which is 400 MIPS.
The DDS algorithm consumes only 2 cycles per sample, one cycle for memory access to read the sample from the LUT, and one cycle for incrementing the reading index. The transfer of DDS samples to DAC convertor requires 10 cycles per sample.
At the receiving site, the demodulator invokes 4 correlators. At each correlator, one sample is treated on 4 cycles to read, multiply, accumulate, and update index.
Finally, we apply
The cycle’s consumptions per sample of these different modules are presented in Table
Memory and processing time analysis results for the PLC-modem DSP implementation.
Module | PM space |
DM space |
Number of cycles |
---|---|---|---|
Modulator module | 1620 | 656 | 3840 |
ADC reception module | 1066 | 160 | 1280 |
Correlation module | 246 | 656 | 2560 |
S-FSK decision module | 87 | 32 | 156 |
Initialization PHY module | 513 | 10 | 2323 |
PHY layer FSM module | 3869 | 822 | 5236 |
The cycle’s consumption of the S-FSK modem software composed of the modulator, demodulator, and PHY layer functionalities according to IEC 61334-5-1 is lower than the available cycles per symbol period
By considering the DSP implementation, we measured an average cycles consumption of 9076 cycles during transmission (21.78% of available cycles) and 9232 cycles during reception (22.15% of available cycles).
Memory consumption is 10.25% for data memory and 45.17% for code memory.
The physical layer is designed and implemented. The remaining available cycles and memory will be used to build upper layers: MAC layer and Application layer.
In this paper, we have described the design and optimized DSP implementation of an S-FSK profile for a PLC node in an AMR system. To overcome power line channel condition, an improved ML S-FSK receiver is used. Improved receiver presents close error performance to the ideal ML S-FSK receiver but has simplifier architecture.
Analysis of new receiver reveals excellent results in terms of memory occupations, required cycles, and BER performances.
Data rate of 9.6 kbps is easily provided with flexibility and programmability to change receiver parameters.
This work was supported by the Embedded Systems Technology (EBSYS) SmartGrid Division and GRESCOM Research Laboratory of Higher School of Communication of Tunis.