Journal of Electrical and Computer Engineering
Volume 2015 (2015), Article ID 679505, 6 pages
http://dx.doi.org/10.1155/2015/679505

Research Article

High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates

Amirhossein Fereidountabar, Gian Carlo Cardarilli, and Marco Re

Department of Electronic Engineering, University of Rome “Tor Vergata”, 00133 Rome, Italy

Received 13 July 2015; Accepted 13 August 2015

Academic Editor: Chi Chung Ko

Copyright © 2015 Amirhossein Fereidountabar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Mathematical analysis and optimization of a carrier tracking loop are presented. Due to fast changing of the carrier frequency in some satellite systems, such as Low Earth Orbit (LEO) or Global Positioning System (GPS), or some planes like Unmanned Aerial Vehicles (UAVs), high dynamic tracking loops play a very important role. In this paper an optimized tracking loop consisting of a third-order Phase Locked Loop (PLL) assisted by a second-order Frequency Locked Loop (FLL) for UAVs is proposed and discussed. Based on this structure an optimal loop has been designed. The main advantages of this approach are the reduction of the computation complexity and smaller phase error. The paper shows the simulation results, comparing them with a previous work.

1. Introduction

PLL is used in many communication systems for synchronization and tracking of carrier. Use of PLL assisted FLL is very common in a lot of receivers for reducing locking time and avoiding false locks. The typical trade-off in tracking loop design is bandwidth versus dynamic performance. The effect of noise increase is increment of the loop bandwidth, while dynamic tracking error increment decreases the loop bandwidth [1].

Because speed of the UAVs is limited (against GPS and LEO that have high speed), therefore shift of the carrier frequency is almost small; hence the bandwidth of our tracking loop is narrow so it has two advantages, tracking ability of high dynamic carrier and the noise decreasing.

It is obvious that limit of the Doppler shift tracking has direct relationship with the loop bandwidth and bandwidth of the loop corresponds to the carrier bandwidth with attention to Doppler shift that should take it into account for the loop design.

Most of the above phenomena are related to the presence of the Doppler effects that shall be compensated at the receiver side. This puts forward higher requirements for the carrier tracking structure due to the high changing in carrier frequency. The goal of this paper is the improvement of the tracking loop dynamic behavior proposing a new topology based on the modified third-order PLL assisted second-order FLL, which has a smaller phase error. This new structure has been simulated and the results are compared to the previous works. Reducing the phase error allows obtaining a faster tracking of the input signal. For designing the tracking loop, there are some methods such as two-term quadratic functional with weighing [2] or optimization process that poses trade-off between noise and bandwidth [3]. In this paper a new method based on the mathematical modification of the poles inside and outside the unitary circle is proposed.

2. Loop Structure

A typical communication front-end stage extracts the in-phase and quadrature components from the received signal. The NCO generates the local in-phase and quadrature reference signals at the sampling rate for coherent correlating. The output of the loop filter modifies the phase and frequency of the NCO every .

The phase and the frequency of the NCO are modified every period, with the same pace of the loop filter output. The in-phase and quadrature components are then sent to the inputs of the tracking loops. The base-band linear model of the third-order PLL assisted second-order FLL tracking loop used in our work is shown in Figure 1. In this model, we introduced a differential block in the frequency error path for evaluating the frequency error. In the following sections, we will use the methods developed in [4, 5] for analyzing this structure. The analysis results will be used for the design of an optimized tracking loop. The in-phase and in-quadrature correlation of the received signal with the locally generated replicas are the inputs of the tracking loops [4]. In our analysis, the signals obtained from the front-end section can be expressed, for the th sample, as

where is the results of correlation between the input signal and the NCO output, is the phase estimation error, and is the frequency estimation error. is the integrations time and is the code correlation function. The phase discriminator and the linear frequency discriminator have the following outputs:

where and can be written as [4]

A mathematical model of the FLL and the PLL is shown in Figure 2.

Figure 1: Structure of the third-order PLL assisted second-order FLL.

(a)

(b)

Figure 2: Block diagrams of (a) second- and (b) third-order digital loop filters excluding last integrator (the NCO).

In this paper combining both of the filters (Figure 2), applying some modifications (for finding suitable factors) [2] and optimizations (described in Section 4), we achieve the final tracking loop of Figure 3.

Figure 3: The structure of the optimum PLL for tracking Doppler rates.

Considering the transfer functions of the NCO, , and the loop filters, and , the loop equations become [5, 6]

where is the error of the loop which also represents the NCO input.

The expressions for , , , and are

3. Loop Performance

In this second-order FLL, the overall frequency transfer function, , can be expressed in terms of the loop filter, , the numerically controlled oscillator, , and the discriminator function, , obtaining [7, 8]

Also, we have

where is the phase difference function. and are the transformations of and . For the third-order PLL, the loop transfer function is [2, 8]

By expanding the function, we have

4. Loop Optimization

In this section, the optimization of the PLL assisted by FLL loop will be considered. The goal of this section is to find an optimal filter for the loop, able to optimize the dynamic behavior and the noise bandwidth.

Let us assume the following performance function [2, 6]:

where is the deterministic part of the phase difference between the incoming and the generated phase. The parameter is determined on the basis of noise bandwidth considerations:

The noise part of (10) can be expressed in terms of the closed loop transfer function, . is the noise spectral density of noise and is related to the input noise spectral density by

The closed loop transfer function is

Applying Parseval’s equation in (10), we have

In this paper we rewrite the function that should be minimized as the product of two new functions, and ,

For minimizing we can minimize . To do this minimization, we used the method proposed in [9]. Applying some factorization to the equation derived by [9] and taking into account (11) and (14), (10) will be expressed:

in which = Θ(z) Θ(z⁻¹).

Let , where is the optimal loop transfer function we are searching and is the variation that should be minimized on the optimized . Substituting this equation into (16) and setting the variation of and to zero, we complete the standard vibrational procedure [6, 8]:

The notation indicates that the value is kept within the interval .

With the method proposed in [2], the transfer functions of the loop blocks are computed. However, in this paper we use a new method based on the separation of the poles to find the function of the loop blocks. In this way we reduce the amount of computation in comparison to the former works.

With assumption,

where all the poles in are inside the unit circle while has all the poles outside the unit circle.

So, we have from (18) that [4]

From (20), we can find that the poles in the first part are and those in the second part are , and we have [6]

Therefore we have

By putting (22) to zero, we obtain

where is defined such that all the poles are outside the unit circle. The corresponding optimal loop filter is

Therefore

According to [2], loop factors can be computed. In our paper these factors are , , and .

5. Simulation Results

In this section the simulation results are shown. Phase error is simulated considering a step acceleration of 10 g (against [2] works with acceleration steps up to 40 g, the required computational burden is large since several simultaneous correlation calculations and FFT computations are needed [3]). Because our measurement time is very short (about 100 msec), in this time range it is possible to assume the motion path of the vehicle is a line.

The designed loop has been simulated by MATLAB. Figure 4 shows phase error simulation result for the designed loop. In our simulation, carrier frequency is 1580 MHz, its power is −110 dBm,  dB/Hz, equivalent noise bandwidth is 60 Hz, and the UAV speed is up to 500 km/h. Comparing times of Figure 4 with of Figure 5 and of Figure 6 (that show the simulation results of [2] and [3], resp., for an identical experiment), we observe that our phase error width is almost 30–35% narrower (this corresponds to a shorter locking time) and its amplitude is about 35–45% smaller (this causes phase error that has less fluctuations after reaching the zero level).

Figure 4: Phase error in proposed design during the 10 g steps.

Figure 5: Phase error in [2].

Figure 6: Phase error in [3].

6. Conclusion

The performance of a tracking loop for high dynamic Doppler rates consisting of a third- order PLL assisted second-order FLL is considered. An optimal loop filter design method with reduced calculation complexity was also proposed. In this work as first step the authors analyzed the structure of the modified third-order PLL assisted second-order FLL; then the analysis results are used for deriving an optimal tracking loop. Simulation result confirms that a careful design of the loop has tracking capacity up to acceleration steps of 10 g, so as to reduce the computation complexity.

The main advantages of the proposed loop are its simplicity for a digital (FPGA) implementation and a better performance with respect to similar solution proposed previously.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

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