Novel designs of current-mode Ternary minimum (AND) and maximum (OR) are proposed in this paper based on Carbon NanoTube Field Effect Transistors (CNTFET). First, these Ternary operators are designed separately. Then, they are combined together in order to generate both outputs concurrently in an integrated design. This integration results in the elimination of common parts when both functions are required at the same time. The third proposed current-mode integrated circuit generates both ternary operators with the usage of only 30 transistors. The new designs are composed of three main parts: (1) the part which converts current to voltage; (2) threshold detectors; and (3) the parallel paths through which the output current flows. Unlike the previously presented structure, there is no need for any constant current source within the new designs. This elimination leads to less static power dissipation. The second proposed current-mode segregated Ternary minimum operates 43% faster and consumes 40% less power in comparison with a previously presented structure.
1. Introduction
In current-mode logic (CML), logic levels are represented by current levels. It has several advantages over voltage-mode logic (VML). The merits include (1) simple wiring of the currents, making linear sum operation easier and reducing the number of active devices [1]; (2) the ease of circuit expansion [2]; (3) the usage of the direction of current as the explanation of sign, which eliminates the requirement of sign bit [1]; (4) lower noise sensitivity [3]; (5) scaling and copying the currents with a simple current mirror circuit [4]; and, last but not least, (6) high-speed operation [4]. However, despite its several advantages, high static power consumption is the main drawback of CML.
Current-mode circuits are traditionally implemented by either bipolar (bipolar CML) or MOS (MCML) devices. MCML is preferred for mixed analog-digital signal environments due to high power consumption of bipolar transistors and higher supply noise immunity of MOS devices [3]. Although the latter has been the superior technology for implementing energy-efficient circuits for many years, their suitability in today’s nanometer VLSI industry is gradually fading away. This is mainly because of several critical challenges of MOS devices in nanoranges such as very high leakage currents, high power density, large parametric variations, and decreased gate control [5]. To overcome these difficulties, Carbon NanoTube Field Effect Transistor (CNTFET) is considered as the most promising successor to the MOS technology in the near future. This is mainly because of its intrinsic similarities to current technology. In addition, it benefits from the same motility of both n-type and p-type CNTFET devices, high-speed operation, low power consumption, and the realization of desired threshold voltage, which is a great feature in multiple-valued logic (MVL) circuitry [6].
MVL is an approach that utilizes more than two logic levels, while Binary logic computations are based on two values (“0” and “1”). MVL circuits benefit from fewer interconnections and pinouts, less area dissipation, and higher parallel and serial communication rates [1]. MVL is also known as an alternative design technique to Binary circuits, where the amount of interconnections is becoming a serious challenge. The huge amount of wires inside today’s nanoscale chips adds undesirable parasitic effects, reduces noise tolerance, dissipates more power, and restricts the routing and placement processes of logic elements [7–9]. The increment of logic levels can be considered as a solution to these difficulties and limitations. MVL circuits will play an important role in the next generation of electronic systems [1]. The most efficient MVL system, which leads to less product cost and complexity than Binary, is Ternary logic [7].
In this paper, new Ternary minimum (Logical AND) and maximum (Logical OR) circuits are proposed. They are based on CNTFET technology and CML design technique. They are fundamental operators in mathematical and logical components and computational units such as Arithmetic Logic Unit (ALU). Since both operators are required at the same time in most processors, their circuits are combined together to share the common parts and reduce transistor-count. The new circuits are based on mixed current and voltage logics. The usage of constant current source is avoided in the new designs. Therefore, power dissipation is reduced dramatically in comparison with the previously presented structure.
The rest of the paper is organized as follows: Section 2 reviews the previously presented current-mode MVL-based works in the literature. The transistor-level implementation of the previous design is also presented in this section. New current-mode Ternary Min/Max circuits are proposed in Sections 3 and 4. Simulation results and comparisons are brought in Section 5. Finally, Section 6 concludes the paper.
2. Literature Review
New minimum and maximum circuits have been presented in [10–12] for fuzzy logic. They are based on linear addition and subtraction of input currents, and they benefit from design simplicity and low transistor-count. Although it is apparently possible to use them in any MVL system, they have not been particularly designed for Ternary logic or any other digital systems. As a result, they fail to refresh and fortify incomplete signals. One of the major features of circuits in discrete systems is the ability of generating full-swing outputs in spite of non-full-swing input signals. Therefore, the employment of these fuzzy circuits [10–12] in digital systems is neither suitable nor practical.
Some current-mode structures have been previously presented in [13] for implementing signed Ternary functions. A comparable method has been used in [14] to design an unsigned Ternary circuit, which is the main objective in this paper. The previous Ternary maximum and minimum circuits, presented in [14], are shown in Figures 1(a) and 1(b), respectively. These structures utilize constant independent current sources as threshold detectors. In case the input current (a or b) is less than the constant one (the threshold), the rest of the current charges the gate capacitor of a p-type transistor, turning it off. If the amount of input current is more than the constant one, the transistor, whose gate capacitor is discharged, switches on. The transistor-level implementation of constant independent current sources, presented in [15], is used in this paper for simulation purpose (Figure 1(c)).
The previously presented circuits, (a) Ternary maximum [14], (b) Ternary minimum [14], (c) constant independent current source (transistor-level implementation) [15].
In the unsigned Ternary logic, there are three positive logic values, 0,1,23. They are represented in current-mode logic by different current levels. The unit current of 8 μA is considered in this paper to represent logic value “1”. Therefore, the logic value “2” is implemented by 16 μA, while no current flows when logic value is “0”.
The final representation of the previously presented Ternary Min and Max are shown in Figure 2, where each transistor is marked with three values (numbers). They indicate the diameter of CNTs (DCNT), the number of nanotubes under the gate terminal (Tube), and the pitch parameter. These designs require constant currents of 4 μA, 8 μA, 12 μA, and 28 μA as threshold detectors, whose transistor-level implementations are included in the figures. In addition, variable input currents (a and b) are duplicated by current mirrors since two copies of them are needed in each circuit.
The previous current-mode circuits [14], (a) previous Ternary maximum (Previous TMax), (b) previous Ternary minimum (Previous TMin).
3. The Proposed Current-Mode Segregated Ternary Operators (CSTO)
Logical AND and OR are among the most essential and fundamental operators in digital electronics. They are, respectively, equal to the minimum and maximum mathematical functions regardless of what MVL system is used. Their function in Ternary logic is shown in Table 1. In this section, new Ternary Min and Max circuits are proposed separately. They are based on a technique where input currents are converted to voltage. Then, threshold detectors control the switching activity of the transistors, which are situated on the output paths. A unit of current (8 μA) flows through each output path in case all of the related transistors are switched on. If the output value equals “2”, the currents of two different paths are joined in order to increase the amount of current to 16 μA.
The truth table of Ternary minimum and maximum.
a
b
∑in
Minimum
Maximum
0
0
0
0
0
0
1
1
0
1
0
2
2
0
2
1
0
1
0
1
1
1
2
1
1
1
2
3
1
2
2
0
2
0
2
2
1
3
1
2
2
2
4
2
2
In this section, the segregated strategy is followed. Then, the separated designs are combined together to achieve an integrated circuit in the next section.
3.1. The First Approach with a Current Mirror in the Last Part
The first proposed CML Ternary Min circuit is shown in Figure 3, where each transistor is marked with three values (numbers). As mentioned earlier, the numbers indicate the diameter of CNTs (in nanometer), the number of nanotubes under the gate terminal, and the pitch parameter (in nanometer). For example, there are eight nanotubes (Tubes = 8) with the diameter of 1.48 nm (DCNT = 1.48 nm) under the gate of T1. The distance between the centers of two adjacent CNTs is also 14 nm (Pitch = 14 nm).
The first proposed Current-mode Segregated Ternary Min (CSTMin1) with the current mirror in the last part.
There are two input currents, a and b. The proposed approach is on the basis of the sum of input currents. Unlike VML, it is as simple as connecting the wires (a and b) to achieve their linear addition in CML (a+b). Then, the summation is converted to voltage by means of a resistor. A diode-connected transistor (T9) is used as a resistor to make this conversion possible. To obtain higher resistivity, channel (Lg) and doped CNT source- (Lss) and drain-side (Ldd) extension regions for this transistor have been lengthened by 90 nm. The longer the channel is, the more it resists. This increment of channel length does not slow the operation because these converting transistors are not situated along the critical path of the cell.
The input currents (a and b), themselves, have to be converted to voltage as well. The transistors T4 and T8 are responsible for this purpose (for these two transistors: Lg=Lss=Ldd=100 nm). However, it is not feasible to take branches from the input currents due to the fact that the amount of current is divided. In CML, currents must be mirrored in case another copy it is required. In Figure 3, T2 and T3 (T6 and T7) duplicate the input current a (b) twice. In order to have the exact copy, they must have the same dimensions as T1 (T5). This part of the circuit (T1 to T9) is repeated in all of the proposed designs in this paper.
After the conversion, threshold detectors (TDs) control the switching activity of the rest of the transistors. Threshold detectors are in fact inverters with shifted voltage transfer characteristic (VTC) curves. There is only one TD in the first proposed Ternary Min circuit. The turning point of this TD is set 3.5/4 (Figure 3). It means that the output of this inverter is “0” only if the sum of input variables becomes the largest amount, four (∑in = 4).
The last part of the circuit, which determines the output value, is the most important one. It contains different paths, through which the output currents flow. The dimensions of the transistor(s) on a specific path have to be set properly so that exactly the unit current of 8 μA flows in each path in case the related transistor(s) is/are switched on. The threshold voltage of T12 and T13 is set properly so that they switch on if a≥1 and b≥1, respectively. T15 copies the current to the output node (Min). In case both input variables equal logic value “2” (∑in = 4), the threshold detector switches T16 on, and another unit of current is added to the previous one. Hence, the total current reaches 16 μA (Min = “2”).
The same approach is used to design the first proposed CML Ternary Max circuit (Figure 4). The threshold voltage of T16 is set “low.” Therefore, it switches on as soon as ∑in becomes greater than zero (∑in ≥ 1). T17 lets the current flow until ∑in reaches four (∑in ≤ 3). Consequently, the path is active in case 1 ≤ ∑in ≤ 3. T19 copies the same current to the output node (Max). There are two other parallel paths, constructed by the transistors T20 and T21. In case only one of the inputs is “2” (2 ≤ ∑in ≤ 3), a unit of current is added to the previous one (the copied one). If both are “2” (∑in = 4), the former path is inactive and the added transistors (T20 and T21) generate 16 μA current through two parallel paths.
The first proposed Current-mode Segregated Ternary Max (CSTMax1) with the current mirror in the last part.
3.2. The Second Approach without the Usage of Current Mirror in the Last Part
The second approach is almost the same as the first one except that the current mirror in the third part of the circuit is eliminated and the final currents are only generated by the p-type transistors. The second proposed CML Ternary Min and Max circuits are shown in Figures 5 and 6, respectively. In Figure 5, T16 and T17 function exactly the same way as T12 and T13 in Figure 3. However, the path consists of only two transistors, one transistor fewer than the first approach, where current flows through two n-type transistors and a p-type one. The fewer transistors a path has, the more precise the amount of current is. In addition, the critical path shortens and the entire circuit becomes more robust.
The second proposed Current-mode Segregated Ternary Min (CSTMin2) without the usage of current mirror in the last part.
The second proposed Current-mode Segregated Ternary Max (CSTMax2) without the usage of current mirror in the last part.
In Figure 6, T20 and T21 are considered as the replacements of T16 and T17 in Figure 4. They let the current flow in case 1≤∑in≤3. Although it is possible to connect the sum of input currents directly to the gate of T21, it increases robustness if the activity of T21 is controlled by a TD circuit. The full-swing output signal of a TD makes the following transistor switch on (or off) completely. In addition, there is no need to set the threshold voltage of this transistor precisely. It could have the same dimensions as T20. It results in a simpler transistor sizing procedure as well. It is worth mentioning here that the threshold voltage of the CNTFET is an inverse function of DCNT [16].
4. The Proposed Current-Mode Integrated Ternary Operators (CITO)
In some applications such as within the Arithmetic Logic Unit (ALU), both operators (AND and OR) are required at the same time. In this section, the previous segregated circuits are combined together in order to eliminate the common parts. The first proposed integrated circuit is shown in Figure 7. It is in fact the combination of CSTMin1 (Figure 3) and CSTMax1 (Figure 4), unless TDs are employed extensively to have a robust and accurate design. The common parts are the transistors which make the current to voltage conversion happen (T1 to T9) and the inverter with the turning point of 3.5/4.
The first proposed Current-mode Integrated Ternary Min and Max (CITMin/Max1) with the current mirrors in the last parts.
It is also possible to share the n-type transistors (T28/T29 and T33/T34). It leads us to the second integrated design (Figure 8). While the Min circuit remains unchanged, the functionality of the Max circuit is summarized as follows (though a set of conditions):
If a≥1 and b≥1: T26 and T27 switch on. A unit of current is copied to the both outputs (Min and Max).
If ∑in ≥ 3: T40 switches on. Another unit of current is added.
If a = “0” and b≥1∣b = “0” and a≥1: either (T35 and T36) or (T37 and T38) are ON and a unit of current flows.
If a = “0” and b = “2” ∣ a = “2” and b = “0”: either (T31 and T32) or (T33 and T34) are ON and another unit of current is added to (3). The output becomes “2”.
The last design (Figure 9) is the combination of the second proposed segregated designs, CSTMin2 (Figure 5) and CSTMax2 (Figure 6). It has the fewest number of transistors among the integrated designs. It generates both outputs with the usage of only 30 transistors. Figure 10 shows the signal waveforms of this last design. The input pattern includes 72 transitions. The output signals are generated at the same time, and their values are exactly 0 μA, 8 μA, and 16 μA, representing logic values “0”, “1”, and “2”.
The second proposed Current-mode Integrated Ternary Min and Max (CITMin/Max2) with a shared current and the current mirrors in the last parts.
The third proposed Current-mode Integrated Ternary Min and Max (CITMin/Max3) without the usage of current mirrors in the last parts.
Input and output waveforms of CITMin/Max3.
5. Simulation Results
All of the proposed designs as well as the previous ones (Figure 2) are simulated with Synopsys HSPICE and 32 nm CNTFET technology file [17, 18]. The simulations are carried out in 1 V power supply with 1 GHz operating frequency at room temperature. The complete input pattern including 72 transitions (Figure 10) is fed to the circuits to reveal the worst-case delay. During all transitions, the average power consumption is measured. The energy consumption (also known as PDP) is the multiplication of the maximum delay time and the average power consumption [16]. The average static power is also measured while the inputs are kept unchanged. The entire nine possible different input patterns (Table 1) are fed to the circuits to measure stand-by power dissipation. The average amount is reported as the static power.
The simulation results are exhibited in Table 2. In general, Max circuits consume more power than Min ones do. This is mainly because the output function is more likely to be “0” in Ternary AND than Ternary OR (Table 1). To talk literally, when applying a random input pattern, the probability of Ternary maximum being “0” is only 1/9, while Ternary minimum has the same value in most cases (5/9). Therefore, less current flows in a Ternary Min circuit.
The initial simulation results.
Designs
Delay (psec) TMin
Delay (psec) TMax
Average power (μW)
PDP (fJ)
Static power (μW)
Number of transistors
Previous TMin
19.64
—
72.56
1.42
72.94
19
CSTMin1
14.23
—
46.92
0.66
47.52
16
CSTMin2
11.17
—
43.19
0.48
43.71
18
Previous TMax
—
14.93
75.62
1.12
76.06
19
CSTMax1
—
13.60
56.73
0.77
57.51
21
CSTMax2
—
13.71
50.40
0.69
51.09
23
CITMin/Max1
18.48
20.68
65.06
1.34
65.69
38
CITMin/Max2
18.11
21.38
58.53
1.25
59.06
40
CITMin/Max3
17.57
18.82
54.84
1.03
55.55
30
The proposed designs operate far more efficient than the previous ones. For example, the first and the second proposed segregated Ternary Min cells (CSTMin1 and CSTMin2) consume 25.64 μW (35%) and 29.37 μW (40%) less power than the previous one, respectively. Higher power consumption is mainly because of the constant current sources in the previous circuits. New designs are even faster, resulting in a great reduction in terms of PDP. Moreover, the second segregated design technique leads to less power consumption and higher efficiency due to the elimination of a few transistors and a parallel path. For instance, CSTMin2 operates 21% faster, consumes 8% less power, and has 35% higher performance (considering PDP) than CSTMin1. Eventually, the third integrated circuit (CITMin/Max3) has the highest performance in terms of energy. It generates both outputs with the fewest transistors needed.
Sensitivity to the variation of temperature is put under examination for the previous and some of the proposed designs. The amount of energy consumption (PDP) versus a wide range of ambient temperatures, from 0°C to 70°C, is plotted in Figure 11. The proposed designs show insignificant sensitivity to temperature variations.
PDP versus temperature.
One major advantage of CML over VML is that fan-out circuits do not cause speed degradation and performance loss for the current-mode circuits. This is due to the way that fan-out circuits are connected to a current-mode circuit. Instead of a direct connection, output currents are mirrored to the new branches (Figure 12). To test this capability, simulations are redone twice more. First, only the output load transistor is added to the proposed circuits. Then, four copies of the output current are also included in the examination. As it is demonstrated in Table 3, the existence of the output load transistor and the connection of the fan-out circuits do not increase cell delay. They do not add extra load to the output node. This is exactly in contrast with VML in which as the output load increases, voltage-mode circuits operate slower [6, 16].
Delay parameter of the proposed designs versus the output load(s).
Designs
Without any output loads
With the output load transistor
With the output load transistor and 4 copies of the output current
Delay (psec) TMin
Delay (psec) TMax
Delay (psec) TMin
Delay (psec) TMax
Delay (psec) TMin
Delay (psec) TMax
CSTMin1
14.23
—
14.44
—
14.40
—
CSTMin2
11.17
—
13.45
—
13.34
—
CSTMax1
—
13.60
—
13.79
—
13.80
CSTMax2
—
13.71
—
14.03
—
13.99
CITMin/Max1
18.48
20.68
18.81
21.31
18.76
21.20
CITMin/Max2
18.11
21.38
18.46
21.72
18.53
22.08
CITMin/Max3
17.57
18.82
17.76
19.27
17.71
19.33
The output current is mirrored in CML to be connected to the fan-out circuits.
Finally, as it was mentioned in Section 2, digital circuits must have the ability of refreshing incomplete signals. This is an absolute fact in all discrete MVL systems. Otherwise, the signal offset intensifies and propagates within the whole system and it causes information loss eventually. Figure 13 shows how the circuit CITMin/Max3 restores an incomplete input signal. This is the ability the fuzzy circuits like the ones presented in [10–12] do not have. As a result, they are not appropriate for any digital systems such as Ternary.
Signal restoration in CITMin/Max3, (a) Ternary minimum, (b) Ternary maximum.
6. Conclusion
In this paper, novel designs of current-mode Ternary Min and Max have been proposed. The new designs are based on mixed current and voltage logics, resulting in the elimination of constant independent current sources. Their elimination leads to higher performance for the proposed cells in comparison with the ones use constant current sources extensively as threshold detectors. The proposed CSTMin2 has approximately 66% higher efficiency than the previously presented design in terms of PDP. This paper also shows that, unlike VML, fan-out circuits have almost no effect on the delay parameter. Furthermore, Min circuits generally consume less power than the Max ones. This is due to the fact that the Ternary Min function is “0” in more input patterns than the Ternary Max one. For example, CSTMin2 consumes 7.21 μW less power than CSTMax2. Finally, the common parts could be easily integrated in order to combine two different circuits in CML. The integrated designs produce both Ternary minimum and maximum functions with almost the same speed.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
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